TW200527650A - Inductor and fabricating method thereof - Google Patents

Abstract

An inductor constructed on a substrate having a dielectric layer thereon is provided. The inductor includes a first inductor pattern, a second inductor pattern a third inductor pattern. The first inductor pattern is disposed on the dielectric layer, the second inductor pattern is disposed on the first inductor pattern and electrically connected to the first inductor pattern, and the third inductor pattern is disposed on the second inductor pattern and electrically connected to the second inductor pattern wherein the first inductor pattern, the second inductor pattern, and the third inductor pattern have similar pattern. Because the thickness of the inductor can be increased by multilevel inductor pattern, therefore a resistance of the inductor is reduced.

Description

200527650 V. Description of the invention (1) The technical field to which the invention belongs The present invention relates to a method and structure for manufacturing a semiconductor element, and more particularly to a method and structure for manufacturing an inductor element. Prior art In integrated circuits, inductive elements are an important element. These inductive element types are generally round or square spiral metal coils, and the application range of these inductive elements can be said to be quite wide. In the field of high-frequency applications, the quality requirements for inductive components are relatively high, which means that the inductive components applied in this field have a higher Q value. For example, in the application of wireless communication, the Q value of the inductive element must reach about 60. The above Q value is defined as follows: Q-^ 0L / R (l) where is the resonant angular frequency of the inductive element, R is the resistance of the inductive element, and L is the value of the inductive element of the metal coil. From Equation (1), it can be known that under the fixed L, the Q value will increase as the resonance angular frequency increases and / or the resistance decreases, where the resistance is proportional to the square of the current density, so the method to improve the Q value One is to increase the cross-sectional area of the metal coil to reduce the current density of the metal coil. In this way, the resistance of the metal coil is reduced, and the purpose of increasing the Q value is achieved. Therefore, in the semiconductor manufacturing process, if you want to increase the cross-sectional area of the metal wire to make high-Q inductance components, you can increase the width of the metal wire.

11487TWF.PTD Page 8 200527650 V. Description of Invention (2) Completed. However, if the width of the metal wire is too large, the charge tends to be concentrated at the corners of the metal wire, so that the increased cross-sectional area of the metal wire cannot achieve the effect of reducing the current density of the metal wire, and it cannot improve the metal wire. The Q value of the composed inductive element. Therefore, the Q value of an inductive element generally manufactured by a semiconductor process can only be about 10 at most. Moreover, most of the inductive components are arranged under the protective layer of the chip, so the inductive components are very close to the silicon substrate (<10 mm), so the silicon substrate will become a conductor at high frequencies using high-frequency components. , And consume a lot of energy, so that the quality of the inductive element is reduced. Moreover, although it is conventionally proposed to form a three-dimensional inductive element composed of metal wires / interlayer windows / metal wires through a metal interconnect process, this inductive element also has the problem of being too close to the silicon substrate. Furthermore, the interposer The layer of the window layer is limited by the process, and cannot be made into a pattern similar to the metal wire layer. Only a large number of plugs can be formed to connect the upper and lower metal wire layers, so the Q value of the inductor element cannot be further improved. Therefore, how to solve the above problems and improve the quality of the inductive element and its Q value are the concerns of the current manufacturing process. In view of this, the object of the present invention is to provide a method for manufacturing an inductive element, which can reduce the impedance of the inductive element and improve the Q value of the inductive element without additional process steps. Another object of the present invention is to provide an inductive element structure, which can make the inductive element structure farther away from the silicon substrate, so as to reduce the silicon substrate to the inductor element.

11487TWF.PTD Page 9 200527650 V. Explanation of the invention (3) Magnetic permeability interference caused by the item to improve chip performance. It is still another object of the present invention to provide an inductive element structure. The inductive element has a multilayer structure and the entire inductive element has a uniform thickness, so that the Q value of the inductive element can be increased. The invention provides a method for manufacturing an inductive element. This method is structured on a substrate. At least a first dielectric layer is formed on the substrate. The method for manufacturing the inductive element is to first form a patterned layer on the first dielectric layer at the same time. The first metal layer and the first inductance pattern. Then, a patterned second dielectric layer is formed on the first dielectric layer to cover the first metal layer, the first inductance pattern, and the first dielectric layer, and the second dielectric layer has a plurality of first openings. And a plurality of second openings, wherein the first opening exposes the first metal layer, and the second opening exposes the first inductance pattern. Then, metal is filled in the first opening and the second opening to form a second metal layer in the first opening at the same time, and a second inductance pattern is formed in the second opening. The second metal layer is connected to the first metal. Layers are electrically connected, and the second inductance pattern is electrically connected to the first inductance pattern. Next, a patterned third metal layer is formed on the second metal layer, and at the same time, a third inductance pattern is formed on the second inductance pattern, wherein the third metal layer is electrically connected to the second metal layer, and the third inductance is The pattern is electrically connected to the second inductance pattern, and the first inductance pattern, the second inductance pattern, and the third inductance pattern have similar patterns. Therefore, it can be known from the above process that the present invention uses a multilayer inductor pattern to increase the thickness of the metal wire of the inductor element, which can reduce the resistance value of the inductor element and increase its Q value. In addition, in the process of the present invention,

11487TWF.PTD Page 10 200527650 V. Description of the invention (4) The process of the inductive element can be completed by adding additional process steps, so the method of the present invention can be said to be quite simple. The present invention proposes an inductive element structure on a substrate, and at least a planarized dielectric layer is disposed on the substrate. The inductor element structure includes a first inductor pattern, a second inductor pattern, and a third inductor pattern, wherein the first inductor pattern is disposed on the dielectric layer. In addition, the second inductance pattern is disposed on the first inductance pattern, and the second inductance pattern is electrically connected to the first inductance pattern. In addition, the third inductor pattern is disposed on the second inductor pattern, and the third inductor pattern is electrically connected to the second inductor pattern. The first inductor pattern, the second inductor pattern, and the third inductor pattern have similar patterns. In the manufacturing method and structure of the above-mentioned inductance element, the first inductance pattern, the second inductance pattern, and the third inductance pattern are individually formed simultaneously with the uppermost metal layer, metal plug, and metal pad of the multilayer metal interconnect structure. In the manufacturing method and structure of the above-mentioned inductor element, the first inductor pattern, the second inductor pattern, and the third inductor pattern form a three-dimensional inductor structure. For a symmetrical inductor structure, the inductor element has a crossover overlap. Region, and in order to avoid a short circuit of the inductor element, the first inductor pattern and the third inductor pattern are not connected through the second inductor pattern at the overlapping area of the inductor pattern. The invention proposes another method for manufacturing an inductive element, which is structured on a substrate, at least a first dielectric layer is formed on the substrate, and the method is to simultaneously form a patterned first metal in the first dielectric layer. Layer with

11487TWF.PTD Page 11 200527650 V. Description of the invention (5) A first inductor pattern, and then a patterned second dielectric layer is formed on the first dielectric layer to cover the first metal layer and the first inductor pattern And the first dielectric layer, and the second dielectric layer has a plurality of first openings and a plurality of second openings, wherein the first opening exposes the first metal layer and the second opening exposes the first inductance pattern, A second metal layer is formed on the second dielectric layer to fill the first opening, and a second inductance pattern is formed on the second dielectric layer to fill the second opening. The second metal layer is The first metal layer is electrically connected, and the second inductance pattern is electrically connected to the first inductance pattern. In the above-mentioned manufacturing method of the inductance element, the first inductance pattern, the second inductance pattern, and the third inductance pattern are formed separately from the uppermost metal layer, the metal plug, and the metal pad of the multilayer metal interconnection structure, and the metal The plug and the metal pad (the second inductance pattern and the third inductance pattern) are formed in the same deposition and lithography etching steps. In the manufacturing method of the above-mentioned inductance element, the first inductance pattern and the second inductance pattern form a three-dimensional inductance structure. For the symmetrical inductance structure, the inductance element has a crossover overlapping area, and in order to avoid inductance The component is short-circuited so that the first inductance pattern and the second inductance pattern are not connected to each other at the overlapping area of the inductance pattern. Therefore, it can be known from the manufacturing method and structure of the inductive element that the present invention uses multiple layers of inductive patterns to increase the thickness of the metal wire of the inductive element, so that the resistance value of the inductive element can be reduced, and the Q value can be increased. quality. Moreover, since each layer of the multilayer inductance element of the present invention has a phase

11487TWF.PTD Page 12 200527650 V. Description of the invention (6) Similar pattern, so that the entire inductance element has a uniform thickness, which can further effectively increase its Q value. In addition, this inductance element can be manufactured together with the metal welding process, so the formed inductance element is farther away from the substrate than before, so the magnetic permeability interference caused by the substrate to the inductance element can be reduced to improve the chip performance. In addition, since the inductance pattern corresponding to the metal plug and the metal pad portion of the present invention can be completed in the same deposition and lithography etching steps, the process is simplified. Furthermore, since the inductance pattern corresponding to the metal plug and the metal pad portion is made of the same material, the contact resistance caused by the contact of different materials can be reduced, thereby increasing the Q value of the inductance element. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, several preferred embodiments are exemplified below, and in conjunction with the accompanying drawings, detailed descriptions are as follows: Embodiments First Embodiment First FIG. 2 is a schematic top view of a structure for forming an inductive element according to a first embodiment of the present invention; FIG. 2A to FIG. 2C are schematic cross-sectional views of the manufacturing process from I to Γ in FIG. 1; 3A to 3C are schematic cross-sectional diagrams of the manufacturing process from II to II 'in Figure 1, in which the areas labeled 1 0 1, 1 0 3, and 1 0 5 shown in Figure 1 are related to Figs. 2A to 2C and Figs. 3A to 3C correspond to each other, and the region 105 refers to a portion where the region 101 and the region 103 overlap. And in this embodiment, its disclosure

11487TWF.PTD Page 13 200527650 V. Description of the Invention (7) It is shown as a symmetrical circular spiral inductor element, and this inductor element has a crossover overlapping area. Please refer to FIG. 1, FIG. 2 A and FIG. 3 A at the same time. First, a substrate 1 0 0 is provided for the production of the inductive element. At least a dielectric layer 102 is formed on the substrate 100. The material is, for example, an oxide. Silicon, silicon nitride, low dielectric constant materials and other commonly known dielectric materials are formed by, for example, a chemical vapor deposition method, first depositing a dielectric layer 102 on a substrate 100, and then chemically The mechanical polishing method performs a planarization step. Those skilled in the art should know that the dielectric layer 102 may have a structure of a plurality of layers, and that a plurality of elements and metal interconnections may be formed on the substrate 100 and the dielectric layer 102. Then, a patterned metal layer 104a and an inductor pattern 104b are simultaneously formed in the dielectric layer 102. The top view of the inductor pattern 104b is shown in FIG. 4A, and the metal layer 104a is, for example, a substrate 100 on the substrate 100. The uppermost metal layer of the multilayer metal interconnection structure, that is, during the metal interconnection process, the inductance pattern 104b can be formed in the same process. In addition, the material of the metal layer 104a and the inductor pattern 104b is, for example, copper, and the formation method thereof is, for example, a generally known metal damascene process, and a patterned opening is first formed in the dielectric layer 102 ( (Not shown), and then fill a metal material into the opening to form a patterned metal layer 104a and an inductor pattern 104b. Next, referring to FIGS. 1, 2B, and 3B at the same time, a patterned dielectric layer 106 is formed on the dielectric layer 102 to cover the metal layer 104a, the inductor pattern 104b, and the dielectric layer 102. In addition, the dielectric layer 106 further has a plurality of openings 10 8 a and 10 8 b, wherein the openings 10 8 a expose a metal layer.

11487TWF.PTD Page 14 200527650 V. Description of the invention (8) 1 0 4 a and the opening 1 0 8 b exposes the inductance pattern 1 0 4 b. In addition, a method of forming the dielectric layer 106 is, for example, comprehensively forming a dielectric layer (not shown) on the dielectric layer 102 to cover the metal layer 104a, the inductor pattern 104b, and the dielectric layer 102. . Chemical mechanical grinding is then performed to flatten the dielectric layer completely. Then, the dielectric layer is patterned using a conventional lithographic etching process to define a dielectric layer 106 having a plurality of openings 108a, 108b. In addition, it is worth mentioning that in order to avoid short-circuiting of the inductive element in the design, when the opening 1 0 8 b is formed by patterning the dielectric layer, openings 1 0 8 b are not formed in the areas 1 0 1 and 1 0 3. , Which means that the uppermost inductance pattern (not shown) formed in the subsequent process will not connect the inductance pattern 104b in the area 101 and the area 103 through the inductance pattern (not shown) in the middle layer, except for area 1 Except for 0 1 and area 1 0 3, the pattern trace of the opening 1 0 8 b is similar to that of the inductance pattern 1 0 4 b. After that, please continue to refer to FIG. 1, FIG. 2 B and FIG. 3 B at the same time, and fill metal into several openings 10 8 a and 10 8 b to form a metal layer in openings 10 8 a at the same time. 110a, and an inductance pattern 110b is formed in the opening 108b. The formed metal layer 1 1 0 a is used as a metal plug, for example, and is electrically connected to the metal layer 104 a. In addition, the manner of forming the inductor pattern 1 1 0 b and the metal layer 1 1 0 a is, for example, forming a metal layer (not shown) in the openings 108 a and 108 b and on the dielectric layer 106. The metal material is, for example, Yan, and The formation method is, for example, a low-pressure chemical vapor deposition method or a sputtering method. After that, a planarization step is performed to remove the metal material outside the openings 10 8 a and 10 8 b to form

11487TWF.PTD Page 15 200527650 V. Description of the invention (9) Metal layer 110a and inductor pattern 110b. Therefore, the inductance pattern 110b is formed simultaneously with the metal layer 110a (for example, a metal plug) in the same step. Moreover, the above view of the formed inductor pattern 110b is shown in FIG. 4B, which is electrically connected to the inductor pattern 104b, and in addition to avoiding shorting of the inductor element in the design, it is near the overlapping area of the metal wire ( Regions 101, 103, and 105) except that the inductor pattern 110b is not formed, the inductor pattern 110b has a pattern similar to that of the inductor pattern 110b. Next, please refer to FIG. 1, FIG. 2C and FIG. 3C at the same time, form a patterned metal layer 112 a on the metal layer 110 a, and simultaneously form an inductance pattern 1 1 2 b on the inductance pattern 1 1 0 b, where The metal layer 1 1 2 a is, for example, used as a metal pad, and is electrically connected to the metal layer 1 1 0 a. In addition, the material of the metal layer 1 1 2 a and the inductance pattern 1 1 2 b is, for example, aluminum, and the formation method thereof is, for example, forming a comprehensive metal layer (not shown) on the dielectric layer 106, and the formation method thereof For example, it is a physical vapor deposition method. Then, using a conventional lithography technique, the metal layer is patterned to form a metal layer 112a and an inductance pattern 112b. Therefore, the inductor pattern 112b is formed simultaneously with the metal layer 1 1 2a (for example, a metal pad) in the same step. Moreover, the above view of the formed inductor pattern 112b is shown in FIG. 4C, which is electrically connected to the inductor pattern 1 1 0b, and in addition to avoiding short circuit of the inductor element in the design, only in the region 105 and Except for the inductive pattern 112b formed in the area 103, the inductive pattern 112b has a pattern similar to the inductive patterns 1 1 0b and 1 0 4b. It is worth mentioning that the above-mentioned multilayered inductor patterns 104b, 110b

11487TWF.PTD Page 16 200527650 V. Description of the invention (ίο) and 1 1 2 b constitute a three-dimensional inductance structure, the top view of which is shown in Figure 1, and the area where the three-dimensional inductance structure crosses is heavy (region 105) It is composed of an inductor pattern 104b, a dielectric layer 106, and an inductor pattern 112b. In addition, the inductor pattern 104b and the inductor pattern 112b in this region 105 are not connected by the inductor pattern 1 1 0 b, and are overlapped by the cross-section of the three-dimensional inductor structure. The area is designed as described above. When the current flows along the three-dimensional inductor structure, the current flow will only flow along the first inductance pattern when the current flows through the crossover overlap area *, and only when the current flows through the crossover overlap area for the second time. Flowing along the third inductance pattern can avoid the short circuit of the inductance pattern in the cross-overlap region. In addition, the present invention is not limited to the above-mentioned process steps. The above-mentioned metal layers 110a, 112a, and the inductor patterns 110b, 112b formed at the same time can be completed by a conventional bimetal damascene process. Therefore, it can be known from the above process that the present invention uses multiple layers of the inductor pattern to increase the thickness of the metal wire of the inductive element, so that the resistance value of the inductive element can be reduced and its Q value can be increased. In addition, in the process of the present invention, no additional Adding process steps can complete the process of the inductive element, so the method of the present invention can be said to be quite simple. Furthermore, in the process of the present invention, the opening 1 0 8 b for forming the inductance pattern 1 1 0 b can be formed together with the opening 1 0 8 a for forming the plug of the metal pad, since the opening 1 0 8 a and 1 0 8 b are located at the uppermost layer of the metal interconnect structure, so there are fewer process restrictions, so that the opening 10 8 b can have a similar pattern to the inductor pattern 10 4 b. The following is the junction of the inductive element manufactured by the above process.

114S7TWF.PTD Page 17 200527650 V. Explanation of the invention (11) Structure, please continue to refer to Figure 1, Figure 2C and Figure 3C at the same time, where Figure 1 is the top view of the inductive element of the present invention Figure 2C is a cross-sectional view of Figure 1 along I to Γ, and Figure 3C is a cross-sectional view of Figure 1 along II to I Γ, where 1 0 1, 1 Regions 103 and 105 correspond to FIG. 2C and FIG. 3C, and region 105 refers to a portion where region 101 and region 103 overlap. The structure of the inductive element of the present invention is structured on a substrate 100, and at least a dielectric layer 102 is disposed on the substrate 100. The structure of the inductor element includes three layers of inductor patterns 104b, 11 Ob, and 112b. The inductor pattern 104b is disposed on the dielectric layer 102. The top view of the inductor pattern 104b is shown in FIG. 4A. A metal layer 104a is further disposed on the dielectric layer 102, that is, the metal layer 104a and the inductor pattern 104b. The metal layer 104a is disposed on the same film layer. The metal layer 104a is, for example, the uppermost metal layer of the multilayer metal interconnection structure on the substrate 100, and the material of the metal layer 104a and the inductor pattern 104b is, for example, copper. It is worth mentioning that, in the area 103, except for the area 105 intersecting with the area 101, the inductance pattern 104b is disposed, and the remaining area 103 has no inductance pattern 104b. In addition, the inductance pattern 1 1 0 b is disposed on the inductance pattern 1 0 4 b. The top view of the inductance pattern 110 b is shown in FIG. 4B. Except for the overlapping area, the inductance pattern 110 b and the inductance pattern 104 b have Similar patterns, and the inductor pattern 11 0 b is electrically connected to the inductor pattern 1 0 4 b. In addition, a metal layer 110a is further disposed on the metal layer 104a, that is, the metal layer 110a and the inductor pattern 110b are disposed on the same film layer. The metal layer 110a is, for example, a metal plug, and the metal layer 110a and the inductor Pattern 110b

"fine

11487TWF.PTD Page 18 200527650 V. Description of the invention (12) The material is, for example, tungsten. It is worth mentioning that there is no configuration of the inductor pattern 110b in the area 103 and the area 101 (including the area 105 that overlaps and overlaps). In addition, the inductor pattern 1 1 2 b is disposed on the inductor pattern 1 1 0 b. The top view of the inductor pattern 112 b is shown in FIG. 4C. Except for the overlapping area, the inductor pattern 112 b and the inductor patterns 110 b and 104 b have Similar patterns, and the inductance pattern 1 1 2 b is electrically connected to the inductance pattern 1 1 0 b. In addition, a metal layer 112a is further disposed on the metal layer 110a, that is, the metal layer 112a and the inductance pattern 112b are disposed on the same film layer, and the metal layer 1 1 2 a is, for example, a metal pad 1 1 4. It is worth mentioning that in the region 101, except for the region 105 intersecting and overlapping with the region 103, the inductance pattern 112b is disposed, and the other region 101 does not have the inductance pattern 112b disposed. In addition, the three-layered inductor patterns 104b, 110b, and 112b constitute a three-dimensional inductor structure, and the top view thereof is shown in FIG. 1, and the cross-overlap region (area 105) of the three-dimensional inductor structure is composed of inductors. The pattern 1 0 4 b, the dielectric layer 106 and the inductor pattern 112 b are formed, and the inductor pattern 104 b and the inductor pattern 112 b in this region 105 are not connected by the inductor pattern 110 b so that the inductor pattern does not occur in the overlapping area. Short circuit problem. Second Embodiment FIG. 5 shows a schematic top view of the structure of an inductive element according to the second embodiment of the present invention; FIG. 6A to FIG. 6C show the manufacturing process of III-III ′ in FIG. 5 Schematic cross-section. And in this embodiment, it is disclosed as a concentric spiral inductor element.

11487TWF.PTD Page 19 200527650 V. Description of the invention (13) Please refer to FIG. 5 and FIG. 6 A at the same time. The production of the inductance element is first provided with a substrate 200, and then at least a dielectric layer 202 is formed on the substrate 200, of which This material is, for example, generally known dielectric materials such as silicon oxide, silicon nitride, and low-dielectric-constant materials. A method for forming the material is, for example, a chemical vapor deposition method to deposit a dielectric layer 2 0 2 on a substrate 2 0 And then performing a planarization step by chemical mechanical polishing. Those skilled in the art should know that the dielectric layer 2 0 2 may have a structure of a plurality of layers, and that a plurality of elements and metal interconnections may be formed on the substrate 200 and the dielectric layer 202. Then, a patterned metal layer 204a and an inductor pattern 204b are simultaneously formed in the dielectric layer 202. The top view of the inductor pattern 204b is shown in FIG. 7A, and the metal layer 204a is, for example, a multilayer metal interconnect on the substrate 200. The uppermost metal layer of the structure, that is, during the metal interconnection process, the inductance pattern 204b can be formed in the same process. In addition, the material of the metal layer 2 0 4 a and the inductance pattern 2 0 4 b is, for example, copper, and the formation method thereof is, for example, a generally known metal damascene process. First, patterned openings are formed in the dielectric layer (not shown). ), And then fill a metal material into the opening to form a patterned metal layer 204a and an inductance pattern 204b. Next, referring to FIGS. 5 and 6B at the same time, a patterned dielectric layer 206 is formed on the dielectric layer 202 to cover the metal layer 204a, the inductance pattern 204b, and the dielectric layer 202. In addition, the dielectric layer 206 further includes a plurality of openings 208a, 208b, wherein the opening 208a is exposed to the metal layer 204a, and the opening 208b is exposed to the inductance pattern 204b, and the pattern of the opening 208b is related to the inductance pattern 20 The pattern of 4 b is similar, that is, a spiral opening 2 0 8 b is formed along the inductance pattern 2 0 4 b.

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V. Description of the Invention (14) In addition, the method for forming the dielectric layer 206 is, for example, comprehensively forming a dielectric layer (not shown) on the dielectric 202 to cover the two layers, The inductance pattern 204 and the dielectric layer 202. After that, a chemical machine 1 or abrasion is performed to flatten the dielectric layer. Then, using Xi Zuoyan's research, said: the branching lithography process is used to pattern this dielectric layer, so as to define the dielectric layer 206 with openings 208a and 208b. ’^ After several evenings, please continue to refer to Figure 5 and Figure 6 C at the same time.

A metal layer 2 1 0a and an electrical layer 210b are formed on the 2 0 6 to fill the openings 2 0 a and 2 0 8 b. The metal layer 210a is electrically connected to the metal layer 204a. The metal layer 212a in the opening and the metal layer '21 = composed 'on the dielectric layer 206 and the metal layer 2 1 2a in the opening 2 08a can be used as a metal plug, for example, the dielectric layer 2 0 The metal layer 2 1 4 a on 6 can be used as a metal pad, for example. The inductor pattern 210b can be regarded as an earlier inductor pattern, and can also be regarded as being formed by the inductor pattern 2 1 2 b in the opening 2 0 8 b and the inductor pattern 214 b on the dielectric layer 206 as in the first embodiment. Moreover, since the opening 208b has a pattern similar to the inductance pattern 2 0 4b, the formed inductance patterns 212b, 214b can also have a pattern similar to the inductance pattern 204b.

In addition, the manner of forming the inductance pattern 210b and the metal layer 210a is, for example, forming a metal layer (not shown) in the openings 208a, 208b and the dielectric layer 206, wherein the metal material is aluminum, and the forming method is, for example, Physical vapor deposition. Then, the conventional lithography technique is used to pattern the metal layer to form a metal layer 2 10 a (2 1 2 a, 2 1 4 a) and an inductor pattern 210 b (212 b, 214 b). Therefore, the inductance pattern 210b is related to

11487TWF.PTD Page 21 200527650 V. Description of the invention (15) The metal layer 210a is formed simultaneously in the same step. Similarly, since the present invention uses multiple layers of the inductor pattern to increase the thickness of the metal wire of the inductive element, the resistance value of the inductive element can be reduced and its Q value can be increased. In addition, in the process of the present invention, no additional increase is required. The process steps can complete the process of the inductive element, so the method of the present invention can be said to be quite simple. Moreover, in the process of the present invention, the opening 2 0 8 b for forming the inductance pattern 2 1 0 b can be formed together with the opening 208 a for forming the plug of the metal pad, because the openings 208 a and 208 b are It is located at the uppermost layer of the metal interconnect structure, so the process limitation is small, so that the opening 2 0 b can have a similar pattern to the inductance pattern 2 0 4 b. Furthermore, in this embodiment, since the metal layers 212a and 214a and the inductive patterns 2 1 2 b and 2 1 4 b formed at the same time can be completed in the same deposition and lithography etching steps, it is compared with the first embodiment. It can simplify the manufacturing process. Moreover, since the inductor patterns 212b and 214b are made of the same material, the contact resistance caused by the contact of different materials can be reduced and the Q value can be increased. Furthermore, since the inductance pattern 212b can be made of aluminum, the contact resistance can be reduced and the Q value can be increased compared with the case where tungsten is used in the first embodiment. The following is a description of the structure of the inductive element produced by the above process. Please continue to refer to FIG. 5 and FIG. 6 C at the same time, where FIG. 5 is a schematic top view of the inductive element of the present invention, and FIG. 6 C FIG. 5 is a schematic cross-sectional view taken along III to II Γ. The structure of the inductive element of the present invention is structured on a substrate 200. This base

11487TWF.PTD Page 22 200527650 V. Description of the invention (16) At least a dielectric layer 202 is arranged on the bottom 200. The structure of the inductive element includes an inductive pattern 2 0 4b and 21 Ob. Among them, the inductor pattern 204b is disposed on the dielectric layer 202. The top view of the inductor pattern 204b is not shown in FIG. 7A, and a metal layer 204a is further disposed on the dielectric layer 2Q2, that is, the metal layer 204a and The inductor pattern 204b is disposed on the same film layer. The metal layer 204a is, for example, the uppermost metal layer of the multilayer metal interconnect structure on the substrate 200, and the material of the metal layer 204a and the inductor pattern 204b is, for example, copper. The inductor pattern 210b is disposed on the inductor pattern 204b. The top view of the inductor pattern 210b is shown in FIG. 7C, and the inductor pattern 210b is electrically connected to the inductor pattern 204b. In addition, the &amp; metal layer 210a is further disposed on the metal layer 204a, and the metal layer 210a is disposed on the same film layer as the inductance pattern 210b. In this embodiment, the inductive pattern 2 1 0 b can be regarded as composed of the inductive pattern 2 1 2 b and the inductive pattern 2 1 4 b. 'From this viewpoint, the top view of the inductive pattern 212b is as shown in FIG. 7B. The top view of the inductor pattern 21213 is shown in FIG. 7C. Similarly, the metal layer 2 1 0 a can be considered to be composed of the metal layer 212 a and the metal layer 214 a 'wherein the metal layer 2128 is, for example, a metal plug, the metal layer 2 1 4a is, for example, a metal pad, and the metal layer 2 1 The materials of 0 a and the inductance pattern 2 1 0 b are, for example, Shao. Of course, the form of the above-mentioned inductance element is not limited to the symmetrical circular spiral pattern shown in FIG. 1 or the concentric circular spiral pattern shown in FIG. 5, and other forms such as a symmetrical square spiral pattern or a concentric square The spiral pattern f can also be completed using the present invention. Moreover, the symmetric circular spiral type inductance element in the first embodiment

11487TWF.PTD Page 23 200527650 5. In the description of the invention (17), the first inductance pattern, the second inductance pattern, and the third inductance pattern (¾ upper metal layer, metal plug, metal pad) are deposited by different depositions. It is formed by the manufacturing industry, but the present invention is not limited to this. The inductance element of the first embodiment can also be the same as the second embodiment, so that the second inductance pattern and the third inductance pattern (metal plug, metal pad) are the same. The deposition and lithographic etching steps are completed. Further, any form of the inductance element can be formed by the process disclosed in the first embodiment or the second embodiment. In summary, from the above structure, it can be known that the present invention uses multiple layers of inductive patterns to increase the thickness of the metal wire of the inductive element. This can reduce the resistance value of the inductive element and increase its Q value, thereby improving the quality of the inductive element. In addition, since each layer of the multilayer inductor element of the present invention has a similar pattern, the entire inductor element structure has a uniform thickness, which can further effectively increase its Q value. In addition, since this inductive element can be manufactured together with the process of forming metal pads, the structure formed is farther away from the substrate than before, so the magnetic permeability interference caused by the substrate to the inductive element can be reduced to improve the performance of the wafer. In addition, since the inductance pattern corresponding to the metal plug and the metal pad portion of the present invention can be completed in the same deposition and lithography etching steps, the process is simplified. Furthermore, since the inductance pattern corresponding to the metal plug and the metal pad portion is the same material, the contact resistance caused by the contact of different materials can be reduced, thereby increasing the Q value of the inductance element.

11487TWF.PTD Page 24 200527650 V. Description of the Invention (18) Although the present invention has been disclosed above with several preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art will not depart from the spirit of the present invention. Within the scope and scope, some changes and retouching can be made. Therefore, the scope of protection of the present invention shall be determined by the scope of the appended patent application.

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Brief Description of the Drawings Fig. 1 is a schematic view of a structure of an inductance element according to a first embodiment of the present invention. Figures 2A to 2C are the intentions of the first figure along I to I '. Figure μ shows Figures 3A to 3C are schematic diagrams of the jealousy of Figure 1 along I I to I I ′. &quot; Figures 4A to 4C of the Wang section are schematic top views of the inductor pattern of Figure 1, where Figure 4A is the inductor pattern 104a, Figure 4B is the inductor pattern 'll0b, and Figure 4C is Inductive pattern 112b. ^ Figure 5 is a schematic top view of the structure of an inductance element according to a second embodiment of the present invention. Figures 6A to 6C are the manufacturing process of Figure 5 along I I I to I I Γ. It is not intended. 7A to 7C are schematic top views of the inductance pattern in FIG. 5, where FIG. 7A is the inductance pattern 20 4a, FIG. 7B is the inductance pattern 212b, and FIG. 7C is the inductance pattern 214b. [Illustration of drawing symbols] 1 00, 2 0 0: substrates 1 0 1, 1 0 3, 1 0 5 · • areas 102, 106, 202, 206: dielectric layers 104a, 110a, 112a, 204a, 210a, 212a 214a: Metal layers 104b, 110b, 112b, 204b, 210b, 212b, 214b: Inductive patterns ⑩ 108a, 108b, 208a, 208b: Opening

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Claims (1)

200527650 VI. Scope of patent application 1. A method for manufacturing an inductive element, which is structured on a substrate. At least a first dielectric layer is formed on the substrate. The method includes: simultaneously forming a pattern in the first dielectric layer. Forming a first metal layer and a first inductance pattern; forming a patterned second dielectric layer on the first dielectric layer to cover the first metal layer, the first inductance pattern, and the first A dielectric layer, and the second dielectric layer has a plurality of first openings and a plurality of second openings, wherein the first openings expose the first metal layer and the second openings expose the first opening An inductance pattern; filling a metal in the first openings and the second openings to form a second metal layer in the first openings at the same time, and forming a first in the second openings Two inductance patterns, wherein the second metal layer is electrically connected to the first metal layer, and the second inductance pattern is electrically connected to the first inductance pattern; and forming a patterned pattern on the second metal layer A third metal layer, and A third inductance pattern is formed on the second inductance pattern, wherein the third metal layer is electrically connected to the second metal layer, and the third inductance pattern is electrically connected to the second inductance pattern. The first inductance pattern, the second inductance pattern, and the third inductance pattern have similar patterns. 2. The method for manufacturing an inductive element according to item 1 of the scope of the patent application, wherein the first metal layer includes a multilayer metal interconnect on the substrate. The uppermost metal layer of the structure. 3 · The manufacturer of the inductive element as described in item 1 of the patent application ’ 11487TWF.PTD Page 27 200527650 VI. Patent Application Law, wherein the second metal layer includes a metal plug. 4. The method for manufacturing an inductive element according to item 1 of the scope of the patent application, wherein the third metal layer comprises a metal solder. 5. The method for manufacturing an inductive element according to item 1 of the scope of patent application, wherein the inductive element comprises a symmetrical circular spiral inductor element or a concentric circular spiral inductor element. 6 · The manufacturing method of the inductive element according to item 1 of the scope of the patent application, wherein the first inductance pattern, the second inductance pattern and the third inductance pattern form a three-dimensional inductance structure, and the three-dimensional inductance structure has a The cross-overlap region, and in the cross-overlap region, the first inductance pattern and the third inductance pattern are not connected by the second inductance pattern, so that when a current flows along the three-dimensional inductance structure, it flows for the first time. It only flows along the first inductance pattern when passing through the cross-overlapping region, and only flows along the second inductance pattern when passing through the cross-overlap region a second time. 7. An inductive element, which is structured on a substrate with at least one dielectric layer disposed on the substrate. The structure includes: a first inductive pattern disposed on the dielectric layer; a second inductive pattern disposed on On the first inductance pattern, and the second inductance pattern is electrically connected to the first inductance pattern; and a third inductance pattern, disposed on the second inductance pattern, and the third inductance pattern is connected to the first inductance pattern The two inductance patterns are electrically connected, wherein the first inductance pattern, the second inductance pattern, and the third inductance pattern have similar patterns. 8. The inductive element according to item 7 in the scope of patent application, wherein the 11487TWF.PTD Page 28 200527650 VI. Scope of Patent Application-An inductor pattern is the same layer as one of the first metal layers patterned on the substrate, and the first metal layer includes a multilayer metal interconnect structure on the substrate Topmost metal layer. 9. The inductive element according to item 7 of the scope of patent application, wherein the second inductive pattern is the same layer as a patterned second metal layer on the substrate, and the second metal layer includes a metal plug. 10. The inductive element as described in item 7 of the scope of the patent application, wherein the third inductive pattern is the same layer as a patterned third metal layer on the substrate, and the third metal layer includes a metal pad . 1 1. The inductive element according to item 7 of the scope of patent application, wherein the inductive element comprises a symmetrical circular spiral inductor element or a concentric circular spiral inductor element. 1 2. The inductive element according to item 7 of the scope of the patent application, wherein the first, second and third inductive patterns form a three-dimensional inductive structure, and the three-dimensional inductive structure has a cross-overlap. Area, and at the area where the parent fork is heavy, the first inductor pattern and the second inductor pattern are not connected by the second inductor pattern, so that when current flows along the three-dimensional inductor structure, the first time It only flows along the first inductance pattern when passing through the crossover overlapping area, and only flows along the third inductance pattern when passing through the crossover overlapping area for the second time. 1 3. A method for manufacturing an inductive element, which is structured on a substrate, and at least a first dielectric layer is formed on the substrate. The method includes: simultaneously forming a first patterned layer in the first dielectric layer. A metal layer and a first inductance pattern; 11487TWF.PTD Page 29 200527650 Second gold 6. Application for a patent Forming the first dielectric layer to cover the first metal layer, the first second dielectric layer has a plurality of first ones The opening is to expose the first exposed first inductance pattern; to form a metal layer on the second dielectric layer, and to simultaneously form a second inductance pattern on the second dielectric, wherein the first connection and the first Two inductor patterns are connected. 14. The first method of the scope of patent application, wherein the first metal layer includes a topmost metal layer of the structure. 1 5. As in the first method of applying for a patent, wherein the second metal layer includes 16; as in the first method of applying for a patent, wherein the second metal layer and the 1 7. As in the first method of applying for a patent, wherein the The inductance element includes a concentric circular spiral inductance element. 18. As in the first method of applying for a patent, wherein the first inductor pattern and the inductor structure are 'and the three-dimensional inductor junction is in the crossover overlapping area, the first patterned one of the second dielectric layer is covered with the inductive pattern and The first dielectric layer, the opening and the plurality of second openings, one of which is a metal layer, and the second openings and the two metal layers which fill the second layers and form the two metal layers which fill the second openings The first metal layer is electrically connected to the first inductor pattern. The manufacturer of the inductor element according to item 3 is a multilayer metal interconnect on the substrate. The manufacturer of the inductor element according to item 3 is a metal plug. With metal pads. Manufacture of the inductive element according to item 5, the material of the second inductive pattern includes aluminum. The manufacturing method of the inductive element described in item 3 is called a circular spiral type inductive element or the same as the manufacturing method of the inductive element described in item 3. The second inductance pattern constitutes a three-dimensional structure with a crossover overlapping area, and the inductance The pattern is not the same as the second inductance pattern 11487TWF.PTD Page 30 200527650 11487TWF.PTD Page 31