TW200518875A - Method of reducing pattern effect in CMP process, method of eliminating dishing phenomena after CMP process, and method of CMP rework - Google Patents
Method of reducing pattern effect in CMP process, method of eliminating dishing phenomena after CMP process, and method of CMP reworkInfo
- Publication number
- TW200518875A TW200518875A TW093121274A TW93121274A TW200518875A TW 200518875 A TW200518875 A TW 200518875A TW 093121274 A TW093121274 A TW 093121274A TW 93121274 A TW93121274 A TW 93121274A TW 200518875 A TW200518875 A TW 200518875A
- Authority
- TW
- Taiwan
- Prior art keywords
- cmp process
- cmp
- layer
- rework
- pattern effect
- Prior art date
Links
- 238000000034 method Methods 0.000 title abstract 13
- 230000000694 effects Effects 0.000 title abstract 2
- 230000004888 barrier function Effects 0.000 abstract 3
- 238000000151 deposition Methods 0.000 abstract 1
- 239000000463 material Substances 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/724,201 US7183199B2 (en) | 2003-12-01 | 2003-12-01 | Method of reducing the pattern effect in the CMP process |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW200518875A true TW200518875A (en) | 2005-06-16 |
| TWI274629B TWI274629B (en) | 2007-03-01 |
Family
ID=34620038
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW093121274A TWI274629B (en) | 2003-12-01 | 2004-07-16 | Method of reducing pattern effect in CMP process, method of eliminating dishing phenomena after CMP process, and method of CMP rework |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US7183199B2 (zh) |
| TW (1) | TWI274629B (zh) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7446033B2 (en) * | 2005-01-25 | 2008-11-04 | Samung Electronics Co., Ltd. | Method of forming a metal interconnection of a semiconductor device, and metal interconnection formed by such method |
| US7955964B2 (en) | 2008-05-14 | 2011-06-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dishing-free gap-filling with multiple CMPs |
| US8048752B2 (en) * | 2008-07-24 | 2011-11-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Spacer shape engineering for void-free gap-filling process |
| CN103972048A (zh) * | 2014-04-22 | 2014-08-06 | 上海华力微电子有限公司 | 改善层间介质层研磨返工工艺的方法 |
| KR102292209B1 (ko) * | 2014-07-28 | 2021-08-25 | 삼성전자주식회사 | 반도체 계측 시스템 및 이를 이용한 반도체 소자의 계측 방법 |
| US10177006B2 (en) | 2016-11-30 | 2019-01-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Process for making multi-gate transistors and resulting structures |
| CN109713006B (zh) * | 2017-10-25 | 2023-03-24 | 上海磁宇信息科技有限公司 | 一种制作磁性随机存储器单元阵列及其周围电路的方法 |
| CN107919296A (zh) * | 2017-11-16 | 2018-04-17 | 德淮半导体有限公司 | 半导体结构的形成方法及其加工装置 |
| CN112133820A (zh) * | 2019-06-25 | 2020-12-25 | 中电海康集团有限公司 | Mram底电极的制备方法 |
| CN112133822A (zh) * | 2019-06-25 | 2020-12-25 | 中电海康集团有限公司 | 自对准的mram底电极制备方法 |
| CN112133819A (zh) * | 2019-06-25 | 2020-12-25 | 中电海康集团有限公司 | Mram底电极的制备方法 |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6251786B1 (en) | 1999-09-07 | 2001-06-26 | Chartered Semiconductor Manufacturing Ltd. | Method to create a copper dual damascene structure with less dishing and erosion |
| US6461225B1 (en) | 2000-04-11 | 2002-10-08 | Agere Systems Guardian Corp. | Local area alloying for preventing dishing of copper during chemical-mechanical polishing (CMP) |
| US6929531B2 (en) * | 2002-09-19 | 2005-08-16 | Lam Research Corporation | System and method for metal residue detection and mapping within a multi-step sequence |
| US20040067640A1 (en) * | 2002-10-08 | 2004-04-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Multiple layer copper deposition to improve CMP performance |
-
2003
- 2003-12-01 US US10/724,201 patent/US7183199B2/en not_active Expired - Fee Related
-
2004
- 2004-07-16 TW TW093121274A patent/TWI274629B/zh not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| US7183199B2 (en) | 2007-02-27 |
| TWI274629B (en) | 2007-03-01 |
| US20050118808A1 (en) | 2005-06-02 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | Annulment or lapse of patent due to non-payment of fees |