TW200511023A - Method to provide atomic update primitives in an asymmetric heterogeneous multiprocessor environment - Google Patents
Method to provide atomic update primitives in an asymmetric heterogeneous multiprocessor environmentInfo
- Publication number
- TW200511023A TW200511023A TW093112936A TW93112936A TW200511023A TW 200511023 A TW200511023 A TW 200511023A TW 093112936 A TW093112936 A TW 093112936A TW 93112936 A TW93112936 A TW 93112936A TW 200511023 A TW200511023 A TW 200511023A
- Authority
- TW
- Taiwan
- Prior art keywords
- atomic update
- command
- heterogeneous multiprocessor
- lock line
- multiprocessor environment
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
-
- A—HUMAN NECESSITIES
- A47—FURNITURE; DOMESTIC ARTICLES OR APPLIANCES; COFFEE MILLS; SPICE MILLS; SUCTION CLEANERS IN GENERAL
- A47G—HOUSEHOLD OR TABLE EQUIPMENT
- A47G19/00—Table service
- A47G19/22—Drinking vessels or saucers used for table service
- A47G19/2205—Drinking glasses or vessels
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B65—CONVEYING; PACKING; STORING; HANDLING THIN OR FILAMENTARY MATERIAL
- B65D—CONTAINERS FOR STORAGE OR TRANSPORT OF ARTICLES OR MATERIALS, e.g. BAGS, BARRELS, BOTTLES, BOXES, CANS, CARTONS, CRATES, DRUMS, JARS, TANKS, HOPPERS, FORWARDING CONTAINERS; ACCESSORIES, CLOSURES, OR FITTINGS THEREFOR; PACKAGING ELEMENTS; PACKAGES
- B65D85/00—Containers, packaging elements or packages, specially adapted for particular articles or materials
- B65D85/70—Containers, packaging elements or packages, specially adapted for particular articles or materials for materials not otherwise provided for
- B65D85/804—Disposable containers or packages with contents which are mixed, infused or dissolved in situ, i.e. without having been previously removed from the package
- B65D85/808—Disposable containers or packages with contents which are mixed, infused or dissolved in situ, i.e. without having been previously removed from the package for immersion in the liquid to release part or all of their contents, e.g. tea bags
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
- G06F9/30087—Synchronisation or serialisation instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0038—System on Chip
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Mechanical Engineering (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Multi Processors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/443,727 US7114042B2 (en) | 2003-05-22 | 2003-05-22 | Method to provide atomic update primitives in an asymmetric heterogeneous multiprocessor environment |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200511023A true TW200511023A (en) | 2005-03-16 |
TWI269180B TWI269180B (en) | 2006-12-21 |
Family
ID=33450499
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW093112936A TWI269180B (en) | 2003-05-22 | 2004-05-07 | Asymmetric single-chip heterogeneous multiprocessor computer system and method of providing atomic update primitives for use therein |
Country Status (6)
Country | Link |
---|---|
US (2) | US7114042B2 (zh) |
JP (2) | JP3974597B2 (zh) |
KR (1) | KR100641988B1 (zh) |
CN (1) | CN1273899C (zh) |
HK (1) | HK1070719A1 (zh) |
TW (1) | TWI269180B (zh) |
Cited By (7)
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---|---|---|---|---|
US9274859B2 (en) | 2006-05-25 | 2016-03-01 | Nvidia Corporation | Multi processor and multi thread safe message queue with hardware assistance |
US9928121B2 (en) | 2012-06-15 | 2018-03-27 | Intel Corporation | Method and system for implementing recovery from speculative forwarding miss-predictions/errors resulting from load store reordering and optimization |
US9965277B2 (en) | 2012-06-15 | 2018-05-08 | Intel Corporation | Virtual load store queue having a dynamic dispatch window with a unified structure |
US9990198B2 (en) | 2012-06-15 | 2018-06-05 | Intel Corporation | Instruction definition to implement load store reordering and optimization |
US10019263B2 (en) | 2012-06-15 | 2018-07-10 | Intel Corporation | Reordered speculative instruction sequences with a disambiguation-free out of order load store queue |
US10048964B2 (en) | 2012-06-15 | 2018-08-14 | Intel Corporation | Disambiguation-free out of order load store queue |
TWI637318B (zh) * | 2012-06-15 | 2018-10-01 | 英特爾股份有限公司 | 用於在使用共享記憶體資源的記憶體一致性模型內失序載入之鎖定式與同步式方法 |
Families Citing this family (41)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7233998B2 (en) * | 2001-03-22 | 2007-06-19 | Sony Computer Entertainment Inc. | Computer architecture and software cells for broadband networks |
US7389508B2 (en) | 2003-09-25 | 2008-06-17 | International Business Machines Corporation | System and method for grouping processors and assigning shared memory space to a group in heterogeneous computer environment |
US7549145B2 (en) | 2003-09-25 | 2009-06-16 | International Business Machines Corporation | Processor dedicated code handling in a multi-processor environment |
US7478390B2 (en) * | 2003-09-25 | 2009-01-13 | International Business Machines Corporation | Task queue management of virtual devices using a plurality of processors |
US7523157B2 (en) * | 2003-09-25 | 2009-04-21 | International Business Machines Corporation | Managing a plurality of processors as devices |
US7415703B2 (en) | 2003-09-25 | 2008-08-19 | International Business Machines Corporation | Loading software on a plurality of processors |
US7444632B2 (en) | 2003-09-25 | 2008-10-28 | International Business Machines Corporation | Balancing computational load across a plurality of processors |
US7516456B2 (en) * | 2003-09-25 | 2009-04-07 | International Business Machines Corporation | Asymmetric heterogeneous multi-threaded operating system |
US20050071828A1 (en) * | 2003-09-25 | 2005-03-31 | International Business Machines Corporation | System and method for compiling source code for multi-processor environments |
US7496917B2 (en) * | 2003-09-25 | 2009-02-24 | International Business Machines Corporation | Virtual devices using a pluarlity of processors |
US7657667B2 (en) * | 2004-03-25 | 2010-02-02 | International Business Machines Corporation | Method to provide cache management commands for a DMA controller |
US7774750B2 (en) * | 2005-07-19 | 2010-08-10 | Microsoft Corporation | Common concurrency runtime |
US7509463B2 (en) * | 2005-12-01 | 2009-03-24 | Sony Computer Entertainment, Inc. | Cell processor atomic compare and swap using dedicated synergistic processor element |
US7624237B2 (en) * | 2006-05-03 | 2009-11-24 | International Business Machines Corporation | Compare, swap and store facility with no external serialization |
US7606961B2 (en) * | 2006-06-28 | 2009-10-20 | Kabushiki Kaisha Toshiba | Computer system and data pre-fetching method |
GB2443277B (en) * | 2006-10-24 | 2011-05-18 | Advanced Risc Mach Ltd | Performing diagnostics operations upon an asymmetric multiprocessor apparatus |
US8024521B2 (en) * | 2007-03-13 | 2011-09-20 | Sony Computer Entertainment Inc. | Atomic operation on non-standard sized data using external cache |
US8266391B2 (en) * | 2007-06-19 | 2012-09-11 | SanDisk Technologies, Inc. | Method for writing data of an atomic transaction to a memory device |
US20090077322A1 (en) * | 2007-09-19 | 2009-03-19 | Charles Ray Johns | System and Method for Getllar Hit Cache Line Data Forward Via Data-Only Transfer Protocol Through BEB Bus |
US8015380B2 (en) * | 2008-02-01 | 2011-09-06 | International Business Machines Corporation | Launching multiple concurrent memory moves via a fully asynchronoous memory mover |
US8245004B2 (en) * | 2008-02-01 | 2012-08-14 | International Business Machines Corporation | Mechanisms for communicating with an asynchronous memory mover to perform AMM operations |
US8327101B2 (en) * | 2008-02-01 | 2012-12-04 | International Business Machines Corporation | Cache management during asynchronous memory move operations |
US7941627B2 (en) * | 2008-02-01 | 2011-05-10 | International Business Machines Corporation | Specialized memory move barrier operations |
US8356151B2 (en) * | 2008-02-01 | 2013-01-15 | International Business Machines Corporation | Reporting of partially performed memory move |
US8095758B2 (en) * | 2008-02-01 | 2012-01-10 | International Business Machines Corporation | Fully asynchronous memory mover |
US8275963B2 (en) * | 2008-02-01 | 2012-09-25 | International Business Machines Corporation | Asynchronous memory move across physical nodes with dual-sided communication |
JP5151559B2 (ja) * | 2008-02-29 | 2013-02-27 | 富士通株式会社 | プログラム実行システム |
US20090248919A1 (en) * | 2008-03-25 | 2009-10-01 | Jerzy Szwagrzyk | Method for external fifo acceleration |
US20090254712A1 (en) * | 2008-04-02 | 2009-10-08 | Naveen Cherukuri | Adaptive cache organization for chip multiprocessors |
US8412862B2 (en) | 2008-12-18 | 2013-04-02 | International Business Machines Corporation | Direct memory access transfer efficiency |
CN101950282B (zh) | 2010-08-30 | 2012-05-23 | 中国科学院计算技术研究所 | 一种多处理器系统及其同步引擎 |
US8341316B2 (en) * | 2010-11-17 | 2012-12-25 | Advanced Micro Devices, Inc. | Method and apparatus for controlling a translation lookaside buffer |
US9280348B2 (en) | 2012-03-28 | 2016-03-08 | International Business Machines Corporation | Decode time instruction optimization for load reserve and store conditional sequences |
US10320861B2 (en) | 2015-09-30 | 2019-06-11 | Google Llc | System and method for automatic meeting note creation and sharing using a user's context and physical proximity |
KR102407917B1 (ko) | 2015-11-12 | 2022-06-10 | 삼성전자주식회사 | 멀티 프로세서에 의해 공유되는 메모리를 포함하는 멀티 프로세서 시스템 및 상기 시스템의 동작 방법 |
CN105354153B (zh) * | 2015-11-23 | 2018-04-06 | 浙江大学城市学院 | 一种紧耦合异构多处理器数据交换缓存的实现方法 |
US9652385B1 (en) * | 2015-11-27 | 2017-05-16 | Arm Limited | Apparatus and method for handling atomic update operations |
CN109324838B (zh) * | 2018-08-31 | 2022-05-10 | 深圳市元征科技股份有限公司 | 单片机程序的执行方法、执行装置及终端 |
US11119781B2 (en) | 2018-12-11 | 2021-09-14 | International Business Machines Corporation | Synchronized access to data in shared memory by protecting the load target address of a fronting load |
WO2021198784A1 (en) * | 2020-04-03 | 2021-10-07 | Mobileye Vision Technologies Ltd. | A multi-part compare and exchange operation |
US11106608B1 (en) * | 2020-06-22 | 2021-08-31 | International Business Machines Corporation | Synchronizing access to shared memory by extending protection for a target address of a store-conditional request |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CA2045789A1 (en) | 1990-06-29 | 1991-12-30 | Richard Lee Sites | Granularity hint for translation buffer in high performance processor |
KR0135927B1 (ko) | 1994-11-21 | 1998-06-15 | 양승택 | 다중 프로세서 시스템에서 아토믹 명령어 수행시 데이타 버퍼를 사용한 메인 메모리 액세스 장치 |
JPH08287022A (ja) | 1995-03-31 | 1996-11-01 | Internatl Business Mach Corp <Ibm> | マルチプロセッサ・システム及びその排他的制御方法 |
US5727172A (en) * | 1995-05-01 | 1998-03-10 | Motorola, Inc. | Method and apparatus for performing atomic accesses in a data processing system |
US5822588A (en) * | 1995-06-09 | 1998-10-13 | Sun Microsystem, Inc. | System and method for checking the use of synchronization locks in a multi-threaded target program |
US5794068A (en) * | 1996-03-18 | 1998-08-11 | Advanced Micro Devices, Inc. | CPU with DSP having function preprocessor that converts instruction sequences intended to perform DSP function into DSP function identifier |
US5887134A (en) * | 1997-06-30 | 1999-03-23 | Sun Microsystems | System and method for preserving message order while employing both programmed I/O and DMA operations |
US6098156A (en) * | 1997-07-22 | 2000-08-01 | International Business Machines Corporation | Method and system for rapid line ownership transfer for multiprocessor updates |
US6092156A (en) | 1997-11-05 | 2000-07-18 | Unisys Corporation | System and method for avoiding deadlocks utilizing split lock operations to provide exclusive access to memory during non-atomic operations |
US6148300A (en) | 1998-06-19 | 2000-11-14 | Sun Microsystems, Inc. | Hybrid queue and backoff computer resource lock featuring different spin speeds corresponding to multiple-states |
US6728839B1 (en) * | 1998-10-28 | 2004-04-27 | Cisco Technology, Inc. | Attribute based memory pre-fetching technique |
US6347347B1 (en) * | 1999-07-15 | 2002-02-12 | 3Com Corporation | Multicast direct memory access storing selected ones of data segments into a first-in-first-out buffer and a memory simultaneously when enabled by a processor |
JP3853114B2 (ja) * | 1999-07-30 | 2006-12-06 | 松下電器産業株式会社 | インターフェースの設計方法 |
US6493741B1 (en) * | 1999-10-01 | 2002-12-10 | Compaq Information Technologies Group, L.P. | Method and apparatus to quiesce a portion of a simultaneous multithreaded central processing unit |
US6496905B1 (en) | 1999-10-01 | 2002-12-17 | Hitachi, Ltd. | Write buffer with burst capability |
US6691178B1 (en) * | 2000-02-22 | 2004-02-10 | Stmicroelectronics, Inc. | Fencepost descriptor caching mechanism and method therefor |
JP2002163239A (ja) | 2000-11-22 | 2002-06-07 | Toshiba Corp | マルチプロセッサシステムおよびその制御方法 |
US20030196076A1 (en) * | 2001-07-02 | 2003-10-16 | Globespan Virata Incorporated | Communications system using rings architecture |
US7266587B2 (en) * | 2002-05-15 | 2007-09-04 | Broadcom Corporation | System having interfaces, switch, and memory bridge for CC-NUMA operation |
US7185150B1 (en) * | 2002-09-20 | 2007-02-27 | University Of Notre Dame Du Lac | Architectures for self-contained, mobile, memory programming |
-
2003
- 2003-05-22 US US10/443,727 patent/US7114042B2/en not_active Expired - Fee Related
-
2004
- 2004-04-21 KR KR1020040027540A patent/KR100641988B1/ko not_active IP Right Cessation
- 2004-05-07 TW TW093112936A patent/TWI269180B/zh not_active IP Right Cessation
- 2004-05-18 CN CNB2004100447825A patent/CN1273899C/zh not_active Expired - Fee Related
- 2004-05-18 JP JP2004148226A patent/JP3974597B2/ja not_active Expired - Fee Related
-
2005
- 2005-05-11 HK HK05103951A patent/HK1070719A1/xx not_active IP Right Cessation
-
2006
- 2006-08-30 US US11/468,317 patent/US7814281B2/en not_active Expired - Fee Related
- 2006-12-12 JP JP2006334314A patent/JP4730742B2/ja not_active Expired - Fee Related
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9274859B2 (en) | 2006-05-25 | 2016-03-01 | Nvidia Corporation | Multi processor and multi thread safe message queue with hardware assistance |
US9928121B2 (en) | 2012-06-15 | 2018-03-27 | Intel Corporation | Method and system for implementing recovery from speculative forwarding miss-predictions/errors resulting from load store reordering and optimization |
US9965277B2 (en) | 2012-06-15 | 2018-05-08 | Intel Corporation | Virtual load store queue having a dynamic dispatch window with a unified structure |
US9990198B2 (en) | 2012-06-15 | 2018-06-05 | Intel Corporation | Instruction definition to implement load store reordering and optimization |
US10019263B2 (en) | 2012-06-15 | 2018-07-10 | Intel Corporation | Reordered speculative instruction sequences with a disambiguation-free out of order load store queue |
US10048964B2 (en) | 2012-06-15 | 2018-08-14 | Intel Corporation | Disambiguation-free out of order load store queue |
TWI637318B (zh) * | 2012-06-15 | 2018-10-01 | 英特爾股份有限公司 | 用於在使用共享記憶體資源的記憶體一致性模型內失序載入之鎖定式與同步式方法 |
US10592300B2 (en) | 2012-06-15 | 2020-03-17 | Intel Corporation | Method and system for implementing recovery from speculative forwarding miss-predictions/errors resulting from load store reordering and optimization |
Also Published As
Publication number | Publication date |
---|---|
HK1070719A1 (en) | 2005-06-24 |
JP2007122741A (ja) | 2007-05-17 |
CN1273899C (zh) | 2006-09-06 |
CN1573715A (zh) | 2005-02-02 |
JP3974597B2 (ja) | 2007-09-12 |
KR20040100884A (ko) | 2004-12-02 |
TWI269180B (en) | 2006-12-21 |
JP2004348734A (ja) | 2004-12-09 |
US20070016733A1 (en) | 2007-01-18 |
US7114042B2 (en) | 2006-09-26 |
KR100641988B1 (ko) | 2006-11-06 |
US20040236914A1 (en) | 2004-11-25 |
US7814281B2 (en) | 2010-10-12 |
JP4730742B2 (ja) | 2011-07-20 |
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Legal Events
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MM4A | Annulment or lapse of patent due to non-payment of fees |