TW200504957A - Semiconductor chip package and method of manufacturing lead frame therefor - Google Patents

Semiconductor chip package and method of manufacturing lead frame therefor

Info

Publication number
TW200504957A
TW200504957A TW092119599A TW92119599A TW200504957A TW 200504957 A TW200504957 A TW 200504957A TW 092119599 A TW092119599 A TW 092119599A TW 92119599 A TW92119599 A TW 92119599A TW 200504957 A TW200504957 A TW 200504957A
Authority
TW
Taiwan
Prior art keywords
lead frame
semiconductor chip
groove
chip package
die pad
Prior art date
Application number
TW092119599A
Other languages
Chinese (zh)
Other versions
TWI224839B (en
Inventor
Kang-Wei Ma
Shu-Chen Yang
Shu-Hsia Lin
Ying-Chen Sun
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW92119599A priority Critical patent/TWI224839B/en
Application granted granted Critical
Publication of TWI224839B publication Critical patent/TWI224839B/en
Publication of TW200504957A publication Critical patent/TW200504957A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

A semiconductor chip package includes a lead frame, a semiconductor chip disposed on the lead frame, a plurality of bonding wires for electrically interconnecting the semiconductor die and the lead frame, and a plastic package body encapsulating the lead frame, the semiconductor chip and the bonding wires. The lead frame has a plurality of leads and a die pad. One surface of the die pad has a chip mounting region, a first groove surrounding the chip mounting region, a second groove surrounding the first groove, and a peripheral region surrounding the second groove. The present invention is characterized in that at least one noble metal is plated on the surface of the die pad with the chip mounting region and the peripheral region kept un-plated to form a noble metal pattern between the first groove and the second groove. The present invention further provides a method of manufacturing the lead frame for the semiconductor chip package.
TW92119599A 2003-07-17 2003-07-17 Semiconductor chip package and method of manufacturing lead frame therefor TWI224839B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW92119599A TWI224839B (en) 2003-07-17 2003-07-17 Semiconductor chip package and method of manufacturing lead frame therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW92119599A TWI224839B (en) 2003-07-17 2003-07-17 Semiconductor chip package and method of manufacturing lead frame therefor

Publications (2)

Publication Number Publication Date
TWI224839B TWI224839B (en) 2004-12-01
TW200504957A true TW200504957A (en) 2005-02-01

Family

ID=34568433

Family Applications (1)

Application Number Title Priority Date Filing Date
TW92119599A TWI224839B (en) 2003-07-17 2003-07-17 Semiconductor chip package and method of manufacturing lead frame therefor

Country Status (1)

Country Link
TW (1) TWI224839B (en)

Also Published As

Publication number Publication date
TWI224839B (en) 2004-12-01

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Legal Events

Date Code Title Description
MK4A Expiration of patent term of an invention patent