TW200428665A - Method of fabricating low temperature polysilicon thin film transistor - Google Patents

Abstract

A method of fabricating an interlayer dielectric layer of a low temperature polysilicon thin film transistor is disclosed. First, a substrate with a polysilicon film is provided. Then, a gate insulating layer and a gate are formed on the polysilicon film in sequence. An ion implantation process is performed to form a source and a drain surrounded the gate. After that, a first plasma enhanced chemical vapor deposition (PECVD) process is performed to form a silicon nitride layer covered on the substrate and the gate. A second plasma enhanced chemical vapor deposition process is then performed to form a TEOS based silicon oxide layer on the silicon nitride layer. A photo-etching process is followed to form a contact hole extending through to the source and drain respectively. Then, a conductive layer is filled into the contact holes and electrically connected to the source and drain.

Description

200428665 V. Description of the invention (1) Technical field of the invention The present invention provides a method for manufacturing an interlayer dielectric layer of a low temperature polysilicon thin film transistor (LTP TFT), especially a method for manufacturing the interlayer dielectric layer. A method for manufacturing a low-temperature polycrystalline silicon thin film transistor including a composite interlayer dielectric layer (ILD layer). Previous technology In today's flat-panel display technology, liquid crystal display (LCD) is one of the most mature technologies, such as mobile phones, digital cameras, video cameras, notebook computers and even monitors that are common in daily life. It is a product manufactured using this technology. However, with the increase of people's requirements for the visual perception of displays and the continuous expansion of new technology applications, flat screen displays with higher picture quality, high resolution, high brightness, and low price have become the development of future display technologies. The trend has also created the driving force behind the development of new display technologies. In various types of liquid crystal displays, a low-temperature polysilicon thin film transistor (| LTPS TFT) type liquid crystal display can not only actively drive each pixel electrode on the liquid crystal display panel in an array mode, but also With its high carrier mobility, it meets the requirements of thinness, power saving, and high quality.

Page 6 200428665 V. Description of the invention (2) In the process of low-temperature polycrystalline silicon thin film transistors, an inter layer dielectric (ILD) layer is provided between each transistor and the metal wire layer above it to isolate it. And protect the circuit elements on the display panel, and a plurality of contact holes are provided in the interlayer insulation layer, so that the metal wire layer can fill each of the contact holes and be electrically connected to the corresponding transistor below . Therefore, the data signal can be transmitted to the source / drain of the transistor through the metal wire layer through the metal wire layer in the contact hole to further control the operation of each pixel electrode in the display panel. Please refer to FIGS. 1 to 4. FIGS. 1 to 4 are schematic diagrams of a method for fabricating an interlayer insulating layer of a low-temperature polycrystalline silicon thin film transistor on a display panel in the conventional technology. Generally speaking, a display panel usually includes a plurality of low-temperature polycrystalline silicon thin-film transistors to drive each pixel electrode on the display panel. For convenience, only one low-temperature polycrystalline silicon thin-film transistor is used in the following illustration. . As shown in FIG. 1, a display panel 10 includes a substrate 12. The substrate 12 may be a glass substrate or a silicon substrate. First, a chemical vapor deposition process or a sputtering process is performed to form an amorphous silicon film (not shown) with a thickness of about 50 angstroms over the substrate 12 and an excimer laser annealing process is used. anneal ing process) to recrystallize the amorphous silicon thin film into a polycrystalline silicon thin film 14. Subsequently, a first yellow light and etching process is performed to pattern the polycrystalline silicon thin film 14, and only the low-temperature polycrystalline silicon thin films are left to be formed.

200428665 V. Description of the invention (3) Part of the transistor 'wherein the polycrystalline silicon film 14 has a source region 18, a drain region 20, and a channel region defined therein. regiocu. As shown in FIG. 2 ', a chemical vapor deposition (CVD) process is then performed to form a gate insulating layer 24 on the surface of the polycrystalline silicon thin film 14. A sputtering process is then performed. A metal layer is formed on the surface of the gate insulating layer 24, and the metal layer is patterned by a second yellow light and etching process to form a gate 26 over the channel region 22. Then, as shown in FIG. As shown in FIG. 3, an ion implantation (i 011 imp lan tat ion) process is performed, and the gate electrode 26 is used as a mask to form a source in the source region 18 and the drain region 20 in the polycrystalline silicon thin film 14 respectively. Source 28 and a drain 30, and together with the gate 26 form a low temperature polycrystalline thin film transistor structure 3 2. In the application of the thin film transistor (TFT), the source / drain Series resistance istance) must be very low, so an act i vat i on process will be performed after the ion implantation process, so that the dopants in the source 28 and the drain 30 are highly activated. Moving the ions outside the correct lattice position also has the effect of repairing lattice defects caused by the ion implantation to complete the production of low temperature polycrystalline silicon thin film transistors. ^

200428665 V. Description of the invention (4) After the production of the low-temperature polycrystalline stone and the gate electrode 26, the source electrode 28 of the special transistor 26, and the layer 34 of the electrode 30 are covered. As shown in J and ^, a dielectric yellow light cum # is then deposited on the source core: 1-pole insulating layer 24, and a third pattern is used to form the source 28 to: the domain 8 and the drain Above the area 20 points ho le) 36. Finally, fill in the contact hole of _, drain electrode 30 (contact work. ~ Conductive layer 3 8 to complete the subsequent electrical connection to protect the important process when the full normal protective energy is often unsuitable, nitrogen power 0 which function 〇 However, the force used on the foot, but the cooperation will not be formed by the silicon layer. The circuit elements are formed as a layer. According to the description, the oxygen layer can be easily formed as a layer, which is commonly used before the signal is significant. Take the difference between the insulation layer retardation and the resistance to the parasitic interstitial insulation of the nitrogen stone, except that the electrical layer 3 4 can be used as an insulating layer that will be subjected to subsequent processes. Taking the dielectric layer material and the general semiconductor process layer as an example, nitrogen The silicon layer and metal ions pass through the capacitor to generate a signal layer. Although the phenomenon of the Shi Xi oxygen layer, it can not provide a shadow of the follow-up or obvious though the delay is well protected. The multi-layer often does not show that the panel is good, but its phenomenon has a low dielectric strength but protection to ensure that the other connection can be the same process with high dielectric resistance. lane ❿ In addition, in the production, or ethoxylate, the TEOS can be used as silicon, and the shoulder ① (tet, r ^ ethyl—ortho — silicate) is miscellaneous, forming two different properties. Shi Xi oxygen layer, that is,

200428665 V. Description of the invention (5) The so-called silicon oxide (mainly silicon oxide) or TEOS (silicon oxide), in which the former can be used as a hydrogen atom for hydrogenation of the element to defect, but because of its step covering the hole The latter, although performing deposition, does not provide another hydrogenation process for hydrogenation, which will greatly increase production time. Oxygen layer (Si lane-based, the main stone Xi oxygen layer (TEOS-based because it will contain significant hydrogen atoms, the source's ability to repair in polycrystalline silicon thin film is not good, and easy to generate holes with better step coverage, atomic source That is, it is necessary to additionally provide equipment costs for increasing the hydrogenation process. As mentioned above, in various conventional technologies, there is no one method that can produce both good interface characteristics and high initial voltage stability, as well as water vapor and metals. Ions have better anti-seeding and anti-blocking capabilities, and at the same time have an interlayer insulation layer with high breakdown voltage. Therefore, how to develop a method for manufacturing a low-temperature polycrystalline silicon thin film transistor that has the above advantages, It has become an important subject at present. SUMMARY OF THE INVENTION The main object of the present invention is to provide a method for manufacturing a low-temperature polycrystalline chip thin film transistor with a composite interlayer insulating layer (ILD layer) to solve the above problems. In the embodiment, a substrate is provided first, and the substrate is provided on the substrate.

Page 10 200428665 V. Description of the invention (6) A polycrystalline silicon film is formed on the surface, and then a gate insulating layer and a gate are sequentially formed on the surface of the polycrystalline silicon film, and then an ion implantation process is performed on the gate. A source electrode and a drain electrode are respectively formed around the substrate, and then a first plasma is used to enhance the chemical vapor deposition process to form a silicon nitride layer to cover the gate and the surface of the polycrystalline silicon film, and then a second plasma is performed. The chemical vapor deposition process is enhanced to form a silicon oxide layer mainly composed of tetraethoxysilane on the surface of the nitrogen silicon layer, and finally a yellow light and etching process is performed for the source and sink of the thin film transistor. A contact hole is formed above the electrode to reach the source and the drain of the low-temperature polycrystalline silicon thin film transistor, and a conductive layer is filled in each of the contact holes to be electrically connected to the source and the drain, respectively. Because the low-temperature polycrystalline silicon thin film transistor of the present invention uses a first plasma enhanced chemical vapor deposition process to form a silicon silicon layer mainly composed of silane, in order to increase protection against moisture and provide a subsequent hydrogenation process Source of hydrogen ions, and then a second plasma enhanced chemical vapor deposition process to form a silicon oxide layer mainly composed of tetraethoxysilane to provide a better step coverage and reduce the dielectric constant Therefore, the generation of parasitic capacitance can be avoided, so the purpose of effectively improving the electrical performance and reliability of the low-temperature polycrystalline broken film transistor can be achieved. Embodiment Please refer to FIG. 5 to FIG. 8, which are made according to the present invention

Page 11 200428665 V. Description of the invention (7) A schematic diagram of a low-temperature polycrystalline silicon thin film transistor method. As mentioned above, a display panel usually includes a plurality of low-temperature polycrystalline silicon thin-film transistors to drive each pixel electrode on the display panel. For convenience, only one low-temperature polycrystalline silicon thin-film transistor is used in the following illustration. representative. As shown in FIG. 5, first, a chemical vapor deposition process or a sputtering process is performed to form an amorphous stone film (not shown) with a thickness of about 500 angstroms on a display panel 110, and then use a The excimer laser annealing process recrystallizes the amorphous silicon film into a polycrystalline silicon film 1 1 4 and then performs a first yellow light and etching process to pattern the polycrystalline silicon film 11 4, leaving only A portion of each of the low-temperature polycrystalline silicon thin film transistors is scheduled to be formed next. Among them, the display panel 110 is a substrate 11 2 ′ and the substrate 112 may be a glass substrate or a stone substrate, and the surface of the polycrystalline thin film 114 is defined with a source region 118, a The drain region 120 and the channel 1 region (channe 1 region) 122. Due to the quality of the amorphous silicon thin film (not shown), the characteristics of the polycrystalline silicon thin film 11 subsequently formed are greatly affected. Various parameters in the amorphous stone film deposition process need to be strictly controlled in order to form low hydrogen content, high thickness un if or mity, and low surface roughness ) Of amorphous silicon film. In addition, during the excimer laser annealing process, the amorphous silicon thin film achieves rapid melting and recrystallization through the absorption of laser deep ultraviolet light to form a polycrystalline silicon thin film.

Page 12 200428665

The fast absorption caused by the short-time pulsed laser is only used for ==, so the substrate 112 can be kept at a low temperature and the state%. As shown in Fig. 6, a chemical vapor deposition (CVD) process is performed to form a gate insulating layer 124 on the surface of the polycrystalline silicon thin film n4. Subsequently, a sputtering process is performed to form a metal layer on the surface of the gate insulating layer 丨 24, and the metal layer is patterned by a second yellow light and etching process to form a gate over the channel region 122. Extremely ι26. In a preferred embodiment of the present invention, the gate insulating layer 1 24 is a silicon nitride layer, a silicon oxide layer, or a composite structure containing a silicon nitride layer or a silicon oxide layer at the same time to form the gold S metal layer. The materials include tungsten, aluminum, chromium, or alloys thereof. As shown in FIG. 7, an ion implantation process is then performed, and the gate electrode 126 is used as a mask for the source region 118 and the non-electrode region in the polycrystalline silicon film 1 14. A source 128 and a drain! 30 are respectively formed in 120, and a low-temperature polycrystalline silicon thin film transistor structure 1 3 丨 is formed together with the gate electrode 1 2 6. Then, an activation process is performed, so that the dopants in the source 128 and the drain 130 are highly activated, and the ions are moved to the correct lattice position, and the ions are implanted at the same time. The effect of repairing the lattice defects caused.

Page 13 200428665 V. Description of the invention (9) As shown in Fig. 8, a first plasma enhanced chemical vapor deposition (PEC VD) process is then performed. (Nh 3) and nitrogen (N2) to form a silicon silicon layer 132 (si 1 icon nitride layer, SiNx layer, 0 · 8 < χ < 1 · 6), which is dominated by silicon methane, covering gate 126 and gate A TEOS based silicon oxide layer is formed on the silicon-silicon layer 1 3 2 by injecting tetraethoxysilane and oxygen on the insulating layer 1 2 4. At 134 °, the nitrogen-silicon layer dominated by silicon methane 1 2 3 and the silicon-oxygen layer dominated by tetraethoxy silane 1 34 together form a composite interlayer insulation layer. _ • It is worth noting that because the dielectric constant of the nitrogen silicon layer 1 3 2 is much larger than that of the silicon oxide layer 134, the method of the present invention requires the thickness of the silicon nitride layer 132 and the silicon oxide layer 134 to be the same. The optimized adjustment is to deliberately increase the thickness ratio of the silicon oxide layer 13 such as jin to effectively reduce the dielectric constant of the composite interlayer insulating layer, thereby avoiding the signal delay phenomenon due to the high dielectric constant. . In a preferred embodiment of the present invention, the thickness of the silicon nitride layer 132 is about 500 to 35,000 angstroms, and the thickness of the silicon oxide layer 134 is about 2500 to 1000 angstroms. In addition, the first plasma-enhanced chemical vapor deposition process and the second plasma-enhanced chemical vapor deposition process can be continuously deposited in the same reaction chamber or the above two plasma-enhanced chemical vapor deposition processes can be completed in different reaction chambers, respectively. Deposition process. As shown in Figure 9, a third yellow light and etching process is then performed.

Page 14 200428665 V. Description of the invention (ίο) The source region 1 1 8 and the drain region i 2 0 form a contact hole (c0ntact h〇ie) i36 which reaches the source i 28 and the electrode 13 30, respectively. Then, a conductive layer 1 3 8 is filled in the contact hole 1 3 8 and electrically connected to the source electrode 1 2 8 and the drain electrode 1 3 0 'to complete the electrical connection of the low-temperature polycrystalline silicon thin film transistor 1 3 丨. 2. As the manufacturing method of the present invention uses two plasmas to enhance the chemical vapor phase > Epilayer process', a nitrogen silicon layer mainly composed of siloxane and a tetraethoxy group are formed on a low temperature polycrystalline silicon thin film transistor, respectively. Silane-based silicon oxide layer 'so, on the one hand, it can provide a source of hydrogen ions made by subsequent hydrogenation through a silicon-silicon layer and enhance the protection against water vapor and metal ions; on the other hand, by using tetraethoxylate The silane-based silicon oxide layer is used to increase the replacement coverage ability, reduce the dielectric constant, and increase the breakdown voltage (breakd0wn vo 11age) to achieve the purpose of effectively improving the characteristics and reliability of the device (re 1i abi1i ty). The manufacturing method disclosed above is based on an example of a top gate type low temperature polycrystalline silicon thin film transistor. However, the manufacturing method of the present invention is not limited to this. It can also be thrown at a low gate type low temperature polycrystalline silicon thin film transistor. Production of crystals. Please refer to Figs. 10 to 12, which are schematic diagrams of a method for fabricating a low-temperature polycrystalline silicon thin film transistor in a second embodiment of the present invention. As shown in FIG. 10, a gate 2 1 4 is first formed on a substrate 2 1 2, and a gate insulating layer 2 1 6 and an amorphous silicon film 2 1 8 are sequentially covered on the gate 2 1 4

Page 15 200428665 V. Description of the invention (11) and the substrate 2 1 2. Next, as shown in FIG. 11, an excimer laser annealing process is performed to recrystallize the amorphous silicon film 2 1 8 into a polycrystalline silicon film 2 2 0, and then an ion distribution process is performed for the polycrystalline silicon film 2 A source electrode 2 2 2 and a drain electrode 2 2 4 are formed in 20 to form a bottom gate low temperature polycrystalline silicon thin film transistor 2 26. Finally, as shown in FIG. 12, in the same manner, a low temperature polycrystalline silicon thin film transistor 2 2 6 is sequentially formed with a silicon dioxide-based nitrogen silicon layer 22 8 and a tetraethoxysilane-based silicon oxide. Layer 2 3 0 to form a composite interlayer insulation layer 2 3 2, and then two contact holes 2 3 4 are formed in the composite interlayer insulation layer 2 3 2 to reach the source 2 2 2 and the drain 2 2 4 respectively, and A conductive layer 2 3 6 is filled in the contact hole 2 3 4 to complete the electrical connection of the low-temperature polycrystalline silicon thin film transistor 2 2 6. · Compared with the conventional method for manufacturing the interlayer insulating layer of low temperature polycrystalline silicon thin film transistors, the present invention is to form a low temperature polycrystalline silicon thin film transistor by using a plasma enhanced chemical vapor deposition process to form a tetraethoxylate. Silane-based silicon oxide layer, and then another plasma enhanced chemical vapor deposition process to form a silicon-nitrogen-based nitrogen silicon layer to form a composite interlayer insulation layer, so it can not only have a high step Covering ability, high breakdown voltage, and excellent protection of water and metal ions, can also provide a source of hydrogen atoms made by subsequent hydrogenation to effectively improve the electrical performance and reliability of low temperature polycrystalline silicon thin film transistors. m The above description is only a preferred embodiment of the present invention. Any equal changes and modifications made in accordance with the scope of the patent application of the present invention shall belong to the present invention patent.

Page 16 200428665 V. Coverage of the invention description (12).

«Circle_11 Page 17 200428665 Brief description of the diagrams Brief description of the diagrams Figures 1 to 4 are schematic diagrams of the conventional method for manufacturing the interlayer insulating layer of a low-temperature polycrystalline silicon thin film transistor. 5 to 9 are schematic diagrams of a method for fabricating an interlayer insulating layer of a low-temperature polycrystalline silicon thin film transistor in the first embodiment of the present invention. Figures 10 to 12 are not intended to illustrate the method for making an interlayer insulating layer of a low temperature multi-crystal shredded thin film transistor in a second embodiment of the present invention. Schematic symbol description

Page 18 10 Display panel 12 Substrate 14 Polycrystalline silicon film 18 Source region 20 Drain region 2 2 Channel region 24 Gate insulation layer 26 Gate 28 Source 30 Drain 32 Low temperature polycrystalline silicon thin film transistor 34 Dielectric layer 36 Contact hole 38 Conductive layer 110 Display panel 112 Substrate 1 14 Polycrystalline silicon film 118 Source region 120 Drain region 122 Channel region 124 Gate insulation layer 126 Gate 128 Source 130 Drain 131 Low temperature polycrystalline silicon thin film transistor 200428665 Schematic description 1 3 2 Nitrogen silicon layer 1 3 6 Contact hole 2 1 2 Substrate 2 1 6 Gate insulating layer 2 2 0 Polycrystalline silicon film 2 2 4 Drain 2 2 8 Nitrogen silicon layer 2 3 2 Composite interlayer insulation 2 3 4 Contact hole 1 3 4 Silicon oxide layer 138 Conductive layer 2 1 4 Gate 2 1 8 Amorphous silicon film 2 2 2 Source electrode 2 2 6 Low temperature polycrystalline film transistor 2 3 0 Silicon oxide layer 2 3 6 Conductive layer

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Claims (1)

200428665 VI. Application Patent Scope 1. A method for manufacturing a low temperature polysilicon (LTPS) thin film transistor (TFT), the method includes the following steps: providing a substrate; and a substrate A polycrystalline silicon thin film is formed on the surface, and the surface of the polycrystalline silicon thin film includes a source region, a drain region, and a channel region between the source region and the drain region. Forming a gate insulating layer over the substrate; forming a gate over the substrate; performing an ion implantation process for the source region and the drain region A source electrode and a drain electrode are respectively formed in the polycrystalline silicon thin film; a si 1 ic η nitride 1 ayer layer is formed to cover the gate and the surface of the polycrystalline silicon thin film; and the silicon nitride layer is formed A TEOS based sil icon oxide layer (TeOS based sil icon oxide layer) is formed on the surface. 0 2 The method further includes the following steps: performing a yellow light and etching process to form a contact hole above the source electrode and the drain electrode; and filling a conductive layer in each of the contact holes. Are electrically connected to the source and Page 20 200428665 6. Scope of patent application The drain. 3. The method according to item 1 of the patent application, wherein the method for forming the polycrystalline silicon thin film includes the following steps: forming an amorphous silicon thin film on the substrate; and performing an excimer laser annealing (ELA) ) Process to recrystallize the amorphous silicon film into the polycrystalline silicon film. 4. The method according to item 1 of the patent application scope, wherein the nitrogen-silicon layer is a silane-based silicon nitride layer mainly composed of stone-fired sintering. Xin 5. The method according to item 4 of the patent application, wherein the silicon silicon layer contains 20% to 40% of hydrogen atoms to provide a source of hydrogen atoms for hydrogenation of the device. 6. The method according to item 1 of the patent application, wherein the gate is a metal gate. 7. The method according to item 1 of the scope of patent application, wherein the thickness of the silicon oxide layer is 2 500 to 100 Angstroms. »8. The method according to item 1 of the patent application range, wherein the thickness of the silicon nitride layer is 50 to 3 500 Angstroms Page 21 200428665 VI. Application scope of patent 9. The method of the first scope of patent application, wherein the method uses a first plasma enhanced chemical vapor deposition (PECVD) process to make the nitrogen Shi Xi layer. ο Use the method of law to form the first layer of oxygen silicon, form the shape, and make the process. The product of the system of encirclement of the air, and the science of chemistry and chemistry, please increase your application, such as electricity 11. If the scope of patent application is No. l 〇 The method of item 1, wherein the first plasma enhanced chemical vapor deposition process and the second plasma enhanced chemical vapor deposition process are performed in the same reaction chamber. 1 2. The method according to item 10 of the application, wherein the first plasma enhanced chemical vapor deposition process and the second plasma enhanced chemical vapor deposition process are performed in different reaction chambers. 13. The method according to item 10 of the scope of patent application, wherein the low-temperature polycrystalline silicon thin-film transistor system is an upper-gate low-temperature thin-film transistor or a lower-gate low-temperature polycrystalline broken-film transistor. Page 22