TW200422817A - Power-on reset circuit with supply voltage and temperature immunity, ultra-low DC leakage current, and fast power crash reaction - Google Patents

Abstract

A power-on reset circuit includes a Schmitt trigger circuit, a voltage divider, and a compensate circuit. The Schmitt trigger circuit includes a plurality of MOS devices of a uniform threshold voltage (Vt) for determining a power reset trigger level. The voltage divider is coupled to an input of the Schmitt trigger circuit for tracking the supply signal. The compensate circuit is operative to generate a small reset pulse to compensate for temperature and the supply signal variation effect.

Description

200422817 V. Description of the invention (1) Field of the invention The present invention relates to a power supply circuit, and more particularly to a power-on reset circuit of a power supply circuit. The prior art has traditionally required an electronic device to provide a fairly stable voltage to the electronic device. In such devices, when the power is initially supplied to the electronic device, the supply signal is not immediately raised from a ground potential to A level of operation. When the supply signal exceeds a threshold value 1, a "power-on reset" signal is input to various components that obtain sufficient voltage from the supply signal, and then various components of the device may respond to the power supply. The reset signal is turned on to initialize to a preset state. In many electronic devices, each time the power-on reset signal is generated, the electronic device will enter the same preset state. Many electronic devices also have a low Low power mode, also known as s 1 eep mode or hibernation mode. When in low power mode, the supply signal is reduced to a very low level, which is sufficient to provide the operation of some devices. But it is not enough to provide other devices to operate, for example, a computer system may include a low-power memory, which can store connection information, the latest revision files and other data used to repair the computer system. When the supply signal is hibernated When returning to its operating level, the power-on reset signal is usually not desired because the power-on reset signal Recovery is set to a predetermined state instead of resuming the connection, e.g., the power-on reset signal may even erase the

Page 6 200422817 V. Description of the invention (2) Part of the memory used during the line. In order to avoid such bad results, many electronic devices are designed when the voltage of the supply signal is increased from a very low `` sleep π voltage '' to one. When the voltage is fully operated, the power-on reset signal is suppressed. Conversely, when the voltage of the supply signal is increased from the ground potential to a fully operational voltage, the power-on reset signal is provided. During the state recovery, suppressing the power-on reset signal helps prevent the memory and other power-on programs from being initialized again, so as to prevent the advantages of the hibernation state from disappearing. Many techniques have been used to suppress the power-on reset signal during recovery from the hibernation state. US Patent No. 6, 0 84, 44 6 uses transistors with different threshold voltages. When the computer system is in sleep mode, a group of transistors with extremely low threshold voltages are used to operate; The gate contact can be triggered even when the voltage of the supply signal is very small. The low critical voltage transistor provides a non-zero voltage at a node. If the low critical voltage transistor does not work, the node will be grounded. The other group of transistors has a normal threshold voltage, and its source terminal is connected to the node. When recovering from the sleep mode, the group of transistors cannot be triggered, but can be triggered when recovering from a full power down state. Making integrated circuits with different threshold voltage devices is a costly and difficult process, which may require multiple photomask process steps. Therefore, in the conventional technology, a power-on reset circuit is required. All the transistors have The threshold voltage is substantially the same, so that the power-on reset circuit can provide a power-on reset signal in response to a supply signal with sufficient voltage, except when recovering from a sleep state. There is more

Page 7 200422817 V. Description of the invention (3) The need for a circuit that generates a power-on reset signal with temperature immunity, ultra-low DC leakage current, and a fast power-down response. SUMMARY OF THE INVENTION The present invention includes a power-on reset circuit. When a supply signal increases from a voltage of zero or near zero (associated with a complete power-down state), it can provide a power-on reset signal in response to a supply signal. Increase, and when the supply signal starts to increase from a non-zero voltage (associated with a sleep state), the power-on reset signal can be suppressed, changing to the 'associated with a complete power drop (p 0 werd 〇w η) state The power-on reset signal is provided in response to a supply signal that is increased from zero supply voltage to an operating voltage, but the power-on reset signal is not provided in association with a sleep state and should be increased from a non-zero voltage to an operation Supply voltage signal. Further, the present invention includes a power-on reset circuit, which can provide a power-on reset power supply with reduced amplitude when a supply signal is reduced from the operating voltage to a voltage of zero or close to zero (associated, falling state). The number k should correspond to the decrease in the supply signal, and when the supply signal starts to increase from a zero or near zero voltage (associated power supply down state) to the operating power ^ 'can provide a larger amplitude power on reset signal to The increase in signal should be supplied. On the one hand, the present invention can meet the above requirements by, for example, providing a power-on reset circuit. All the electric crystals in the power-on reset circuit have substantially the same threshold voltage. On the other hand, the power on

Page 8 200422817

V. Description of the invention (4) The reset circuit includes a voltage divider surface. The power supply and the reset circuit package can provide a very low purpose when the signal is received. When Schmitt triggers the electrical recovery, it can be achieved by For example, when providing a low power state recovery, the need to provide a consistent threshold voltage. The Schmitt procedure is applied when the voltage drops from the state. Temperature variation according to another aspect of the present invention provides thermal compensation. To the extent that any feature stated herein is provided, as long as there is no apparent conflict between these texts, the description, and the field. In order to describe the clear viewpoints and advantages of the present invention, not all viewpoints, advantages, or specific embodiments. In the following, additional advantages and viewpoints of the present invention follow a supply signal, and a voltage divider is included in another aspect. Tracking this supply DC leakage current. According to the circuit of the present invention, when a trigger voltage threshold value is dropped from a complete power supply, and when another trigger voltage is used to eliminate the transition from a non-operational power supply to a complete trigger circuit, a trigger can be provided. Circuits can be included, responded or combined in any combination of the features of the present invention = with the knowledge of ordinary artisans to summarize the purpose of the present invention, here are the new features, of course, you can understand the features, must be included The scope of the present invention = detailed description and patent application will be obvious. Embodiments The accompanying drawings proposed in the present invention are referred to. As far as possible, preferred embodiments of the same or month will be described in more detail and explained with reference to the same or similar drawings, and are used in the drawings without precise dimensions. The diagram is a simplified diagram. The disclosure is used here for related companions.

200422817 V. Description of the invention (5) The direction of the drawing is above, convenient and clear. The explanation is limited to the way of the example, although it describes the traditional process of the complete process stated here by applying for the invention. The manufacturing process used by the product is generally used to indicate that this number and temperature are free from power on unless the name is special; ^ should be regarded as a "critical value", "Lin ^" means a voltage; usually "-Names, such as up, down, left, right, up, down, at, below, behind, and front, are for the purpose of illustration only, and in any case such direction names do not make the scope of the invention This disclosure refers to certain illustrated embodiments, and is proposed in a non-limiting manner so that its content can be understood. Exemplary embodiments, but the purpose of the detailed description below is to define the spirit of the invention And scope to cover this modification, change, and equivalent. It can be understood and appreciated that the process steps and structure do not include the power supply system manufacturing process, the present invention may be applied In the field of prismatic technology, only the most general steps are included here to help understand the present invention. The present invention is used in the field of semiconductor components and processes. However, for the purpose The following statement is an example of a circuit with a supply of epidemic and ultra-low DC leakage current and fast power supply collapse response. Do not specify, π voltage ", π signal "," level "and" threshold value good indication " Voltage, for example, the name "supply signal VDD" should be provided to the voltage of the power-on reset circuit, and the comparison between voltages should be regarded as the same voltage drop between voltages "throughout this statement One dollar difference, this voltage difference is approximately equal to any thunder ^ ^ ^ ^ -6 »The boundary voltage drop should be a pressure difference of approximately 0.6 volts, but 200422817 V. Description of the invention (6) 疋 It should be understood that if different The transistor will have different values. In this illustrative embodiment, the critical voltage of any transistor in the power-on reset circuit is substantially the same as the Sft boundary voltage of all other transistors in the power-on reset circuit. With. Although other embodiments may use 1 ^ 103 with different Vt, in this illustrative embodiment, only the single Vt of Sin 3 and the Schmitt trigger circuit are used to determine the power reset trigger level. The power is turned on / off. The voltage is determined according to a reset signal. When the supply signal VDD is unstable, a low-end resistor R2 is connected to the node LB to track VDD. This is different from some known systems. In these known systems, In order to reset the power on, the system uses M0S elements with different Vt. In this system, because the PM0S is used to reduce the DC leakage current, the power reset trigger level may be reduced to 1 · 2 Volts. Referring to a more specific diagram, FIG. 1 is a simple schematic diagram of a power-on reset circuit according to an embodiment of the present invention. The power-on reset circuit shown in the figure includes a voltage divider 10 and a compensation circuit 2. A Schmitt trigger circuit 30, a supply coupling capacitor 40, a first inverter XI, a ground coupling capacitor 60, and a second inverter χ2. 2 is a detailed diagram of a power-on reset circuit according to an embodiment of the present invention. The power-on reset circuit includes the voltage divider 10, the compensation circuit 20, the Schmitt trigger circuit 30, the Supply coupling capacitor 40, the first inverter XI, the ground coupling capacitor 60, the second inverter X2, and a third inverter X3. Continue to refer to FIG. 1 and FIG. 2, the voltage divider 1 The purpose of 〇 is to

Page 11 200422817 V. Description of the invention (7) No matter how the power supply of the circuit changes, such as thermal changes, no matter what power is supplied to the power supply, such as a thermal change, provide a stable < power + voltage to the Schmitt trigger input node LB to Track VDD. Since the stable voltage is provided as the input of the Schmitt trigger circuit, the voltage at the Schmitt trigger input node LB can be considered as a trigger voltage. Device 10 includes a current source transistor M1, a diode transistor M2, a transistor M4, a high-side resistor R1, and a low-side resistor 1 ^ 2. A compensation transistor M7 and a buffer capacitor (using a buffer) are provided. Transistor M8 is implemented) is connected in parallel with the low-side electrical device I1 and R2. A gate-source voltage (equal to VD ^) across the current source transistor ** 1 generates a main current through the current source transistor M 1 and the triode transistor M2, and substantially all the main current flows Through the transistor M4 (its gate-drain voltage is equal to the gate-source voltage of the diode transistor 112), the high-side resistor R1 and the large low-side resistor R 2 through which the main current passes are regarded as maintaining the history. The voltage divider 100 for the input voltage at the input node LB of the Mitte trigger. The function of the compensation circuit 20 is' even if voltage transients, current transients, and // Or the thermal drift of voltage and current, the voltage of the Schmitt trigger input node LB is still maintained at a fairly stable voltage. The compensation circuit includes a CMOS inverter (including a PM0S compensation control transistor M5 and a MNM0S compensation control transistor M6) and a compensation transistor M7. The gate extremes of the PM0S compensation control transistor M5 and NOMS compensation control transistor M6 are connected to the node LA. The PM0S compensation control transistor M5 and NOMS compensation control transistor M6 source

Page 12 200422817 V. Description of the invention (8) The extreme points are respectively coupled to the supply signal VDD and the ground potential. The drain extreme points of the pM0S compensation control transistor M5 and NOMS compensation control transistor M6 are connected to the compensation. The gate extreme point of transistor M7 forms the compensation transistor gate extreme node LB1. In addition to conducting the main current from the current source transistor M1 to the transistor M4, the diode transistor M2 also generates a voltage at the node LA, which voltage increases as the main current increases, in other words, the The current source transistor M1 and the transistor M4 are regarded as resistance-like elements, and the diode transistor is regarded as a diode. Increasing the current through the current source transistor M 丨 will cause a voltage at the point LA 1 Increase, in addition, such an increase in current will lead to an increase in the source voltage (ie, node 1 A) of the monolithic body M2; since the transistor M4 is also a resistance-like element like the transistor M1, the Schmitt The voltage at the input node LB also increases. Therefore, the voltages at the nodes LA, la 1 and lb are all proportional to the current through M 1 and the power supply voltage. If the main current is increased, for example, the voltage-current relationship of the current source transistor M1 is changed due to a thermal change (eg, an increase in temperature), and the voltage at the node ^ is increased. As a result, the CMOS inverter (ie pm0S compensation control) Transistor M5 and NMOS compensation control transistor M6) provide a compensation control voltage, which is reduced to the gate terminal of the compensation transistor M7. When the temperature increases, any transistor that suppresses the feedback current flowing through the compensating transistor M7 is matched to maintain a fairly stable; the force is passed through: The resistance R2 'makes the input at the Schmitt trigger The Schmitt trigger input voltage at node LB thus remains stable. A small leakage current passes through the voltage knife 10 and the cut-off transistor M3 (its function is the same as a small variable current

200422817 V. Description of the invention (9) Source) 'prevents the voltage on this node LA from drifting too far due to the supply signal VDD. On the other hand, any decrease in the main current flowing through the current source transistor M 丨, for example, due to a decrease in temperature, will reduce the voltage at the node ^, so that the voltage at the gate of the compensation transistor M7 increases. And further promote current to flow through the compensation transistor M7, for example, because the temperature is lowered, the current will not flow through R2. In this embodiment, although the main current fluctuates, the current through the low-side resistor R 2 remains substantially stable. ’

Figure 3 is an embodiment of the present invention, a set of analog current source transistor Ml: node LA1 and Schmitt trigger input node LB in time "sound diagram is not, Figure 4 is according to an embodiment of the present invention, a set of simulations. The response X of the Schmitt trigger input node LB under various supply voltages is shown in Fig. 4. On the first board (a ", the supply signal diagram is 2). The voltmeter input is ΓΐΠ25. At 25t and 85 ° C, the Schmidt contact is almost overlapped. In the second panel (panel 2), the supply is -2: 2 牿 3 volts and the temperature is _25 〇c, 25 And at 85 o'clock, "history ^ The graph of the voltage value of the input node LB of the handle trigger in time, f is 3.7 units, and the temperature is -25 ° c, 25 °, and 85 °, ' History, special trigger input node LB voltage value in time

The two figures in the Eighth Middle School are almost daylight. The Smith system is used as a capacitor to gently trigger any transient changes in the voltage on the Is input Lang point L Β at this symbol.

200422817 V. Description of the invention (10) The purpose of the Schmitt trigger circuit is to provide a power-on reset signal 'if the voltage of the supply signal VDD increases from the ground potential (or from a voltage of zero', such as 1 volt), then The voltage value of the power-on reset signal increases with the voltage value of the supply signal VDD, and decreases rapidly when the supply signal VDD exceeds a threshold voltage. (By rising and then falling rapidly, the Schmitt trigger circuit can generate a power-on reset signal at the inverter at the output of the Schmitt trigger circuit.) If the supply signal VDD is from any one that is significantly greater than the ground potential The voltage value starts to increase (for example, resume from hibernation state), then the power f of the power-on reset signal remains close to zero (that is, at the ground potential). In addition, the power-on reset and signal amplitude decrease from the operating voltage in response to the supply signal The level of zero or near zero power decreases (associated power down state), and conversely, the amplitude of the power-on reset signal increases as the supply signal increases from zero or near zero voltage (associated power down state) to the operating voltage. The operation of these transistors as variable resistors may help to understand the operation of the Schmitt trigger. In these transistors, the source of each transistor and the "resistance value" between them are Controlled by the gate voltage, when the gate voltage of an NMOS transistor is increased, between the source and the $ of the NMOS transistor, the resistance value decreases, and when a PM0S transistor is As the gate voltage increases, the "resistance value π" between the source and the drain of the PMOS transistor increases.

^ The Schmitt trigger circuit includes a PM0S initialization transistor M10, a _Mitt trigger transistor Ml1, a disable transistor, an Rc transistor M13, and a feedback transistor M14. The PM0S initial

Page 15 200422817

The 4 d electrical point LB is connected to the crystal M10. The -gate terminal is coupled to Smith, a source terminal is connected to the supply signal VDD, and a 2, where f has an extreme threshold to the enhanced transistor source. Reset signal training. The NM0S Schmitt trigger transistor is: the gate terminal is coupled to the Schmitt trigger input node, and the drain terminal is connected to the reset signal node T1, and the drain terminal is strengthened by: f node T3. The disabling transistor μ 1 2 and; # ρ〇 'Schmitt trigger input node LB, a source terminal is coupled to the neighboring @ # node T3, and a drain terminal is coupled to a ground potential. The feedback body M14 has a gate terminal coupled to the reset signal node ^, an x terminal is coupled to the critical strengthening node τ 3, and a drain terminal is responded to a signal VDD. 4

The Schmitt trigger circuit responds to the change in the supply signal VDD seen in the source knowledge of the PM0S initialization transistor 10 to achieve the purpose of the reset circuit of the transistor, in the voltage divider. And the cut-off transistor M9 maintains a fairly small voltage difference between the gate source extremes of the PMOS initialized transistor M10 and the NMOS history of the gate extremes of the pMOS initialized transistor M10. A considerable voltage difference is maintained between the Mitte trigger transistor M11 and the source terminal M of the disabling transistor 02, and therefore, during normal operation, such as =. When the supply signal VDD is at its operating voltage, the voltage acting on the input node LB of the Schmitt 2 generator is large enough to enable the conduction between the NMOS Smitt trigger transistor Mil and the disabling transistor M12.

In particular, during normal operation, when the supply signal VDD is at its operating voltage, the voltage on the Schmitt trigger input node LB allows the transistor Mn and the disabling transistor to be triggered by the NMOS Smith. Ml2

200422817 V. Description of the invention (12) The current is much larger than that of the PM0S initialization transistor M10. The high voltage at the Schmitt trigger input node LB makes the PM0S initialization transistor M10 have a very high impedance. However, the NM0S Schmitt trigger transistor M 1 1 and the disabling transistor M 1 2 have a very low impedance. Therefore, during normal operation, the reset signal node T 1 and the critical strengthening node T 3 are released. All remaining charges in the NMOS schmitt trigger transistor M11 and the disabling transistor M12 are triggered.

FIG. 5 is a diagram illustrating the response of a group of simulated reset signal nodes T1 (11) and a critical strengthening node T3 (t3) to supply signals $ VDD (vdd) at various levels according to an embodiment of the present invention. In particular, the upper panel is the time pattern of the supply 1 signal VDD, while the lower panel is the time pattern of the reset signal node T1 and the critical strengthening node T3 corresponding to the first panel supply signal VDD. The solid line indicates the reset signal node, and the dashed line indicates the critical strengthening node T 3. In the simulation diagram used for illustration, when the supply number VDD is at its operating voltage, the reset signal node T1 and the critical strengthening The node T3 is zero. In this simulation, the supply signal VDJ) is about 3.3 volts. FIG. 6 is a set of explanations when the supply signal VDD transitions through the initial power-up, sleep mode, power-down, and subsequent power-up,

The response of the pulse (corresponding table reset signal node τ 丨) to the supply IVDD at various levels is shown graphically. Starting from the initial power rise, the supply signal is approximately 0 volts at the initial level. At this low level, the Smith contactor input node LB is low enough to allow the "03 initialization transistor to pass" so that The reset signal node T1 tracks the supply signal ¥ 1) 〇,

200422817 V. Description of the invention (13) Similarly ‘the Schmitt trigger transistor 乂 1 and the disabling transistor 丨 2 are cut off’ and the critical strengthening node T3 is low voltage. When the supply signal VDD rises, the reset signal node T1 continues to be charged by the current from the PM0S initialization transistor M 1 0 until the potential of the reset signal node τ 丨 is large enough to turn on the feedback transistor M14. When the feedback transistor M14 is turned on, the critical strengthening node T3 is passed by the supply signal VDD through the feedback transistor, and the current generated at M 1 4 is charged. After charging begins, the critical strengthening node T3 raises the threshold voltage of the NMOS Schmitt trigger transistor M11, so that the Schmitt trigger input node LB cannot easily turn on the Schmitt trigger. This phenomenon is reflected in The relationship between a larger pulse A (where the critical strengthening node 'point T3 is charged) and a smaller pulse B (where the critical strengthening node T3 is not charged). When the supply signal continues to rise, the potential of the Schmitt trigger input node LB will become large enough to cut off the transistor M 1 0 initialized by the PM0S and turn on the Schmitt trigger transistor μ 1 1 and the loss at the same time. The energy transistor M 1 2 discharges electric charges from the reset k vanishing point T 1 and the critical strengthening node τ 3. In this description, when the supply signal VDD reaches an operating voltage of about 2.7 volts, the potential of the Schmitt trigger input node LB is about 1.5 volts, which is large enough to turn on 乂 1 〇 to the The reset signal node T3 is charged, and the potential is sufficient to turn on the Schmitt trigger transistor M11 and the disabling transistor M12 to discharge charges from the reset signal node T1 and the critical strengthening node τ 3. Since the critical strengthening The Lang point T 3 is not charged, and the threshold voltage of the Schmitt trigger transistor does not increase. The threshold voltage is reflected in the relatively small pulse B, stated as follows. 200422817 V. Description of the invention (14) _ Anihiro: ref .; Figure 6, the sleep mode is defined to occur when the confession is provided. The ground potential can be located at the electrical a-phase P · initialization potential of the // signal _ which is not low enough to charge the reset signal node T1, 卄; the special input node LB has a relatively high potential, so The Schmitt trigger said that the nrw transistor = the transistor MU and the disabling transistor two Λ :, without charging the reset signal node T 1. ^ In the sleep mode, a power-down operation is entered, and the supply signal VDD is switched from its operating voltage to two approximately zero voltages. ^ In this description, the approximately zero voltage is approximately 1 volt. Before the power supply drops, the supply signal VDD has a value of 2, and the Smith% special trigger input node 1 has a potential of about 15 volts. The 5 volts: 5: Turn on to charge the reset signal node T3. And the potential of 1.5 volts is enough to turn on the Schmitt trigger transistor

Mil and the disabled transistor M12 take the reset signal node τι and the critical point [point: ί charge, because the critical strengthening node T3 is not charged! 4 = the threshold voltage of the special trigger transistor Mu is not raised L ί is reflected in About small pulse B. When the supply signal ㈣ ϋ Ϊ μ ^ Λ the potential of the node LB drops, the PM0S initialization circuit M10 will turn on the current through the Schmitt to trigger the transistor M1 i and lose power.

Η

200422817 V. Description of the invention (15) Energy transistor M12, but the current cannot be effectively cut off; and the PM0S initialization transistor M1 will pass = history "when the transistor is triggered and the transistor II is disabled. A large current will begin to charge the reset signal node n to a bit ^. The / set signal node T1 will reach-sufficient to turn on the wide potential of the feedback power M14 to charge the critically enhanced node T3. After charging μΙι, the ^ # world invites to strengthen ^ point 73 to increase the boundary voltage of the NMOS schmidt trigger transistor Mil, so that the pass of Schmitt trigger turns on and off = trigger, this phenomenon is reflected in the later comparison Large pulse ^ Easy to open During the power-down mode, the supply signal V.DD is maintained at a potential of 1 volt, and the Schmitt trigger input node "maintains a very low potential (eg, about 0.2 volts) In order to allow the PM 0s initialization transistor M1 0 to be turned on, the reset signal node T 1 can track the supply signal. Similarly, in this history, the special transistor Mil and the disabled transistor M12 are turned off, and the critical strong node T3 is turned off. Still being charged. After leaving the power-down mode, when the supply signal VDD starts to rise, the potential of the Schmitt trigger input node LB becomes large enough to turn off the PM0S initialization transistor mi 0 and turn on the Schmitt trigger transistor M 1 1 And the disabling transistor M1, 2 to discharge the charge from the reset signal node T1 and the critical strengthening node D3. Referring back to FIG. 3, the leakage current through the low-side resistor 1-2 can be limited by using a very large resistor as the resistor, due to the power consumption of the low-side resistor R2 (which can be considered as a loss of heat and battery life). Approximately V 2 / R 'so the low-side resistance R 2 of the south resistance value can limit bad leakage

Page 20 200422817 V. Description of the invention (16) The current effect, where V is the voltage on the Schmitt trigger input node lb, and R is the resistance value of the low-side resistor R 2. Since the voltage at the Schmitt trigger input node LB is approximately IR, a low-side voltage R 2 with a suitably high resistance value allows the voltage at the Schmitt trigger input node LB to have a low The main current is maintained, and the standby current between 2 · 6 to 3 · 8 volts and-40 to 100 ° C is less than 10 u A. Reset signal levels between 2 · 6 to 3 · 8 volts and-40 to 100 ° C are accurate. Four serial digital inverters receive the voltage of the reset signal node τ 丨. In the first inverter, the voltage of the reset signal node τ 丨 is applied to the PM0S output driving transistor M16 and NM0S output drive electric '^

At the gate of M 1 7, when the voltage of the reset signal node τ 1 increases, the voltage at the output node T 2 decreases; when the voltage of the reset signal node τ 丨 decreases, the output node T 2 The voltage increases. The reset signal node T 1 is also coupled to a supply coupling transistor M15, and the output node T2 is bridged to a ground coupling transistor M18. The transistors M15 and M18 are used as a capacitor. . The second inverter X2, the second inverter X3, and the fourth inverter χ4 provide a buffer current to the output.

FIG. 7A is a diagram illustrating the response of a group of reset signals in time according to an illustrative embodiment of the present invention. The reset signal is obtained by measuring the output terminal of the fourth inverter χ4, and the signal is equivalent to The reset signal node n. In the first panel, the voltage waveform of a 2 · 7 volt supply signal VDD is described, and when the second panel is at _25 t, the reset signal corresponds to the time pattern of the first panel supply signal VDD. The third panel is attached at 25

200422817 V. Description of the invention (17) c. The reset signal corresponds to the graph of the first panel supply signal VDD in time. The fourth panel is at 85 ° C. The reset signal corresponds to the first panel supply signal. Graph of VDD in time. FIG. 7B is a response diagram of a set of reset signals in time according to an embodiment of the present invention. The reset signal is obtained by measuring the output of the fourth inverter χ4, and the signal is equivalent to the reset. Signal node η. In the first =, 'indicates the voltage waveform carried by the supply signal of -3.3 volts, while the graph of ΐ ί, the third panel is at 25 ° C, and the fourth panel is at 8 5 tΞ Ϊ: JV 二In the shape of the shape, the figure of the number VDD in time. The reset corresponds to the plastic embodiment of the first panel supply letter. A set of reset signals is at the upper end of time: J:% ΐ ί 系 measures the output of the fourth inverter X4 ΪΓΐ J: 3 7: At the reset signal node T1. In the first-the second panel is a voltage waveform of -2 "ci, and the signal VDD should be a graph of the time TUJ. The first-panel supply signal pair ^ = is at 25t, and the heavy double voltage should be k ^ VDD The fourth panel is at 85. (: The pattern of resetting on Yujian, the number of VDD in time. Figure corresponding to the first panel supply letter in Figure 8 A according to The response diagram of the present invention f is shown in the first panel with :, and the waveforms of various signals in time VDD and time in the graph board 'seven supply-3.3 volts supply voltage and the second panel provides the first Quadrature

200422817 V. Description of the invention (18) The reset k number at the output of the X4 device corresponds to the graph of the first panel supply signal νρρ in time. The third panel provides the node LA potential corresponding to the first panel supply signal VDD at the time. On the graph, the fourth panel provides a graph of the Schmitt trigger input node LB potential corresponding to the first panel supply letter VDD in time. ~ ° Fig. 8 B is a set of various signals that sound vtn in time according to an embodiment of the present invention. In the first panel, a "3. 3 volt supply voltage / / Λ Λ waveform diagram" and the second The panel system provides the compensation voltage: T :: Lang point LB1 potential corresponding to the first panel supply signal vdd, the third panel provides the reset signal node τι, and the bit f should be 5 Hz. The first panel supply signal VDD is at In the shape of time, this fourth panel provides zinc for the entire circuit. The circuit board can be used to w ® & the four sides of the vnn produce μ ι »^ 峪 〃mechanical and electrical equipment, L corresponding to the first panel supply signal Graph of VDD in time. # m According to the circuit of the embodiment of the present invention illustrated in FIG. 2, it can be ^ 1. In the system, the computer system includes a memory for storing the sub == 7 and > material, a bus coupling To the memory, and a micro processor = ί 1, or multiplexed microprocessor) according to the instruction in response to the control signal and processing,-shell material. The computer system includes the power-on reset circuit to generate a power-on reset signal to the microprocessor. In order to determine a power reset trigger level, the power-on reset circuit includes a plurality of Schmitt trigger circuit composed of M0S elements. The power reset trigger level is determined by the voltage at the critical strengthening node τ 3. The power reset trigger level includes a voltage divider connected to the input of the Schmitt trigger circuit to track the supply signal VDD. The voltage divider package

Page 23 200422817 V. Description of the invention (19) Including a current source response signal, such as the low-end value of the source resistance of transistor M1, the high-resistance value uses the power supply to turn on a small reset pulse, such as the micro The recompensation circuit responds to the current by the Schmitt source to reset the input node LB of the Schmitt source and a first critical point T3, which is lower than the first and enters sleep by a ground potential circuit. When the mode boundary voltage is compared to the ground potential type, the reset response should be made. A current is generated from the above crystal, for example, the current source transistor M1 in response to a supply signal VDD (obviously, connected to the current source). The voltage divider includes a high resistance, in particular, the low-side resistance R2, which is used to reduce leakage current. In addition, the setting circuit further includes a compensation circuit to generate a micro-compensation due to the effect of temperature and supply signal fluctuations. For example, the pulse current is passed through the compensation transistor M7. The change, for example, temperature change, adjustment A feedback voltage on the input terminal of the Schmitt trigger circuit, such as & current flowing through the compensation transistor M7, includes a reset signal node corresponding to electricity. The Schmitt trigger circuit compares the Schmitt trigger voltage (the voltage is related to the voltage of the supply signal). The voltage of the first threshold voltage is set by the critical strengthening section # ί No. 1 node has a voltage. The critical voltage of the supply signal, when the supply signal rises, the voltage rises, a first voltage. If the Schmitt trigger type, * the supply signal does not smoothly match the voltage of the first signal node of the reset signal by the third voltage drop. If the Schmitt trigger circuit does not enter the sleep mode node generally There is no counter-narration of the change in the supply signal, and those who are familiar with the art in this field will

200422817 V. Description of the invention (20) It is understood that the method of the present invention can gain the structure of the power supply circuit ', especially the power-on reset of the power supply circuit. The embodiments provided above as examples do not limit the scope of the present invention. For those skilled in the art, the disclosed embodiments may be changed or adjusted according to the spirit of the foregoing detailed description. For example, adjusting these embodiments may include one or more compensations of various / different aspects. Circuit, voltage divider, and Schmitt trigger circuit. In addition, for those skilled in the art, other combinations, removals, substitutions, and modifications of the embodiments disclosed herein will be obvious. Therefore, The present invention is not limited to the disclosed embodiment 1, but is determined by the scope of patent application. /

Page 25 200422817 Brief description of the drawings Brief description of the drawings FIG. 1 is a schematic diagram of a power-on reset circuit according to an embodiment of the present invention, and FIG. 2 is a detailed diagram of a power-on reset circuit according to an embodiment of the present invention; FIG. 3 shows the time series of a group of analog current source transistors Ml (ml), node LA (la), node LAl (lal), and a Schmitt trigger circuit output node LB (1b) according to an embodiment of the present invention. Response diagram; Figure 4 is a set of simulation diagrams of the response of node LB under various temperatures and supply voltages according to an embodiment of the present invention; ^

FIG. 5 is a diagram illustrating the response of a set of reset signal nodes T1 (tl) and critical strengthening nodes T3 (t3) to various levels of supply signals VDD (vdd) according to an embodiment of the present invention; FIG. 6 is based on In the embodiment of the present invention, a set of simulation supply signals at various levels when the supply signal VDD transitions through the initial power-up, sleep mode, power-down, and subsequent power-up is applied to various levels. The response diagram of VDD, this signal corresponds to the signal on the reset node T 1; ^ FIG. 7A is a set of simulations according to the embodiment of the present invention, when the supply signal VDD is 2.7 volts' Response graph

FIG. 7B is a time response diagram of a reset signal to various temperatures when the supply signal VDD is 3.3 volts according to an embodiment of the present invention; FIG. 7C is a set of analog time supply signals VDD according to an embodiment of the present invention Time response graph of reset signal to various temperatures at 3.7 volts;

Page 26 200422817 Schematic illustration Figure 8A is a time response diagram of a set of analog supply signal VDD, reset signal node T1, node LA and Schmitt trigger input node LB to various temperatures according to an embodiment of the present invention And FIG. 8B is a response diagram in time of a set of analog supply signals VDD, a compensation thyristor extreme node LB1 (lbl), a reset signal node T1, and a standby current of the entire circuit according to an embodiment of the present invention. Description of figure symbols 10 Voltage divider 20 Compensation circuit 30 Schmitt trigger circuit 40 Supply coupling capacitor 60 Ground coupling capacitor

Page 27

Claims (1)

200422817 6. Scope of patent application Patent scope of application 1. A power-on reset circuit, comprising: a Schmitt trigger circuit composed of a plurality of M0S elements with a threshold voltage vt to determine a power reset trigger level; And a voltage divider connected to the input of the Schmitt trigger circuit for tracking a supply signal. 2. If the power-on reset circuit of item 1 of the patent application scope includes a compensation circuit to generate a tiny reset pulse to compensate for the temperature and the effect of the supply signal. > 3. If the power-on reset circuit of item 1 of the scope of patent application, / wherein the voltage divider includes a current source transistor to generate a current in response to a supply signal. 4. The power-on reset circuit of item 1 of the patent application range, wherein the voltage divider includes a low-end resistor with a high resistance value to reduce leakage current. 5. The power-on reset circuit of item 1 of the patent application range, wherein the voltage divider includes a compensation circuit that adjusts a feedback current in response to a change in the supply signal to maintain the current at the input of the Schmitt trigger circuit. Voltage. 6 · If the power-on reset circuit of item 1 of the patent application scope, wherein the Schmitt trigger circuit further includes a critical strengthening node, when the Schmitt trigger circuit enters or leaves the power down mode, the node has a greater than The first voltage is zero. When the Schmitt trigger circuit enters or leaves the sleep mode, the node has a second voltage smaller than the first voltage. 7. The power-on reset circuit such as the one in the scope of patent application, where Page 28 200422817 6. Scope of patent application The Schmitt trigger circuit further includes a reset signal node. If the Schmitt trigger circuit does not enter a sleep mode, when the supply signal is compared with a first threshold voltage, Should the supply signal increase, the node rises from the ground potential to a first voltage. When the supply signal is not compared with the first threshold voltage, the node drops from the first voltage to the ground potential. 8. If the power-on reset circuit of item 1 of the patent application scope, wherein the Schmitt trigger circuit further includes a reset signal node, when the Schmitt trigger circuit enters a power down mode, the node has a first A 1 voltage peak, when the Schmitt trigger circuit leaves the power-down mode, the node has a second voltage peak greater than the first voltage peak. 9. The power-on reset circuit according to item 8 of the patent application, wherein when the Schmitt trigger circuit enters and leaves a sleep mode, the reset signal node has a third voltage smaller than the first voltage peak. 10. —A method for providing a reset signal in response to a supply signal, including the following steps: a main current is generated in response to the supply signal; a trigger voltage is generated in response to the main current; if the sleep mode is not entered and the supply signal is not connected to a When the first critical level is compared, the reset signal is increased from a reference potential to a first potential in response to an increase in the supply signal; and when the supply signal is compared with the first critical level without entering the sleep mode, Set the reset signal to the reference potential. 1 1 · The method of item 10 in the scope of patent application, where: Page 29 200422817 6. Scope of patent application When entering the power-up state, the reset signal should increase from the reference potential to the first potential due to the increase of the supply signal; when entering the power-down state, the reset signal is due to The decrease in the supply signal should be increased from the reference potential to a second potential; and the first potential is greater than the second potential. 1 2. The method according to item 11 of the scope of patent application, further comprising compensating the trigger voltage in response to a change in temperature, wherein compensating the trigger voltage in response to a change in temperature includes the following steps: 'Provide a main current path with a current Corresponding to the trigger voltage; and having a complementary temperature coefficient associated with a current source in a circuit, adjusting the current of the main current path to compensate for changes in the temperature-dependent current. 13. The method of claim 12, wherein adjusting the current of the main current path to compensate for changes in the temperature-related current includes: providing a compensation path in parallel with the low-end portion of the current path; and responding to the main The reduction of the current increases the compensation current on the compensation path, and reduces the compensation current on the compensation path in response to the increase of the main current. 14 · A computer system including: Page 30 200422817 VI. Patent application scope A microprocessor; a bus coupled to the microprocessor; a memory coupled to the bus; and a power-on reset circuit to generate electricity Signal to the microprocessor, the power-on reset circuit includes: a Schmitt trigger circuit, consisting of a plurality of M0S elements, to determine a power reset trigger level and a voltage divider, connected to The Schmitt trigger terminal is used to track a supply signal. ‘15 • If the computer system of item No. 14 of the scope of patent application, turning on the reset circuit further includes a compensation circuit to generate a micro to compensate for the temperature and the effect of the supply signal. 16 · If the computer system of item 14 of the patent application scope, the voltage divider includes a current source transistor to supply the signal current. 1 7. If the computer system voltage divider of item 14 of the scope of patent application includes a high-resistance low-end resistor to reduce the leakage current 1 8 · If the computer system voltage divider of area 14 of the patent application includes a compensation circuit It should be maintained at the input terminal of the Schmitt trigger circuit according to the variable current of the supply signal. If the special trigger circuit of the computer system under item 14 of the patent application includes a reset signal node, Boundary voltage Vt; take the circuit's turn-in, where the power reset pulse, where the voltage to generate an electric current, where the voltage flows. , Where the voltage will be adjusted once. , Where the Schmitt-triggered electricity Page 31 200422817 6. The patent application range does not enter a sleep mode. When the supply signal is compared with a first threshold voltage, the node rises from the ground potential to a first voltage due to the increase in the supply signal, and when When the supply signal is not compared with the first threshold voltage, the node drops from the first voltage to the ground potential. 20. The computer system according to item 14 of the scope of patent application, wherein the Schmitt trigger circuit further includes a reset signal node, in addition to not entering or leaving the sleep mode, whether during power-up or power-down mode In response to a change in the supply signal, the node rises from a ground potential to a first voltage. 2. 21. The computer system according to item 14 of the scope of patent application, wherein: The Schmitt trigger circuit further includes a reset signal. During the power-up mode, the node should be connected to a ground potential in response to a change in the supply signal. Rises to a first voltage, during the power-down mode, the node rises from the ground potential to a second voltage in response to a change in the supply signal; and the first voltage is greater than the second voltage. # Page 32