TW200421600A - Split gate flash memory cell and manufacturing method thereof - Google Patents

Abstract

A split gate flash memory cell comprises a substrate having a trench; a stack structure consisted of a tunneling dielectric layer, a floating gate and a cap layer is set on the substrate; a first inter-gate dielectric layer and a second inter-gate dielectric layer is set on the sidewalls of stack structure, and the first inter-gate layer is adjacent to the top of trench; a selecting gate is set on the sidewall of first inter-gate dielectric layer and the trench; a selecting gate dielectric layer is set between the selecting gate and the substrate; a source region is set in the substrate next to the second inter-gate dielectric layer side of stack structure; and a drain region is set in the bottom of trench next to the side of selecting gate.

Description

200421600 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a semiconductor device, and more particularly to a split gate flash memory cell and a method for manufacturing the same. [Previous technology] Flash memory devices have become a personal computer and an advantage because they can store, read, and erase data multiple times, and the stored data will not disappear even after power is turned off. A non-volatile memory element widely used in electronic equipment. A typical flash memory device is made of doped polycrystalline silicon to make a floating gate and a control gate. Moreover, the floating gate and the control gate are separated by a dielectric layer, and the floating gate and the substrate are separated by a penetrating oxide layer (T u η n e 1 0 X i d e). When writing / erasing (Write / Erase) data to the flash memory, the control gate and source / drain regions are biased so that electrons are injected into the floating gate or Pull the electrons out of the floating gate. When reading the data in the flash memory, a working voltage is applied to the control gate. At this time, the charged state of the floating gate will affect the on / off of its lower channel (Channel), and the opening of this channel / Off is the basis for interpreting the data value "0" or "1". When the above flash memory is erasing data, because the number of electrons discharged from the floating gate is not easy to control, it is easy to cause the floating gate to discharge too many electrons with a positive charge, which is called excessive erasure. -erase). When this over-erase phenomenon is too serious, even the channel below the floating gate will be turned on when the control gate is not applied with operating voltage.

10847twf. Ptd Page 6 200421600 V. Description of the invention (2) State, resulting in misjudgment of information. In order to solve the problem of excessive erasure of components, the industry currently proposes a split gate (S p 1 i t G a t e) flash memory. Figure 1 shows a structural cross-sectional view of a conventional split-gate flash memory cell. Please refer to Fig. 1. This flash memory cell starts from the substrate 100, and is a tunneling dielectric layer 10 in sequence, a floating gate electrode 104, and an inter-gate dielectric layer 106 (I nter- gate Die 1 ectric) and selection gate 1 0 8, in addition to the selection gate 1 0 8 above the floating gate 1 0 4, there is still a portion extending above the substrate 1 0 0, and the substrate 1 0 The 0 gates are separated by a selected gate dielectric layer 110. The source region 1 1 2 is located on the substrate 1 0 0 on the side of the floating gate 1 0, and the drain region 1 1 4 is located on the selection gate 1 0 8 on the side that extends to the substrate 1 0 0 0 in. In this way, when the over-erase phenomenon is too serious, and the channel below the floating gate 1 0 4 is continuously opened without selecting the operating voltage of the gate 1 08, the channel below the selected gate 1 0 8 is still open. It can be kept in a closed state, so that the drain region 1 1 4 and the source region 1 1 2 cannot be conducted, and the misjudgment of data can be prevented. However, since the separated gate structure requires a larger separated gate area and a larger memory cell size, its memory cell size is larger than that of the stacked gate structure, which results in the so-called inability to increase the component accumulation. problem. Moreover, as integrated circuits are being developed towards smaller components with higher integration, the size of the memory cell can be achieved by reducing the gate length of the memory cell. However, a smaller gate length shortens the Channel Length under the tunneling oxide, so when this memory cell is programmed, abnormal electrical currents are easily generated between the drain and source regions.

10847twf. Ptd Page 7 200421600 V. Description of the invention (3) Sexual penetration (P n c h T h r 〇 u g h), this will seriously affect the electrical performance of this memory cell. In addition, in the step of forming the selection gate of the flash memory, the selection gate has a problem of alignment of the photomask, so that the channel region extending below the selection gate of the substrate cannot be correctly defined. That is, if a misalignment occurs when the gates are patterned, the channel area lengths of the two memory cells sharing the source region will be inconsistent, which will cause the problem of asymmetric programming of the memory cells, resulting in two memory cells. Different characteristics. [Summary of the Invention] In view of this, one object of the present invention is to provide a split gate flash memory cell and a manufacturing method thereof, which can avoid a punch through phenomenon in a source region and a drain region during programming, And improve memory cell performance. Another object of the present invention is to provide a flash memory cell with separated gates and a method for manufacturing the same. The self-aligned process is used to form a selection gate, which can avoid the problem of inconsistent length of the channel area of the two memory cells, and can prevent memory. Cell stylization asymmetry problem and improve memory cell performance. Another object of the present invention is to provide a separate gate flash memory cell and a method for manufacturing the same. The gate is selected to be fabricated on the side wall of the floating gate and extends to the side wall of the trench in the substrate. Therefore, the size of the memory cell can be reduced, and Increasing the accumulation degree of memory elements The present invention provides a split gate flash memory cell. The split gate flash memory cell is composed of a substrate, a stacked structure, a first inter-gate dielectric layer, a first

10847twf.ptd Page 8 200421600 V. Description of the invention (4) The inter-gate dielectric layer, the selection gate, the selection gate dielectric layer, the source region and the drain region are composed. The base has a trench. The stacked structure is disposed on the substrate, and the stacked structure is a tunneling dielectric layer, a floating gate electrode, and a cap layer in order from the substrate. The first inter-gate dielectric layer is disposed on a side wall of the first side of the stacked structure, and the first inter-gate dielectric layer is adjacent to the top of the trench. The second inter-gate dielectric layer is disposed on a sidewall of the second side of the stacked structure. The selection gate is placed on the first side of the stacked structure and the side wall of the trench. The selection gate dielectric layer is disposed between the selection gate and the substrate. The source region is disposed in a substrate on the second side of the stacked structure. The drain region is set at the bottom of the trench on the side of the selection gate. The selection gate of the split gate flash memory cell of the present invention is set on the first side of the stacked structure and the side wall of the trench, so its channel region is set on the trench. The base of the sidewall (vertical channel area), and the channel length is determined by the trench depth. Therefore, even if the component size (gate length) is reduced, the channel length can be accurately controlled by controlling the depth of the trench, which can avoid the problem of the electrical penetration of the source and drain regions during programming, and Can increase component integration. The invention further provides a method for manufacturing a gate flash memory cell. This method provides a substrate having a stacked structure, and the stacked structure is a tunneling dielectric layer, a floating gate electrode, and a cap layer in order from the substrate. . Next, after a source region is formed in the substrate on the first side of the stacked structure, an inter-gate dielectric layer is formed on a sidewall of the stacked structure. Then, a trench is formed in the substrate on the second side of the stacked structure, and a selective gate dielectric layer is formed on the sidewall and the bottom of the trench. On the side wall of the second side of the stacked structure and the trench

10847twf. Ptd Page 9 200421600 V. Description of the invention (5) After the selection gate is formed on the side wall, an electrodeless area is formed at the bottom of the trench on the side of the selection gate. In the manufacturing method of the split gate flash memory cell of the present invention, the selective gate is formed by self-alignment. Since no lithography technology is used, the process margin can be increased, and the process cost and process time can be saved. Moreover, it can avoid the problem of inconsistent channel regions of adjacent memory cells, and can prevent the asymmetry of the programming of the memory cells, thereby improving the reliability of the memory. Moreover, the selection gate is formed on the sidewall of the stacked structure and the trench, so the channel region of the selection gate is provided in the substrate of the sidewall of the trench (vertical channel region). Therefore, even if the component size (gate length) is reduced, by controlling the depth of the trench to accurately control the channel length, the problem of electrical penetration of the source and drain regions during programming can be avoided, and the increase can be increased. Component accumulation. The present invention further provides a method for manufacturing a gate flash memory cell. This method provides a substrate on which a tunneling dielectric layer, a first conductor layer, and a mask layer have been sequentially formed. After the mask layer is patterned to form an opening of the exposed first conductor layer, a cap layer is formed on the exposed first conductor layer. Next, the mask layer is removed, and the top cap layer is used as the mask, and the first conductor layer and the tunnel dielectric layer are etched to form a stacked structure. After a source region is formed in the substrate on the first side of the stacked structure, an inter-gate dielectric layer is formed on a sidewall of the stacked structure. Then, a trench is formed in the substrate on the second side of the stacked structure, a selective gate dielectric layer is formed on the sidewall and the bottom of the trench, and a second conductor layer is formed on the substrate. Next, remove part of the second conductor layer for stacking

10847twf. Ptd Page 10 200421600 V. Description of the invention (6) The side wall of the first side of the structure forms a conductor gap, and the side wall of the second side of the stacked structure and the side wall of the trench form a selection gate. Then, a drain region is formed at the bottom of the trench on the gate side. In the method for manufacturing a gate flash memory cell of the present invention, a portion of the second conductor layer is removed to form a conductor gap wall on a side wall of the first side of the stacked structure, and a side wall and a trench on the second side of the stacked structure. After the step of forming the gate on the sidewall and before the formation of the drain region on the bottom of the trench on the side of selecting the gate, an etching step may be performed to remove the conductor gap. In the manufacturing method of the split gate flash memory cell of the present invention, the selective gate is formed by self-alignment. Since no lithography technology is used, the process margin can be increased, and the process cost and process time can be saved. Moreover, because the problem of inconsistent channel regions between adjacent memory cells can be avoided, the asymmetry of the programming of the memory cells can be prevented, and the reliability of the memory can be improved. Moreover, the selection gate is formed on the sidewall of the stacked structure and the trench, so the channel region of the selection gate is provided in the substrate of the sidewall of the trench (vertical channel region). Therefore, even if the component size (gate length) is reduced, by controlling the depth of the trench to accurately control the channel length, the problem of electrical penetration of the source and drain regions during programming can be avoided, and the increase can be increased. Component accumulation. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below and described in detail with the accompanying drawings as follows: [Embodiment]

10847twf.ptd Page 11 200421600 V. Description of the invention (7) Figure 2 shows a sectional view of the structure of the split gate flash memory cell of the present invention. Please refer to FIG. 2. The flash memory cell of the present invention is composed of a substrate 200, a tunneling dielectric layer 2 0, a floating gate electrode 2 0 4, a cap layer 2 06, and an inter-gate dielectric layer 2 0. 8 a, inter-gate dielectric layer 2 0 8 b, selected gate dielectric layer 2 10, selected gate 2 1 2, source region 2 1 4 and drain region 2 1 16. The substrate 2 0 has a trench 2 1 8. The floating gate electrode 2 0 4 is disposed on the substrate 2 0 0. The tunneling dielectric layer is disposed between the floating gate 204 and the substrate 200, and the material thereof is, for example, silicon oxide. The top cover layer 2 0 6 is disposed on the floating gate electrode 2 0 4, and the material thereof is, for example, oxide stone. The tunneling dielectric layer 20, the floating gate electrode 204, and the cap layer 2 06 form a stacked structure 2 2 2. The inter-gate dielectric layer 208a is disposed on a side wall of one side of the stacked structure 220, and the inter-gate dielectric layer 208a is adjacent to the top of the trench 218. The inter-gate dielectric layer 2 0 8 b is disposed on a side wall of the other side of the stacked structure 2 2 0. The material of the inter-gate dielectric layer 208 a and the inter-gate dielectric layer 208 b is, for example, silicon oxide / nitride stone or stone oxide / nitride stone / silicon oxide. The selected gate electrode 2 1 2 is disposed on the stacked structure 2 2 2. The gate dielectric layer 2 8 a and the sidewall of the trench 2 1 8 are made of, for example, doped polycrystalline silicon. The selection gate dielectric layer 2 1 0 is disposed between the selection gate 2 1 2 and the trench 2 1 8. The source region 2 1 4 is disposed in the inter-gate dielectric layer 2 0 8 b of the stacked structure 2 2 2. The drain region 2 1 Θ is disposed at the bottom of the trench 2 1 8 on the selection gate 2 1 2 side. In the above embodiment of the present invention, the gate electrode 2 12 is selected to be disposed on the cap layer 206, the inter-gate dielectric layer 208a and the sidewall of the trench 218. Therefore, the channel region 220 is disposed on the sidewall of the trench 218. The substrate 200 (vertical channel region), and the length of the channel region 220 is determined by the depth of the trench 218. to

10847twf. Ptd Page 12 200421600 V. Description of the invention (8) Yes, even if the component size (gate length) is reduced, the channel length can be accurately controlled by controlling the depth of the trench 218, which can be avoided during programming. The source and drain regions are electrically connected. In addition, since the gate electrode 2 12 is selected to be disposed on the side wall of the top cap layer 2 06, the inter-gate dielectric layer 2 8 a and the trench 2 18, the size of the memory cell can be reduced, and the component accumulation degree can be increased. . 3A to 3D are cross-sectional views showing a manufacturing process of a split gate flash memory cell according to a preferred embodiment of the present invention, and are used to explain the method of manufacturing the flash memory of the present invention. First, please refer to FIG. 3A, and provide a substrate 300. This substrate 300 is, for example, a silicon substrate. This substrate 300 has formed an element isolation structure (not shown), and the element isolation structure is in a stripe shape. Layout and used to define the active area. The formation method of the element isolation structure is, for example, a region oxidation method (LOC a 1 Oxidation, LOCOS) or a shallow trench isolation method (Shallow Trench Isolation, STI). Next, a tunnel dielectric layer 3 02 is formed on the substrate 300. The material of the tunnel dielectric layer 3 02 is, for example, silicon oxide, and the method of forming the tunnel dielectric layer 3 2 is, for example, a thermal oxidation method ( T herma 1 Oxidation) o Next, a conductor layer 304 is formed on the tunneling dielectric layer 302. The material is, for example, doped polycrystalline silicon. The formation method of the conductor layer 304 is, for example, chemical vapor deposition. After the undoped polycrystalline silicon layer, an ion implantation step is performed to form it. Then, a mask layer 306 is formed on the conductor layer 304. The material of the mask layer 306 is, for example, silicon nitride, and the formation method thereof is, for example, chemical vapor phase.

10847twf. Ptd page 13 200421600 V. Description of the invention (9) Chemical Vapor Deposition (CVD). Next, the mask layer 306 is patterned to form a plurality of openings 308 in the mask layer 306 that expose the conductive layer 304. Next, referring to FIG. 3B, a capping layer 3 1 0 is formed on the conductor layer 3 0 4 exposed by the opening 3 0 8. The material of the capping layer 3 1 0 is, for example, an oxide stone. For example, it is a thermal oxidation method. After the top cover layer 3 10 is formed, the cover layer 3 06 is removed. Then, using the top cap layer 3 10 as a self-alignment mask, the conductive layer 304 and the tunnel dielectric layer are etched until the substrate 300 is exposed to form a conductive layer 304a and a through dielectric f302a. The capping layer 310, the conductive layer 304a, and the tunneling dielectric layer 302a constitute a stacked structure 31 2, and the conductive layer 304 a serves as a floating gate of a memory cell. Next, referring to FIG. 3C, a pattern of apricot layer 3 1 4 is formed on the substrate 300. After the patterned photoresist layer 3 1 4 is exposed to a region X i that is intended to form a source, an ion implantation is performed. In the step, a source region 3 16 is formed in the substrate 300 on the 3 1 2 side of the stacked structure. In addition, please refer to FIG. 3D and the diagram, and remove the patterned photoresist layer 31 1 and the sidewalls of the structure 3 1 2 to form a gate dielectric layer 3 丨 8a and a gate; 1 =. The inter-gate dielectric layer 3183 and the inter-gate dielectric layer 31 are made of ^ silicon / silicon nitride, etc. The inter-gate dielectric layer 3 1 8a and the inter-gate dielectric chip 3 are used. Oxidation method to form a layer of silicon oxide; ", i of the & compressive chemical vapor deposition method to form a silicon nitride layer,-a favorable etching step, remove part of the silicon oxide layer and the silicon nitride layer ^: etc Please refer to FIG. 3E to form another layer pattern on the substrate 300.

Page 14 200421600 V. Description of the invention (ίο) The photoresist layer 3 2 0, the patterned photoresist layer 3 2 0 covers the source region 3 丨 6. Then, the patterned photoresist layer 3 2 0 and the stack structure 3 1 2 with the inter-gate dielectric layers 3 丨 8 a, 3 丨 8 b are used as a mask, and the step of engraving is performed, and the stacked structure 3 1 2 A gate dielectric layer 3 1 8 a is formed on the side of the substrate 3 0 0 to form a trench 3 2 2. /. Next, referring to FIG. 3F, after removing the patterned photoresist layer 320, a dielectric layer 324 is formed on the sidewall and the bottom of the trench 322. The material of the dielectric layer 324 is, for example, silicon oxide, and a method of forming the dielectric layer 324 is, for example, thermal oxidation. Of course, a dielectric layer 326 will also be formed above the source region 316, and the surface of the inter-gate dielectric layers 318a, 3i8b will also form a thin silicon oxide layer, so that the inter-gate dielectric layer 3a, 8a, 3 丨 8 b to form a silicon oxide / silicon nitride / silicon oxide structure. Then, a conductive layer 3 2 8 is formed on the sidewall of the gate dielectric layer 3 丨 8a on the side of the stacked structure 3 1 2 and the trench 3 2 2. This conductor layer 3 2 8 serves as the gate of choice for separating the gate flash memory cells. The step of forming the conductive layer 3 2 8 is, for example, forming a conductive material layer (not shown) on the substrate 300. Afterwards, an anisotropic etching process is performed to remove a portion of the conductive material layer so that a gate dielectric layer 3 丨 8a on the side of the stacked structure 3 1 2 and a side wall of the trench 3 2 2 form a conductor layer. 3 2 8. In this step, a conductor gap 3 3 0 is also formed on the side wall of the inter-gate dielectric layer 3 1 8 b formed on the stacked structure 3 1 2. The material of the conductor layer 3 2 8 and the conductor spacer 3 3 0 is, for example, doped polycrystalline silicon, which is formed, for example, by using chemical vapor deposition to form an undoped polycrystalline silicon layer, and then performing an ion implantation step to form the layer. . Next ’Please refer to FIG. 3G to form a layer of patterned light on the substrate

10847twf. Ptd page 15 200421600 V. Description of the invention (11) A resist layer 332. This patterned photoresist layer 332 exposes a region above the source region 316. Then, an etching step is performed to remove the conductive spacer 3 3 0. The method for removing the conductive spacer 3 3 0 is, for example, a wet etching method or a dry etching method. In this embodiment, the conductive spacers 3 3 0 of two adjacent memory cells are electrically connected to each other, and it is easy to cause the adjacent two memory cells to interfere with each other during operation. Therefore, it is necessary to move the conductive spacers 3 3 0 except. Of course, if the conductive spacers 3 3 0 of two adjacent memory cells are separated from each other without being electrically connected, the step of removing the conductive spacers 3 3 0 can be omitted. Next, referring to the third figure, after removing the patterned photoresist layer 3 3 2, another patterned photoresist layer (not shown) is formed on the substrate 300, and the patterned photoresist layer is exposed to form a drain electrode. Area. Then, an ion implantation step is performed, and a drain region 3 3 4 is formed at the bottom of the trench 3 2 2 on the side of the conductive layer 3 2 8. Then, the patterned photoresist layer is removed. The subsequent completion of the process of separating the gate flash memory is well known to those skilled in the art, and will not be repeated here. In the above embodiment, the selection gate (conductor layer 3 2 8) is formed on the side wall of the stacked structure 3 1 2 and the trench 3 2 2. Therefore, the channel region of the selection gate (conductor layer 328) is provided in the trench 322. In the substrate 300 of the sidewall (vertical channel region). Therefore, even if the component size (gate length) is reduced, the channel length can be accurately controlled by controlling the depth of the trench 322, thereby avoiding the problem of electrical penetration of the source and drain regions during programming. In addition, since the selection gate (conductor layer 3 2 8) is formed on the side wall of the stacked structure 3 12 and the trench 3 2 2, the size of the memory cell can be reduced, and the degree of component accumulation can be increased.

10847twf. Ptd Page 16 200421600 V. Description of the invention (12) In addition, the present invention uses a self-aligning method to form the selection gate (conductor layer 3 2 8). Since no lithography technology is used, the process margin can be increased Degrees, and can save process costs and process time. In addition, the present invention uses a self-aligning method to form a selection gate (conductor layer 3 2 8), so that the channel regions of adjacent memory cells have the same length. Therefore, when operating this flash memory, The channel regions of the two memory cells in the source region have the same length, so the problem of asymmetric programming of the memory cells can be avoided, and the reliability of the memory can be improved. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some changes and retouch without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application.

10847twf. Ptd Page 17 200421600 Brief Description of Drawings Figure 1 is a sectional view showing the structure of a conventional flash memory cell with separated gates. Fig. 2 is a sectional view showing a structure of a split gate flash memory cell according to the present invention. Figures 3A ~ 3 are cross-sectional views showing the manufacturing process of the split gate flash memory cell of the present invention. [Illustration of diagrammatic symbols] 1 00 > 200 > 300: substrate 102 > 202, 302, 3 0 2a: tunneling dielectric layer 104, 204: floating gate 106, 2 0a, 208b, 31 8a, 31 8b • Inter-gate dielectric layer 108 ^ 212: Select gate 110 ^ 210, 324: Select gate dielectric layer 112, 214 > 316: Source region 114 > 216, 334: Drain region 206 ^ 310: top cover layer 218 \ 322 = trench 220: channel area 304, 3 0 4a > 328: conductor layer 306: cover layer 308: opening 312: stacked structure 314 \ 320 ~ 332: patterned photoresist layer 326 : Dielectric layer

10847twf. Ptd Page 18 200421600 Simple illustration of the drawing 3 3 0: Conductor gap ΙΗϋΙΙ Page 19 10847twf. Ptd

Claims (1)

200421600 6. Application patent scope 1. A split gate flash memory cell, comprising: a substrate, the substrate having a trench; a stacked structure disposed on the substrate, the stacked structure sequentially passing through from the substrate A tunnel dielectric layer, a floating gate electrode, and a cap layer; a first inter-gate dielectric layer disposed on a side wall of a first side of the stacked structure, and the first inter-gate dielectric layer and the trench The top of the stack is adjacent; a second inter-gate dielectric layer is disposed on a side wall of a second side of the stacked structure; a selection gate is disposed on the first side of the stacked structure and a side wall of the trench; a selection A gate dielectric layer is disposed between the selection gate and the substrate; a source region is disposed in the substrate on the second side of the stacked structure; and a drain region is disposed on the selection gate The bottom of the ditch on one side. 2. The split gate flash memory cell according to item 1 of the scope of the patent application, wherein the material of the first gate dielectric layer and the second gate dielectric layer includes silicon oxide / silicon nitride. 3. The split gate flash memory cell as described in item 1 of the scope of patent application, wherein the material of the first gate dielectric layer and the second gate dielectric layer includes silicon oxide / silicon nitride / silicon oxide . 4. The split gate flash memory cell described in item 1 of the scope of patent application, wherein the material of the tunneling dielectric layer includes silicon oxide. 5. Split gate flash memory as described in item 1 of the scope of patent application 10847twf.ptd Page 20 200421600 6. Scope of patent application, in which the material of the floating gate includes doped polycrystalline silicon. 6. The split gate flash memory cell described in item 1 of the scope of patent application, wherein the material of the selected gate includes doped polycrystalline silicon. 7. A method for manufacturing a gate flash memory cell, comprising: providing a substrate; forming a stacked structure on the substrate; the stacked structure is sequentially a tunneling dielectric layer and a floating gate from the substrate; A source layer and a cap layer; a source region is formed in the substrate on a first side of the stacked structure; a gate dielectric layer is formed on a side wall of the stacked structure; A trench is formed in the substrate; a selective gate dielectric layer is formed on a sidewall and a bottom of the trench; a selective gate is formed on a sidewall of the second side of the stacked structure and a sidewall of the trench; and a selective gate A drain region is formed at the bottom of the trench on the pole side. 8. The method of manufacturing a split gate flash memory cell as described in item 7 of the scope of the patent application, wherein the step of forming the selection gate on a side wall of the second side of the stacked structure and a side wall of the trench includes: Forming a second conductor layer on the substrate; and removing a portion of the second conductor layer to form a conductor gap wall on a side wall of the first side of the stacked structure and a side wall on the second side of the stacked structure, A sidewall of the trench forms the selection gate. 9. The method of manufacturing a gate flash memory cell as described in item 8 of the scope of patent application, wherein the method of removing a portion of the second conductor layer includes a non- 10847twf. Ptd Page 21 200421600 6. Scope of patent application Isotropic etching method. 10. The method for manufacturing a separate gate flash memory cell as described in item 8 of the scope of the patent application, wherein the step of forming the gate selection after the step of forming the gate by the side wall of the second side and the side wall of the trench of the stacked structure Remove the conductive spacer 〇11. The method for manufacturing a gate flash memory cell as described in item 7 of the scope of patent application, wherein the step of forming the inter-gate dielectric layer on the side wall of the stacked structure includes: A '* silicon oxide layer is formed on the side wall of the floating gate; and a silicon nitride layer 0 12 is formed on the silicon oxide layer. A method for manufacturing a separate gate flash memory cell as described in item 7 of the scope of patent application Among them, the method of forming the gate dielectric layer on the sidewall and bottom of the trench includes a thermal oxidation method. A method for manufacturing a gate flash memory cell includes: A substrate is provided; a tunneling dielectric layer, a first conductor layer, and a mask layer are sequentially formed on the substrate; the mask layer is patterned to form an exposed portion of one of the first conductor layers. The exposed _ first conductor layer is formed on the _ cap layer 9. The cap layer is removed, and the cap layer is used as a cap. The first conductor layer and the tunnel dielectric layer are etched to form a stacked structure. f forming a source in the substrate on the second side of the stacked structure 10847twf. Ptd page 22 200421600 6. In the patent application area, an inter-gate dielectric layer is formed on the side wall of the stacked structure; a trench is formed in the substrate on the second side of the stacked structure; on the side wall of the trench Forming a selective gate dielectric layer with the bottom; forming a second conductor layer on the substrate; removing a portion of the second conductor layer to form a conductor gap wall on the side wall of the first side of the stacked structure and the A sidewall of the second side of the stacked structure and a sidewall of the trench form a selection gate; and a drain region is formed at the bottom of the trench on the side of the selection gate. 1 4. The method for manufacturing a gate flash memory cell as described in item 13 of the scope of the patent application, wherein the method for removing part of the second conductor layer includes anisotropic etching. 15. The method for manufacturing a split gate flash memory cell as described in item 13 of the scope of patent application, wherein a portion of the second conductor layer is removed to form the conductor gap on a side wall of the first side of the stacked structure. The wall and the side wall on the second side of the stacked structure and the side wall of the trench after the step of forming the selection gate and before forming the drain region at the bottom of the trench on the side of the selection gate further include removing the conductor Gap wall. 16. The method for manufacturing a separate gate flash memory cell as described in item 13 of the scope of the patent application, wherein the step of forming the inter-gate dielectric layer on the side wall of the stacked structure includes: A silicon oxide layer is formed on the sidewall; and a silicon nitride layer is formed on the silicon oxide layer. 1 7. Separate gate flash memory as described in item 13 of the scope of patent application 10847twf.ptd p. 23 200421600 10847twf. Ptd Page 24