TW200419706A - Wafer bumping process - Google Patents
Wafer bumping process Download PDFInfo
- Publication number
- TW200419706A TW200419706A TW092106130A TW92106130A TW200419706A TW 200419706 A TW200419706 A TW 200419706A TW 092106130 A TW092106130 A TW 092106130A TW 92106130 A TW92106130 A TW 92106130A TW 200419706 A TW200419706 A TW 200419706A
- Authority
- TW
- Taiwan
- Prior art keywords
- metal layer
- bottom metal
- ball
- patent application
- layer
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 41
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- 244000269722 Thea sinensis Species 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
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- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
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- 229910052710 silicon Inorganic materials 0.000 description 1
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- 238000003466 welding Methods 0.000 description 1
Classifications
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Description
200419706 五、發明說明(l) [發明所屬之技術領域] 本發明疋有關於種晶圓凸塊(solder bumping)製 程,且特別是有關於一種利用薄光阻層成長高凸塊的製 程0 [先前技術] 所謂的晶圓凸塊製程,常見於覆晶技術(f丨丨p ch丨p) 中’其主要是在形成有多個晶片的晶圓上對外的接點(通 常是金屬焊墊)上長出球底金屬層(UBM,UnderBump Metallurgy),並於球底金屬層之上成長凸塊,最後,晶 片便透過凸塊與基板(substrate)連接。由於(矽)晶片與 基板的熱膨脹係數不同,當基板與晶片之間隙太小時,凸 塊會承受較大的剪應力,便會降低其機械可靠度。 針對上述問題點’可設法形成較高的凸塊,以增大 基板與晶片之間隙,使凸塊承受的剪應力降低,並改善其 機械可靠度。 "八 關於習知技術形成高凸塊的方法,請依序參考第^〜2 圖0 其中標號1 0 0代表晶圓,1 〇 2代表焊 請參考第1圖 墊。保護層104係覆蓋於晶圓100之表面並暴露出焊墊 102。標號1〇6代表球底金屬層(UBM),全面性地覆蓋保護 層104及焊墊102。在球底金屬層1Q6上先後形成圖案化光 阻層1 08、11 0。藉由增加總光阻層厚度,以增加焊料容 ^。並利用電鑛方法,將錫鉛焊料112充填於圖案化光阻 層108、110的開口中,以形成一較厚的焊料層。其中開口
開口中。形成一第二圖案化光
200419706 五、發明說明(2) 1 08的大小約為1 20 mi 1,且各圖案化光阻層〗08、;[丨〇之厚 度約為1 0 0 m i 1。 接著,請參考第2圖,先後剝除圖案化光阻丨1()、108 以及部份的球底金屬層1 〇 6,再進行一回焊步驟,以使焊 料層形成球體凸塊1 1 2 a。 在上述習知的凸塊製程中,因各圖案化光阻層之開 口小’故藉由多層較厚的光阻層堆積的方式,以達所需的 焊料充填區域之容積。但是,其缺點為製程難度高,因為 在曝光微影製程中,欲形成小而深的開孔具有相當的難 度’是以其良率及可靠度降低。 [發明内容] 一曰為解決習知的問題點,本發明的目的之一係,提出 二種晶圓凸塊製程,可以較習知為薄的光阻層配合較習知 為大的開孔,成長高凸塊。 來p本明的目的之—係’提出一種晶圓凸塊製程,可 ϊίίί二以增大基板與晶片之間隙,使凸塊承受的剪 應力降低,並改善其機械可靠度。 為達成上述及,. 製程,包括提供一晶圓他目具提出一種晶圓凸塊 晶圓表面並暴露出焊熱。二、夕固知塾及一保濩層覆蓋於 層並覆於暴露出之焊墊。° ^成一第一球底金屬層覆於保護 球底金屬層,此第一圖案$成一第一圖案化光阻層於第一 別對應於此些焊塾,並^露光,層具有多個第一開口,分 成一第二球底金屬層於^一出。卩份之第一球底金屬層。形
200419706 五、發明說明(3) 阻層,覆於第一圖案化光阻層,此第二圖案化光阻异旦有 多個第二開口 ,且第二開口之大小係大於第一開口之大 小,以暴露出第二球底金屬層。將一焊料填充於第二開 口,並覆於暴露出之第二球底金屬層。進行一回p牛二, 使焊料形成多個球體凸塊。 + 乂。 ’ 在本發明中,並不限定第二開口的形狀,其 形、方形、彡角形# ’只要其大小足以暴露出球底金屬層 (第二球底金屬層)即可。舉例而言,第二開 可呈; 狀以暴露出球底金屬層(第二球底金屬層)。 #月 依照本發明的特徵’第二開口的二小係大於第一開 二社其目的在於’使填充焊料的開口面積(第二開口)大於
:開口卜依此特徵,在回焊步驟時,焊料 口積』J 較小的球底金屬層(第二球底金屬層汗、 於是焊同料理便Λ朝中 調整第二開口的大V,特二而可:需填入的焊料量適當地 :得較薄而把第二開口做得較::阻Γ; 填入所需的焊料量。此較簿 奋積里 在製程中尚且有容易施你r〇a ^較大的圖案化光阻層, 優點。’、 "•作(曝光顯影較易)’且良率較高的 同理如上,本發明i 習知技術中"光阻層辦厚/择展光阻層施作高凸塊,一反 想,為具有高度創作性之;f月?施作高凸塊”的技術思
200419706 五、發明說明(4) 為讓本發明之上述和其他目的、特徵、和優點能更 詳細說明如下·· 佳““列,並配合所附圖式,作 [實施方式] [弟一實施例] 請依序參考第3〜10圖,其繪示依照本發明之 施例的晶圓凸塊製程流程剖視圖。 清茶考第3目,提供一晶圓2〇〇,具有多個焊塾及 -保護層204覆蓋於晶圓_之表面並暴露出焊墊2〇2。全 一球底金屬層2〇6覆於保護層204並覆於暴露出 之烊墊204,以作為後續電鍍製程(詳如第5圖之說明)的種 ^層。在此,形成第一球底金屬層2〇6的方法,舉例而 吕,包括濺鍍等。且第一球底金屬層2〇6係選自於由鉻、 鈦、鈦鎢合金、銅、鎳、鉻銅合金、鎳釩合金、鎳金合 金、鋁及該等之組合所組成之組群中的一種材質。 請參考第4圖,形成一第一圖案化光阻層2〇8於第一 球底金屬層206。第一圖案化光阻層208具有多個第一開口 208a,分別對應於焊墊202,並暴露出部份之第一球底#金 屬層206。其中第一圖案化光阻層208之厚度約為3〇〜75 mil,而第一開口 208a之大小(關鍵尺寸Critical
Dimension , CD)約為160〜250mil 。 請參考第5圖,以上述第一球底金屬層206為種子 層,電鑛形成一第二球底金屬層210於第一開口 2〇8a中。 其中第二球底金屬層210係選自於由鉻、鈦、鈦鎢合金、 l〇789twf.ptd 第10頁 五、發明說明(5) 銅、鎳、鉻銅合金、鎳叙合 合所組成之組群中的—種材錄金合金、銘及該等之組 請參考第6圖,形 約為30〜M mil,覆於第网第安一圖案化光阻層212,厚度 光阻層212具有多個第— 曰208。第一圖案化 叫币_開口212a ,且第一 小係大於第一開口 2〇8 弟一開口 21 2a之大 21〇。 大小,以暴露出第二球底金屬層 請參考第7圖,將一焊料 並覆於暴露出之第二破麻二厘 、《苐一開口 212a, A锡鉼人厶一—表底至屬層21〇。此焊料214之材質可 法,兴你W : 或是金等,且填充焊料214的方 法舉j列而',包括電鍍及印刷填入等。 加+,触月 > 考第8圖,進行一回焊步驟’使焊料214形成多 個球體凸塊214a。ώ协笙-日日01 Λ 夕 y 由於第一開口212a的大小係大於第一開 a,使得填充焊料214的開口面積(第二開口21 2)大於 、θ = 1 4下方的球底金屬層(第二球底金屬層21 〇)的開口面 積 開口 Μ 8a)。因此’在回焊步驟時,焊料會以開口 面積較小的球底金屬層(第二球底金屬層21〇)為基座,往 j攀附。於是焊料214便會朝中央集中,而高突於第二圖 案化光阻層212(球體凸塊214a的高度h2大於第二圖案化光 阻層21 2的厚度hi)。 卜 接著’請參考第9圖,移除第二圖案化光阻層212及 第一圖案化光阻層208,以暴露出部份之第一球底金屬層 2〇6 °之後,如第丨〇圖,移除暴露出之部份的第一球底金 屬層206。 10789twf.ptd 第11頁 200419706 五 發明說明(6) [第二實施例] 充填Λ上述第一實施例的製程中,若淳料是以電錢方文 真t活’則上述流程還可以稍作變化。亦即式 第—及第一圖案化光阻層,之後再進行回 ^移除 說明過的流程,在此便省略之。 卓…例中已 在第3〜7圖的製程流程之後,亦即,在雷供枯+ 214之後,移除第二圖案化光阻層212及第ί =充焊料 2+〇8 ’以暴露出部份之第一球底金屬層206随層 路出之部份的第一球底金屬層20 6,以成為 多除暴 構。在第11圖中和第-實施例中相同的元件 ,的门结 標號,在此亦省略其說明。 -件“吏用相同的 成找科接參照第1G圖’進行一回焊步驟’使焊料2Η形 成球體凸塊214a。 、上述移除暴露出之部份的第一球底金屬層206的動作 也可以移至在形成球體凸塊2 14a之後再進行。 依照本發明的特徵,並不限定第二開口的形狀,其 可為圓形、方形、多角形等,只要其大小足以暴露出球底 金屬層(第二球底金屬層)即可。舉例而言,如第12圖所 示第一圖案化光阻層312的第二開口 312a係可呈斜角 狀’ _而呈朝第一開口 2〇8a漸縮的方式以暴露出球底金屬層 第二球底金屬層2 1 0 )。在第1 2圖申與第一實施例相同的 元件係採用相同的符號,在此便省略其說明。 依照本發明的特徵,第二開口的大小係大於第一開
200419706 五、發明說明(7) 口,其目的在於,使填充焊料的開口面積(第二開口)大於 焊料下方的球底金屬層(第二球底金屬層)的開口面積(第 一開口)。依此特徵,在回焊步驟時,焊料會以開口面積 較小的球底金屬層(第二球底金屬層)為基座a,往上攀附。 於是焊料便會朝中央集中,而高突於第二圖案化光阻層。 ^ 〃同理如上,依此特徵,可依需填入的焊料量適當地 2 ί 了開口的大小,舉例而言,可把第二圖案化光阻層 而把第二開口做得較大,以調整開口容積量,以 在·鞀:的焊料量。此較薄而開口較大的圖案化光阻層’ 在I权中尚具有容易施作的優點。 反習同Λ如上,本發明可以"薄"光阻層施作”高"凸塊, 思想 想,為度光:作層Λ厚發:層以施作高凸 受的 /^ 雖然本發明已以& ^ 以限定本發明,任何孰=Λ施例揭露如上,然其並非用 神和範圍内,當可作:11技藝者,在不脫離本發明之精 護範圍當視後附:::=更動與潤*,因此本發明之伴 :d月專利範圍所界定者為準。…呆 l〇789twf.ptd 第13頁 200419706 圖式簡單說明 第1〜2圖繪示習知的晶圓凸塊製程流程剖視圖; 第3圖〜第1 0圖繪示依照本發明之第一實施例的晶圓 凸塊製程流程剖視圖; 第1 1圖繪示當利用電鍍充填焊料之後的製程變化之 例示;以及 第1 2圖繪示依照本發明之較佳實施例的光阻開口之 變化例。 [圖式標示說明]
100 、2 0 0 : 晶 圓 102 、202 : 焊 墊 104 、204 : 保 護層 106 :球底金屬 層 108 、1 10 : 圖 案化 光 阻層 206 、210 : 第 、 第 二球 底 金 屬 層 208 ^ 212 : 第 、 第 二圖 案 化 光 阻層 208a 、212a I 第一 第二 開 Π 214 :焊料 214a :球體凸 塊 312 • 笛 一 圖案化光阻層 312a • 篦- • >P 一 二開 D
10789twf.ptd 第14頁
Claims (1)
- 2004197061. 一種晶圓凸塊製程,包括· 覆盖於該 提供一晶圓,具有複數個焊墊及一保護層 晶圓表面並暴露出該些焊墊; 形成一第 之該些焊墊; 球底金屬層覆於該保護層並覆於暴露出 ^ 形成一第一圖案化光阻層於該第一球底金屬層,該 第-圖案化光阻層具有複數個第一開口,分別對應於該些 焊墊,並暴露出部份之該第一球底金屬層; — 形成一第一球底金屬層於該些第一開口中; 形^成一第二圖案化光阻層,覆於該第一圖案化光阻 層’该第二圖案化光阻層具有複數個第二開口,該些第二 開口之大小係大於該些第一開口之大小,以暴露出該第二 球底金屬層; 將一焊料填充於該些第二開口,並覆於暴露出之該 第二球底金屬層; 進行一回焊步驟,使該焊料形成複數個球體凸塊; 移除該第二圖案化光阻層及該第一圖案化光阻層, 以暴藤出部份之該第一球底金屬層;以及 移除暴露出之部份的該第一球底金屬層。 2 ·如申請專利範圍第1項所述之晶圓凸塊製程,其中 填充该焊料的方法包括印刷填入。 3·如申請專利範圍第1項所述之晶圓凸塊製程,其中 填充该焊料的方法包括電鑛^。 4 ·如申請專利範圍第3項所述之晶圓凸塊製程’其中10789twf.ptd 第15頁 200419706 六、申請專利範圍 該回焊步驟係在移除該第二圖案化光阻層、該第一圖案化 光阻層及該第一球底金屬層之後進行。 5. 如申請專利範圍第3項所述之晶圓凸塊製程,其中 該回焊步驟係在移除該第二圖案化光阻層、該第一圖案化 光阻層之後,且在移除該第一球底金屬層之前進行。 6. 如申請專利範圍第1項所述之晶圓凸塊製程,其中 該些第二開口係呈斜角狀以暴露出該第二球底金屬層。 7. 如申請專利範圍第6項所述之晶圓凸塊製程,其中 該些第二開口係呈朝該些第一開口漸縮的方式以暴露出該 第二球底金屬層。 8. 如申請專利範圍第1項所述之晶圓凸塊製程,其中 形成該第一球底金屬層的方法包括濺鍍。 9. 如申請專利範圍第1項所述之晶圓凸塊製程,其中 形成該第二球底金屬層的方法包括電鍍。 1 0.如申請專利範圍第1項所述之晶圓凸塊製程,其 中該第一球底金屬層係選自於由鉻、鈦、鈦鎢合金、銅、 鎳、鉻銅合金、鎳飢合金、鎳金合金、銘及該等之組合所 組成之組群中的一種材質。 11.如申請專利範圍第1項所述之晶圓凸塊製程,其 中該第二球底金屬層係選自於由鉻、鈦、鈦鎢合金、銅、 鎳、鉻銅合金、鎳釩合金、鎳金合金、鋁及該等之組合所 組成之組群中的一種材質。 1 2.如申請專利範圍第1項所述之晶圓凸塊製程,其 中該焊料包括錫鉛合金。10789twf.ptd 第16頁 200419706 六、申請專利範圍 1 3.如申請專利範圍第1項所述之晶圓凸塊製程,其 中該焊料包括金。 1 4.如申請專利範圍第1項所述之晶圓凸塊製程,其 中該焊料包高含鉛材料。10789twf.ptd 第17頁
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TW092106130A TW584936B (en) | 2003-03-20 | 2003-03-20 | Wafer bumping process |
US10/708,707 US6921716B2 (en) | 2003-03-20 | 2004-03-19 | Wafer bumping process |
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TW092106130A TW584936B (en) | 2003-03-20 | 2003-03-20 | Wafer bumping process |
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TW200419706A true TW200419706A (en) | 2004-10-01 |
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JP4758614B2 (ja) * | 2003-04-07 | 2011-08-31 | ローム・アンド・ハース・エレクトロニック・マテリアルズ,エル.エル.シー. | 電気めっき組成物および方法 |
US20060076677A1 (en) * | 2004-10-12 | 2006-04-13 | International Business Machines Corporation | Resist sidewall spacer for C4 BLM undercut control |
TWI240979B (en) * | 2004-10-28 | 2005-10-01 | Advanced Semiconductor Eng | Bumping process |
US7459386B2 (en) * | 2004-11-16 | 2008-12-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming solder bumps of increased height |
US7241678B2 (en) * | 2005-01-06 | 2007-07-10 | United Microelectronics Corp. | Integrated die bumping process |
KR20080037681A (ko) * | 2005-08-23 | 2008-04-30 | 로무 가부시키가이샤 | 반도체 칩 및 그 제조 방법 및 반도체 장치 |
CN100413030C (zh) * | 2005-09-07 | 2008-08-20 | 日月光半导体制造股份有限公司 | 凸块制造方法及其结构 |
KR100695518B1 (ko) * | 2005-11-08 | 2007-03-14 | 삼성전자주식회사 | 범프의 형성 방법, 이를 이용한 이미지 센서의 제조 방법및 이에 의해 형성된 반도체 칩 및 이미지 센서 |
US7323780B2 (en) * | 2005-11-10 | 2008-01-29 | International Business Machines Corporation | Electrical interconnection structure formation |
TWI270155B (en) * | 2005-12-14 | 2007-01-01 | Advanced Semiconductor Eng | Method for mounting bumps on the under metallurgy layer |
US7858438B2 (en) * | 2007-06-13 | 2010-12-28 | Himax Technologies Limited | Semiconductor device, chip package and method of fabricating the same |
US20090008764A1 (en) * | 2007-07-02 | 2009-01-08 | Hsin-Hui Lee | Ultra-Thin Wafer-Level Contact Grid Array |
DE102008020924A1 (de) * | 2008-04-25 | 2009-11-05 | Siemens Aktiengesellschaft | Modul mit Niedertemperatur-Lötverbindung und dazugehöriges Verfahren zur Herstellung |
US20100151118A1 (en) * | 2008-12-17 | 2010-06-17 | Eastman Chemical Company | Carrier solvent compositions, coatings compositions, and methods to produce thick polymer coatings |
WO2011002778A2 (en) * | 2009-07-02 | 2011-01-06 | Flipchip International, Llc | Methods and structures for a vertical pillar interconnect |
US9627254B2 (en) | 2009-07-02 | 2017-04-18 | Flipchip International, Llc | Method for building vertical pillar interconnect |
US8445375B2 (en) * | 2009-09-29 | 2013-05-21 | Semiconductor Components Industries, Llc | Method for manufacturing a semiconductor component |
US8759209B2 (en) * | 2010-03-25 | 2014-06-24 | Stats Chippac, Ltd. | Semiconductor device and method of forming a dual UBM structure for lead free bump connections |
US8492892B2 (en) | 2010-12-08 | 2013-07-23 | International Business Machines Corporation | Solder bump connections |
US8431478B2 (en) * | 2011-09-16 | 2013-04-30 | Chipmos Technologies, Inc. | Solder cap bump in semiconductor package and method of manufacturing the same |
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US6372622B1 (en) * | 1999-10-26 | 2002-04-16 | Motorola, Inc. | Fine pitch bumping with improved device standoff and bump volume |
TWI245402B (en) * | 2002-01-07 | 2005-12-11 | Megic Corp | Rod soldering structure and manufacturing process thereof |
US6750133B2 (en) * | 2002-10-24 | 2004-06-15 | Intel Corporation | Selective ball-limiting metallurgy etching processes for fabrication of electroplated tin bumps |
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US20040185649A1 (en) | 2004-09-23 |
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