200419450 發明說明(1 【發明所屬之技術領域】 本發明是有關於一種基本輸入輸出系統之更新方法， 特別是指一種電子裝置中嵌入式控制器之基本輸入輸出系 統之更新方法。 5 【先前技術】 今曰為了增加電子裝置的功能與效能，除了利用提升 既有電子裝置的處理單元（例如微處理器、晶片組）的功能 外’亦可利用增置一後入式控制器（Embedded Controlled ，EC)，或稱鍵盤控制器（Keyboard Controlled，KBC)來負 10 責新功能。舉例來說，如第一圖，一般筆記型電腦架構包 含一處理單元11與一嵌入式控制器12。處理單元U是 指微處理器與南北橋晶片並用來控制筆記型電腦中主要設 備，例如控制硬碟111、光碟機112、通用序列匯流排 (Universal Serial Bus，USB)113、顯示器等等。嵌入式控 15 制系統12負責控制筆記型電腦中的一些周邊設備與功能 ，例如控制内建滑鼠（internal pointing device) 12l·、内建鍵 盤（internal keyboard) 122、電池（Battery) 123、供外部鍵盤 (External Keyboard)或外部滑鼠（External pointing device) 用的連接埠124。另外，處理單元11之基本輸入輸出系 20 統（Basic Input/Output System，BIOS)係儲存於第一記憶體 114中，由於嵌入式控制器12類似處理單元11為一獨立 系統，所以嵌入式控制器12亦具有一儲存於第二記憶體 12 5中基本輸入輸出系統。 隨著技術進步或軟體中錯誤（Bug)被發現等因素，基 200419450 . ~ '.......， - ' 义、 -；V. - ； > ^ 掛、發日日§e日日d、 本輸入輸出系λ统難免需更新（Update)作業，所以載有基本 輸入輸出系統之記憶體114、125大都會採用可抹除程式 化唯讀記憶體（Erasable Programmable Read-Only Memory，EPROM)，例如電子式可抹除程式化唯讀記憶體 5 (Electrically Erasable Programmable Read-Only Memory，EEPROM)、快閃記憶體（Flash Memory)，而以快 閃記憶體為主流。目前更新嵌入式控制器12之基本輸入 輸出系統的方法大致可分為下列三種。 第一種方式是直接將第二記憶體125拔下來用燒錄機 10 (Programmer)重新燒錄。因而，消費者無法自行更新基本 輸入輸出系統，需將整台電子裝置送回擁有燒錄機之廠商 處維修。如此，不僅對消費者造成不便，對廠商來說，拔 取已組裝於電子裝置中的記憶體來重新燒錄且燒錄完尚需 組裝回電子裝置中，不僅費時、費力且不符成本。 15 第二種方式是一種利用軟體方式來執行更新嵌入式控 制器12之基本輸入輸出系統。配合第二圖，此軟體是一 設置電腦中的更新程式（Flash utility)，而故入式控制器12 中需有一隨機存取記憶體（RAM)126。如步驟131，當處理 單元11執行更新程式時，則處理單元11會通知嵌入式控 20 制器125。其次，如步驟125，嵌入式控制器12會將原本 儲存於第二記憶體125基本輸入輸出系統複製至到隨機存 取記憶體126中，以使嵌入式控制器12需要時可直接讀 取暫存於隨機存取記憶體126中的程式來執行工作，而無 总 需自第二記憶體125讀取程式。此時，如步驟133，處理 7 200419450 <?:：ϊ ；…ΓΓ ' 單元11就可以更新第二記憶體125中的基本輸入輸出系 統程式。如此，利用更新程式即可完成更新於第二記憶體 125中的基本輸入輸出系統並可解決第一種更新方式的不 便。但是，此更新方式需要佔用額外的隨機存取記憶體 5 126的空間來執行程式，且更新完第二記憶體125中的基 本輸入輸出系統後，嵌入式控制器12需等到下次重新開 (reset)後始能執行更新後的基本輸入輸出系統。 第三種方式亦是利用一種更新程式來更新嵌入式控制 器之基本輸入輸出系統的方法。此種方法係先將第二記憶 10 體125’區隔成兩區塊（Bank)127、128，兩區塊127、128 皆儲存一份基本輸入輸出系統，嵌入式控制器12執行時 需要基本輸入輸出系統中的程式時是自區塊127中讀取。 而後，當處理單元11執行更新程式時，如步驟141，處 理單元11會更新另一區塊128中的基本輸入輸出系統。 15 如此，與第二種更新方式相同，當處理單元11更新區塊 128中的基本輸入輸出系統時，嵌入式控制器12仍可讀 取區塊127内基本輸入輸出系統來執行。然而，同樣的基 本輸入輸出系統更新後，並無法馬上執行更新過後的基本 輸入輸出系統，仍需重新開機以執行步驟142來將於區塊 20 128中的已更新的基本輸入輸出系統更新至另一區塊127 中，始能執行新的基本輸入輸出系統。因而，此種方式存 在著需加倍的記憶體空間與重新開機始能執行新的基本輸 入輸出系統的缺憾。 ， 所以，第二、三種軟體更新方式可讓消費者自行更新 8 200419450 -、ί :、、、、、、 -s 、 、 < - s 、 、 - . -； ^ 、” ..........- --- 、、、 、f、、/ '〆、' 、 - ' 琰、潑明說明) |：：ii|：|jPi^i^；iN；：：IINiii：|i：i|v^!i!；iliii：iii^!i|ili^：^ll：l ‘ 基本輸入輸出系統，以可解決第一種方式對於消費者與廠 商造成的不便。然而，第二種與第三種軟體更新方式都需 應用到額外的記憶體空間（如第二種方式中的隨機存取記 憶體126與第三種方式中的區塊128)，致使成本增加， 5 且都需重新開機嵌入式控制器12始能執行新基本輸入輸 出系統，不免對於消費者造成不便。 再者，由於電子裝置重新開機所需的時間（約30秒至 1分鐘）甚長於嵌入式基本輸入輸出系統更新所需的時間（ 約5〜10秒），而電子裝置中的主要控制是由處理單元11 10 負責，因而即便嵌入式控制器12短時間内停止對周邊設 備控制亦不會讓電子裝置的穩定性產生明顯的影響，因而 若能於更新基本輸入輸出系統内的時間令嵌入式控制器 12暫時禁止對於第二記憶體125的存取，並於更新完成 後即恢復嵌入式控制器12對第二記憶體125的存取，而 15 第二記憶體125中的資料為已更新的基本輸入輸出系統。 因而，嵌入式控制器12無需重新開機與應用額外地記憶 體空間，即可完成嵌入式控制器的基本輸入輸出系統更新 之目的。 【發明内容】 20 因此，本發明之一目的，是在提供一種電子裝置中嵌 入式控制器之基本輸入輸出系統之更新方法，係使篏入式 控制於基本輸入輸出系統更新時進入一睡眠模式，以達到 無需重新開機之功效。 3 本發明之一目的，是在提供一種電子裝置中嵌入式控 9 200419450 制器之基本輸入輸出系統之更新方法，以達到無須佔用額 外記憶體空間下更新基本輸入輸出系統之功效。 於是，本發明之電子裝置中嵌入式控制器之基本輸入 輸出系統之更新方法，該電子裝置具有一控制該電子裝置 5 整體動作之處理單元、一控制該電子裝置之周邊設備並受 該處理單元控制之嵌入式控制器及一儲存該嵌入式控制器 之基本輸入輸出系統並受該處理單元與該嵌入式控制器存 取控制之記憶體，該更新方法包括以下步驟： A) 當該嵌入式控制器收到一自該處理單元輸出之更新 10 命令時，該嵌入式控制器由一正常模式進入一睡眠模式， 以中止該嵌入式控制器對該記憶體之存取； B) 當該處理單元偵測到該嵌入式控制器已進入該睡眠 模式時，則該處理單元更新該記憶體中的基本輸入輸出系 統；及 15 C)當該處理單元已完成更新該基本輸入輸出系統，則 輸出一喚醒命令至該嵌入式控制器，使該嵌入式控制器由 該睡眠模式變成該正常模式，以恢復對該記憶體之存取。 【實施方式】 本發明之前述以及其他技術内容、特點與功效，在以 20 下配合參考圖式之一較佳實施例的詳細說明中，將可清楚 的明白。 本發明是用來更新電子裝置中嵌入式控制器之基本輸 入輸出系統之方法。如第四圖，電子裝置可為諸如筆記型 電腦之類的電子裝置而大致包含一處理單元2、一嵌入式 10 200419450200419450 Description of the invention (1 [Technical field to which the invention belongs] The present invention relates to a method for updating a basic input-output system, in particular to a method for updating a basic input-output system of an embedded controller in an electronic device. 5 [Previous technology In order to increase the functions and performance of electronic devices, in addition to enhancing the functions of processing units (such as microprocessors and chipsets) of existing electronic devices, it is also possible to use an additional control device (Embedded Controlled, EC), or Keyboard Controlled (KBC), is responsible for 10 new functions. For example, as shown in the first figure, the general notebook computer architecture includes a processing unit 11 and an embedded controller 12. The processing unit U refers to the microprocessor and the north-south bridge chip and is used to control the main equipment in the notebook computer, such as controlling the hard disk 111, optical drive 112, universal serial bus (USB) 113, display, etc. Embedded control 15 system 12 is responsible for controlling some peripheral devices and functions in the notebook computer, such as controlling the built-in mouse (internal po inting device) 12l ·, internal keyboard 122, battery 123, port 124 for external keyboard or external pointing device. In addition, the basics of processing unit 11 The input / output system 20 (Basic Input / Output System, BIOS) is stored in the first memory 114. Since the embedded controller 12 is similar to the processing unit 11 as an independent system, the embedded controller 12 also has a storage in The basic input and output system in the second memory 12 5. With the advancement of technology or the detection of bugs in software, etc., based on 200419450. ~ '.......,-' Meaning,-; V.- ;> ^ Hanging, issuing day §e day day d, this input and output system λ system inevitably needs to be updated (Update) operation, so the memory 114, 125 containing the basic input and output system will mostly use erasable programming Erasable Programmable Read-Only Memory (EPROM), such as Electronically Erasable Programmable Read-Only Memory (EEPROM), Flash Memory And at a faster flash memory mainstream now update the basic input output system of the method of the embedded controller 12 can be divided into the following three. The first method is to directly pull out the second memory 125 and reprogram it with the programmer 10 (Programmer). Therefore, consumers cannot update the basic input / output system by themselves, and the entire electronic device needs to be returned to the manufacturer who owns the recorder for repair. In this way, it not only causes inconvenience to consumers, but also for manufacturers, it is time-consuming, labor-intensive, and inconsistent to take out the memory that has been assembled in the electronic device to re-burn and complete the burn-in. 15 The second method is a software method to implement the basic input / output system for updating the embedded controller 12. In conjunction with the second figure, this software is a flash utility in the setup computer, and a random access memory (RAM) 126 is required in the embedded controller 12. In step 131, when the processing unit 11 executes the update program, the processing unit 11 notifies the embedded controller 125. Secondly, in step 125, the embedded controller 12 copies the basic input / output system originally stored in the second memory 125 to the random access memory 126, so that the embedded controller 12 can directly read the temporary memory when needed. The program stored in the random access memory 126 performs the work without always reading the program from the second memory 125. At this time, if step 133, the process 7 200419450 <? :: ϊ; ... ΓΓ 'unit 11 can update the basic input / output system program in the second memory 125. In this way, the basic input / output system updated in the second memory 125 can be completed by using the update program, and the inconvenience of the first update method can be solved. However, this update method requires additional RAM 5 126 space to execute the program, and after updating the basic input / output system in the second memory 125, the embedded controller 12 needs to wait until the next restart ( After reset), the updated basic input and output system can be executed. The third method is to update the basic input / output system of the embedded controller by using an update program. This method first divides the second memory 10 body 125 'into two banks (Banks) 127 and 128, and both blocks 127 and 128 store a basic input and output system. The embedded controller 12 needs basic The program in the I / O system is read from block 127. Then, when the processing unit 11 executes the update program, in step 141, the processing unit 11 updates the basic input-output system in another block 128. 15 In this way, as with the second update method, when the processing unit 11 updates the basic input / output system in the block 128, the embedded controller 12 can still read the basic input / output system in the block 127 for execution. However, after the same basic input / output system is updated, the updated basic input / output system cannot be executed immediately. It is still necessary to restart the computer to perform step 142 to update the updated basic input / output system in block 20 128 to another In block 127, a new basic input-output system can be implemented. Therefore, this method has the disadvantages of doubling the memory space and restarting the system to implement the new basic input and output system. Therefore, the second and third software update methods allow consumers to update on their own 8 200419450-, ί: ,,,,,, -s, <-s,,-.-; ^, "...... .....- ---, ,,, f ,, / '〆,',-'琰, Po Ming explanation) | :: ii |: | jPi ^ i ^; iN; :: IINiii: | i : I | v ^! I !; iliii: iii ^! I | ili ^: ^ ll: l 'Basic input-output system to solve the inconvenience caused to consumers and manufacturers in the first way. However, the second kind Both the third software update method and the third software update method need to be applied to additional memory space (such as the random access memory 126 in the second method and the block 128 in the third method), resulting in increased costs. 5 Rebooting the embedded controller 12 can only implement the new basic input and output system, which will inevitably cause inconvenience to consumers. Furthermore, the time required for the electronic device to restart (about 30 seconds to 1 minute) is much longer than the embedded basic input and output The time required for system update (about 5 ~ 10 seconds), and the main control in the electronic device is the responsibility of the processing unit 11 10, so even the embedded control If the controller 12 stops controlling peripheral devices for a short period of time, it will not significantly affect the stability of the electronic device. Therefore, if the time in the basic input output system can be updated, the embedded controller 12 temporarily prohibits the second memory 125. After the update is completed, the embedded controller 12 restores the access to the second memory 125, and the data in the second memory 125 is the updated basic input and output system. Therefore, the embedded control The device 12 can complete the purpose of updating the basic input and output system of the embedded controller without restarting and applying additional memory space. [Summary of the Invention] 20 Therefore, one object of the present invention is to provide an electronic device embedded in the electronic device. The method for updating the basic input / output system of the embedded controller is to make the in-line control enter a sleep mode when the basic input / output system is updated, so as to achieve the effect of no need to restart the computer. The method of updating the basic I / O system of the embedded controller 9 200419450 controller in the device, so as not to occupy additional The effect of updating the basic input-output system in the memory space. Therefore, the method for updating the basic input-output system of the embedded controller in the electronic device of the present invention, the electronic device has a processing unit that controls the overall operation of the electronic device 5, An embedded controller that controls the peripheral equipment of the electronic device and is controlled by the processing unit, and a memory that stores the basic input and output system of the embedded controller and is controlled by the processing unit and the embedded controller, The update method includes the following steps: A) When the embedded controller receives an update 10 command output from the processing unit, the embedded controller enters a sleep mode from a normal mode to suspend the embedded controller pair. Access to the memory; B) when the processing unit detects that the embedded controller has entered the sleep mode, the processing unit updates the basic input-output system in the memory; and 15 C) when the processing The unit has completed updating the basic input-output system, and outputs a wake-up command to the embedded controller, so that the embedded controller The device becomes the sleep mode from the normal mode to access memory of the recovery. [Embodiment] The foregoing and other technical contents, features, and effects of the present invention will be clearly understood in the detailed description of a preferred embodiment with reference to the drawings at 20 or less. The present invention is a method for updating a basic input-output system of an embedded controller in an electronic device. As shown in the fourth figure, the electronic device may be an electronic device such as a notebook computer and generally includes a processing unit 2 and an embedded 10 200419450.
控制器3與一記憶體4。 處理單元2是電子裝置的中樞而可為微處理器與南北 橋晶片組，以負責控制電子裝置中必要設備，例如控制硬 碟、光碟機、通用序列匯流排等等。另外，實現本例之更 5 新方法的更新程式係儲存於硬碟中或者以韌體方式建置， 而處理單元2係可執行此更新程式。 嵌入式控制器3係受處理單元2控制而負責控制電子 裝置之一些周邊設備或附屬功能，例如内建滑鼠、内建鍵 盤、電池與連接埠等等。處理單元2和各周邊設備可對嵌 10 入式控制器3發出一中斷訊號（interrupt signal)，使欲入式 控制器3可依照中斷訊號來工作。平時，嵌入式控制器3 是致能各中斷訊號，亦即當收到中斷訊號時，則會依照各 中斷訊號的請求内容而工作。然而，嵌入式控制器3亦能 依需求而禁能部分中斷訊號或所有中斷訊號，詳言之，若 15 此中斷訊號已禁能，則即使此中斷訊號輸入，嵌入式控制 器3亦會無視於此中斷訊號而不執行對應的工作。再者， 為了省電與工作效率等因素考量，嵌入式控制器3可於一 正常模式與一睡眠模式中切換。在正常模式中，嵌入式控 制器3則是正常地控制各周邊設備與接受處理單元2的命 20 令而工作。在睡眠模式時，嵌入式控制器3會依照預設條 件而中斷對於部分或所有周邊設備的控制（容後再述），以 有效降低耗電量。 記憶體4具有兩區塊41、42，其中一區塊41為開機 $ 區塊（Boot Block)以用來儲存開機所需之資料或程式，而 11 200419450 玖，赛明說明:（7: .) ¾ 另一區塊42用來儲存嵌入式控制器3之基本輸入輸出系 統。一般諸如程式、軟體或檔案之類的物件的前端會有一 表頭（header)，以提供與物件相關的資訊，例如註解文字 、建立時間等等之類，此表頭區421内資料於資料更新時 5 通常不會變更。所以，儲存於區塊42中的基本輸入輸出 系統可大致分別一資料不可變更之表頭區421與一資料或 程式可隨系統更新之正常程式碼區422。在正常程式碼區 422儲存周邊設備控制之必要程式碼與嵌入式控制器3執 行工作所需之程式，所以嵌入式控制器3工作時常需至正 10 常程式碼區422中讀取對應的程式來執行。因而，在基本 輸入輸出系統更新時通常是更新正常程式碼區422中的程 式或資料，而不會更新表頭區422内的資料。另外，記憶 體4為可抹除式的唯讀記憶體，例如電子式可抹除程式化 唯讀記憶體、快閃記憶體，本例之記憶體4為快閃記憶體 15 。再者，為了讓資源充分利用，所以記憶體通常可供數個 電子元件使用，本例之記憶體4即可供處理單元2與嵌入 式控制器3使用，而可受處理單元2與嵌入式控制器3的 控制來存取資料或程式於其中。另外，由於記憶體4本身 具有單一時間時僅能接受一電子元件存取之限制條件，所 20 以若處理單元2存取記憶體4時，則嵌入式控制器3就無 法存取記憶體4。 配合前述的架構，在下文中將配合第五圖來說明本實 施例之更新方法。本例的更新方式是以一更新程式來實現 r ，此更新程式係可儲存於電子裝置的硬碟或記憶體中並由 12 200419450 功:、母日日紛日日γ s Λ ：7又7一卩几·；^ \ u y 處理單元2來執行。當使用者欲更新嵌入式控制器3之基 本輸入輸出系統時，則可啟動此更新程式以使處理單元2 對應執行此更新程式。在此先假設嵌入式控制器3位於正 常模式，所以嵌入式控制3致能與處理單元2和周邊設備 5 的中斷訊號。 如步驟51，當更新程式被啟動時，則處理單元2會 輸出一更新命令至嵌入式控制器3。為了讓嵌入式控制器 3接收此更新命令，所以處理單元2會先發出一中斷訊號 ，來使嵌入式控制器3接收更新命令，以令嵌入式控制器 10 3由正常模式進入睡眠模式。 配合第六圖，嵌入式控制器3需執行步驟61〜64來進 入睡眠模式。當嵌入式控制器3預備進入睡眠模式時，如 步驟61，嵌入式控制器3會儲存目前狀態，以供切換成 正常模式可利用應用先前儲存的狀態資訊來讓嵌入式控制 15 器3迅速恢復成進入睡眠模式前的狀態。禁能除了與處理 單元2外的中斷訊號。在步輝62中，嵌入式控制器3會 禁能除了與處理單元2外的所有中斷訊號，使嵌入式控制 器2在睡眠模式中不再因其他週邊設備發出的中斷訊號來 執行任何工作，因此亦不會有需要存取記憶體42内程式 20 或資料的機會發生，於是在睡眠模式中，嵌入式控制器3 不會對記憶體42執行存取動作。再者，即使嵌入式控制 器3於睡眠模式中，但由於嵌入式控制器3維持致能與處 理單元2間的中斷訊號，嵌入式控制器3仍受處理單元2 &控制而非完全中斷與外部溝通。另外，由於進行基本輸入 13 200419450 ^ r q 7、 7乂·：/观Li./J、 7 八 ' 輸出系統42更新時，正常程式碼區422内程式或資料可 能會發生變化，如此當嵌入式控制器3恢復成正常模式時 ，若嵌入式控制器3讀取的資料已變更時則會發生存取錯 誤（error)，所以如步驟63，欲入式控制器3對於記憶體4 5 的存取位址更會跳至程式的最前端不會再更改的部分（即 表頭區421)，以使嵌入式控制器3跳回正常模式時，亦不 會發生錯誤。另外，如步驟64，嵌入式控制器3的時序 (clock)會暫停。如此，依據前述步驟61〜64，欲入式控制 器3進入睡眠模式而不會再作任何動作，直至收到處理單 10 元2輸出之喚醒命令為止。應注意的是，嵌入式控制器3 無需依序執行步驟61〜64，而可依要調整執行順序或者同 時執行，並不應受限於本實施例的說明。 其次，在步驟52中，處理單元2會確認嵌入式控制 器3是否已進入睡眠模式中。若為是時，則執行步驟53 15 ;反之，若為否時，則繼續執行步驟52。由於一般嵌入 式控制器3執行步驟61〜64以進入睡眠模式所需的時間為 一定（約500nsec)，因而本例中的步驟52中，處理單元2 係測試更新命令發生後的等待時間是否超過嵌入式控制器 3進入睡眠模式所需之時間，來判斷嵌入式控制器3是否 20 進入睡眠模式。 在步驟53中，當已確認嵌入式控制器3進入睡眠模 式時，處理單元2依照更新的檔案來開始更新於記憶體4 中的基本輸入輸出系統。 ? 而後，在步驟54中，處理單元2會確認更新是否已 14 200419450 、、·、、<·¥ ^ S s 、、、'·'··、··' 、'、、'<〇、 , 、 vs -s S s ^ ~ ；· s5 V , '·、'·· ' ' 's s s " 、、、- ' <-〆、,、、 、、 、一、、、 5、 ' 10 ) ： ： ：V^ 完成。若完成時，則執行涉驟55，反之，則跳回步驟53 繼續更新欲入式控制器3之基本輸入輸出系統。 在步驟55中，處理單元2會輸出一喚醒命令至嵌入 式控制器3，以使嵌入式控制器3由睡眠模式回復成正常 5 模式，以完成嵌入式控制器3之基本輸入輸出系統的更新 程序。由於嵌入式控制器3於睡眠模式中仍致能與處理單 元2的中斷訊號，所以處理單元2可先發出中斷訊號來使 嵌入式控制器3接收喚醒命令。配合第七圖，當於睡眠模 式中的嵌入式控制器3收到喚醒命令時，則會依據先前步 10 驟61中儲存的狀態資訊來恢復成先前正常模式中的狀態（ 如步驟71)、致能先前於步驟62禁能的中斷訊號（如步驟 72)與回復成時序（如步驟73)，以使嵌入式控制器3切換 成正常模式來恢復工作。如此，當嵌入式控制器3繼續工 作時，其自記憶體4中存取的基本輸入輸出系統是經步驟 15 53更新過的程式，所以無需重新開機，嵌入式控制器3 即可應用新的基本輸入輸出系統。 歸納上述，本發明之電子裝置中嵌入式控制器之基本 輸入輸出系統之更新方法，係於更新記憶體4之基本輸入 輸出系統時，讓嵌入式控制器3進入睡眠模式而不會執行 20 任何工作，以使處理單元2可順利更新記憶體4中的基本 輸入輸出系統，並於更新後始使嵌入式控制器3切換成正 常模式而可直接應用已更新的基本輸入輸出系統。因而， 相較習知，本發明可達到無需額外佔用記憶體空間與無須 , 重新開機之功效。 15 200419450 紋、囊明說明（14 ) …: 淮以上所述者，僅為本發明之較佳實施例而已， !以此限定本發明實施之範圍，即大凡依本發明申請：利 乾圍及發明說明書内容所作之簡單的等效變化與修飾 應仍屬本發明專利涵蓋之範圍内。 【囷式簡單說明】 第一圖是一種習用筆記型電腦之架構示意圖。 第二圖是一種習用後入式控制器之基本輸入輸出系統 更新方式之示意圖。 第三圖是另一種習用喪入式控制器之基本輸入輸出系 统更新方式之示意圖。 μ 第四圖是本發明之電子裝置中嵌入式控制器之基本輸 入輸出系統之更新方法的較佳實施例的示意圖。 第五圖是第四圖之實施例中處理單元的流程圖。 第六圖是第四圖中被入式控制器由正常模式進入睡眠 模式的流程圖。 第七圖是第四圖中嵌入式控制器由睡眠模式進入正常 模式的流程圖。 16 200419450Controller 3 and a memory 4. The processing unit 2 is the center of the electronic device and can be a microprocessor and a North-South bridge chipset, and is responsible for controlling the necessary equipment in the electronic device, such as controlling hard disks, optical drives, universal serial buses, and so on. In addition, the update program that implements the new method of this example is stored in the hard disk or built in firmware, and the processing unit 2 can execute this update program. The embedded controller 3 is controlled by the processing unit 2 and is responsible for controlling some peripheral devices or auxiliary functions of the electronic device, such as a built-in mouse, a built-in keyboard, a battery, and a port. The processing unit 2 and each peripheral device can send an interrupt signal to the embedded controller 3, so that the intended controller 3 can work according to the interrupt signal. Usually, the embedded controller 3 enables each interrupt signal, that is, when receiving the interrupt signal, it will work according to the request content of each interrupt signal. However, the embedded controller 3 can also disable some or all of the interrupt signals as required. In particular, if this interrupt signal is disabled, even if this interrupt signal is input, the embedded controller 3 will ignore it. The signal is interrupted here without performing the corresponding task. Furthermore, in order to consider factors such as power saving and working efficiency, the embedded controller 3 can be switched between a normal mode and a sleep mode. In the normal mode, the embedded controller 3 works normally by controlling the peripheral devices and receiving commands from the processing unit 2. In the sleep mode, the embedded controller 3 interrupts control of some or all peripheral devices according to preset conditions (to be described later) to effectively reduce power consumption. Memory 4 has two blocks 41 and 42, one of which is a Boot Block to store data or programs required for booting, and 11 200419450 玖, Saiming explained: (7:. ) ¾ Another block 42 is used to store the basic input and output system of the embedded controller 3. Generally, the front end of an object such as a program, software, or file will have a header to provide information related to the object, such as annotation text, creation time, etc. The data in this header area 421 is updated with the data. Hour 5 usually does not change. Therefore, the basic input-output system stored in the block 42 can roughly separate a header area 421 in which data cannot be changed and a normal code area 422 in which data or programs can be updated with the system. In the normal code area 422, the necessary code for peripheral device control and the program required by the embedded controller 3 to perform work are stored, so the embedded controller 3 often needs to read the corresponding program in the positive code area 422 when working. To execute. Therefore, when the basic input / output system is updated, the program or data in the normal code area 422 is usually updated without updating the data in the header area 422. In addition, the memory 4 is an erasable read-only memory, for example, an electronic erasable stylized read-only memory and a flash memory. The memory 4 in this example is a flash memory 15. Furthermore, in order to make full use of resources, the memory is usually available for several electronic components. The memory 4 in this example can be used by the processing unit 2 and the embedded controller 3, and can be received by the processing unit 2 and the embedded. The controller 3 controls to access data or programs therein. In addition, since the memory 4 itself has a restriction condition that only an electronic component can be accessed at a single time, so if the processing unit 2 accesses the memory 4, the embedded controller 3 cannot access the memory 4 . In conjunction with the foregoing architecture, the update method of this embodiment will be described below with reference to the fifth figure. In this example, the update method is implemented by an update program. This update program can be stored in the hard disk or memory of the electronic device and is performed by 12 200419450. The mother day and day γ s Λ: 7 and 7 A few days ·; ^ \ uy processing unit 2 to execute. When the user wants to update the basic input / output system of the embedded controller 3, the update program can be activated to cause the processing unit 2 to execute the update program accordingly. It is assumed here that the embedded controller 3 is in a normal mode, so the embedded control 3 enables interrupt signals with the processing unit 2 and the peripheral device 5. In step 51, when the update program is started, the processing unit 2 outputs an update command to the embedded controller 3. In order for the embedded controller 3 to receive the update command, the processing unit 2 first sends an interrupt signal to enable the embedded controller 3 to receive the update command, so that the embedded controller 10 3 enters the sleep mode from the normal mode. With the sixth figure, the embedded controller 3 needs to execute steps 61 to 64 to enter the sleep mode. When the embedded controller 3 is ready to enter the sleep mode, as in step 61, the embedded controller 3 stores the current state for switching to the normal mode. The previously stored state information can be used to make the embedded controller 15 quickly recover. The state before entering the sleep mode. Disable interrupt signals except for processing unit 2. In Buhui 62, the embedded controller 3 disables all interrupt signals except the processing unit 2 so that the embedded controller 2 no longer performs any work in the sleep mode due to interrupt signals from other peripheral devices. Therefore, there is no chance that the program 20 or data in the memory 42 needs to be accessed. Therefore, in the sleep mode, the embedded controller 3 does not perform an access operation on the memory 42. Furthermore, even if the embedded controller 3 is in the sleep mode, since the embedded controller 3 maintains an interrupt signal between the enable and the processing unit 2, the embedded controller 3 is still controlled by the processing unit 2 & instead of being completely interrupted Communicate with external parties. In addition, since the basic input 13 200419450 ^ rq 7, 7 乂 ·: / view Li./J, 7 8 'output system 42 is updated, the program or data in the normal code area 422 may change, so when embedded When the controller 3 returns to the normal mode, if the data read by the embedded controller 3 has been changed, an access error will occur. Therefore, as in step 63, the memory of the controller 4 for the memory 4 5 The address will jump to the most front-end part of the program (that is, the header area 421), so that when the embedded controller 3 jumps back to the normal mode, no error will occur. In addition, as in step 64, the clock of the embedded controller 3 is suspended. In this way, according to the foregoing steps 61 to 64, the on-type controller 3 enters the sleep mode without performing any action until it receives the wake-up command output from the processing unit 10 yuan 2. It should be noted that the embedded controller 3 does not need to execute steps 61 to 64 in sequence, but may adjust the execution sequence or execute at the same time, and should not be limited to the description of this embodiment. Secondly, in step 52, the processing unit 2 confirms whether the embedded controller 3 has entered the sleep mode. If yes, go to step 53 15; otherwise, if no, go to step 52. Because the general embedded controller 3 executes steps 61 to 64 to take a certain amount of time to enter the sleep mode (about 500 nsec), in step 52 in this example, the processing unit 2 tests whether the waiting time after the update command occurs exceeds The time required for the embedded controller 3 to enter the sleep mode to determine whether the embedded controller 3 has entered the sleep mode. In step 53, when it is confirmed that the embedded controller 3 enters the sleep mode, the processing unit 2 starts to update the basic input / output system in the memory 4 according to the updated file. ? Then, in step 54, the processing unit 2 confirms whether the update has been performed. 14 200419450, ..., ... ^ S s,,, '...', ..., ',', '< 〇 ,,, Vs -s S s ^ ~; · s5 V, '·,' ·· '' 'sss ", ,,-' < -〆 ,,,,,,, one ,,, 5 ,, ' 10)::: V ^ completed. If it is completed, step 55 is executed, otherwise, it returns to step 53 to continue to update the basic input and output system of the on-type controller 3. In step 55, the processing unit 2 outputs a wake-up command to the embedded controller 3, so that the embedded controller 3 returns from the sleep mode to the normal 5 mode to complete the update of the basic input and output system of the embedded controller 3. program. Since the embedded controller 3 still enables the interrupt signal from the processing unit 2 in the sleep mode, the processing unit 2 may first issue an interrupt signal to enable the embedded controller 3 to receive the wake-up command. With the seventh figure, when the embedded controller 3 in the sleep mode receives the wake-up command, it will return to the state in the previous normal mode according to the state information stored in step 61 of step 10 (step 71), Enable the interrupt signal (such as step 72) previously disabled in step 62 and restore the timing (such as step 73) to enable the embedded controller 3 to switch to the normal mode to resume work. In this way, when the embedded controller 3 continues to work, the basic input and output system accessed from the memory 4 is the program updated in steps 15 to 53, so the embedded controller 3 can apply the new one without restarting. Basic input output system. To sum up, the method for updating the basic input output system of the embedded controller in the electronic device of the present invention is to update the basic input output system of the memory 4 to allow the embedded controller 3 to enter the sleep mode without executing any of the 20 It works so that the processing unit 2 can smoothly update the basic input / output system in the memory 4, and after the update, the embedded controller 3 is switched to the normal mode and the updated basic input / output system can be directly applied. Therefore, compared with the prior art, the present invention can achieve the effects of no additional occupation of memory space and no need to restart. 15 200419450 Grain and description (14)…: The above is only the preferred embodiment of the present invention, so as to limit the scope of implementation of the present invention, that is, to apply for: The simple equivalent changes and modifications made in the description of the invention should still fall within the scope of the invention patent. [Brief description of the formula] The first figure is a schematic diagram of the architecture of a conventional notebook computer. The second figure is a schematic diagram of the basic I / O system update method of a conventional rear-entry controller. The third diagram is a schematic diagram of another basic input-output system update method of a conventional funnel-type controller. The fourth diagram is a schematic diagram of a preferred embodiment of a method for updating a basic input-output system of an embedded controller in an electronic device of the present invention. The fifth diagram is a flowchart of the processing unit in the embodiment of the fourth diagram. The sixth diagram is a flowchart of the passive controller entering the sleep mode from the normal mode in the fourth diagram. The seventh figure is a flowchart of the embedded controller from the sleep mode to the normal mode in the fourth figure. 16 200419450
玖、發明說明(12 ) 【圖式之主要元件代表符號簡單說明】 2處理單元 3嵌入式控制器 4記憶體 41、42區塊 421表頭區 422正常程式碼區发明 Description of the invention (12) [Simplified description of the main symbols of the drawings] 2 Processing unit 3 Embedded controller 4 Memory 41, 42 Block 421 Header area 422 Normal code area
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