TW200418181A - SOI chip structure with dual-thickness active device layer and method for producing the same - Google Patents

Abstract

A silicon-on-insulator (SOI) chip structure (or wafer structure) with a dual-thickness active device layer on an insulative layer comprises an active device layer (capable of being sub-divided into a thinner active device layer and a thicker active device layer); at least a shallower buried oxide, in which each buried oxide is located at a specified location beneath the active device layer; at least a deep trench surrounding the buried oxide, the installation depth of the deep trench being deeper than the installation depth of the buried oxide; and a grounding layer in connection with the active device layer and the buried oxide. During the production process, the active device layer, the buried oxide and the deep trench are formed by processing a first wafer. The grounding layer belongs to a second wafer. The first wafer and the second wafer are formed into an SOI wafer having a dual-thickness active device layer by a wafer bonding process.

Description

200418181 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention provides a SOI wafer structure having a dual-thickness active device layer, especially a shallow oxide region ( shallower buried oxide), the periphery of which has an oxide region structure surrounded by a larger set of deep trenches. The present invention also provides a method for manufacturing the same, especially a method in which An oxidation region surrounded by a deep trench having a larger set depth makes the oxidized region after the wafer to which it belongs is flipped to bond and cut (sp 1 it) with another wafer that is a ground layer. A double-thickness element layer SOI wafer structure with respect to a thinner element layer on the shallower oxidation region and a thicker element layer not provided with the thicker element layer on the oxidation region can be formed and a manufacturing method thereof. [Prior art] Please refer to the first figure, which is a schematic diagram of a transverse if-plane of a conventional SOI (Silicon on I n s u 1 a tor) wafer structure 10. The so-called IO chip structure is that the silicon element layer is on an insulator (such as silicon dioxide). The SO I wafer structure 10 includes an element layer 12 for layout of integrated circuit elements, an insulating layer 14 located below the element layer 12 and a ground layer 16 located at the insulating layer 14. Below. Generally speaking, as far as the element layer 12 is concerned, its thickness dl is uniform, which means that the conventional SO I wafer structure 10 is a soi crystal with a single-thickness element layer. 200418181 V. Description of the invention (2 ). The insulating layer 14 is also commonly referred to as a buried oxide 'layer (BOX). There are many ways to form the buried oxide layer, such as directly implanting oxygen ion ions into a silicon substrate, and then adding high temperature to the substrate. The original silicon substrate is oxidized, so that the original silicon substrate structure can form a buried oxide layer of stone dioxide at a certain predetermined depth and degree. The S0 I crystal element layer 1 2 generally has a thickness d 1 of about 0.3 μm to 10 μm.

However, in the current system single-chip (Sytem ο na Chi, S 0 C) is gradually becoming the mainstream of the market, the component layers on the same chip structure may need to layout many different types of circuit components, these circuit components are each With their respective dimensions and heat dissipation conditions, operating current or voltage characteristics, it is difficult to meet the requirements of all components on a SOI chip structure with uniform thickness. In other words, some components have higher operating voltages or larger currents and more heat dissipation, which is more suitable. Suitable layout is in the position of thicker component layers (due to larger operating currents and larger breakdown voltages, etc.) ; And if it is a component with lower operating voltage or less heat dissipation, it only needs to be placed on the component layer position that is not so thick. If the thickness of the component layer of the entire SOI wafer structure is uniform, those components that require a larger operating voltage or have more heat dissipation can also be laid out on this wafer structure, but relatively large wafer areas are required. As a result, the number of wafers that can be laid out on a single wafer will be reduced, which does not meet economic needs. In addition, the conventional S0 I wafer structure 10 has a resistance to electrostatic discharge (ESD) due to

200418181 V. Description of the invention (3) It is difficult to effectively grounded the element layer 12 and the break-down voltage of the element layer 12 is insufficient due to the limitation of the thickness dl. Therefore, it can be seen from the above that the S 0 I chip structure of the above-mentioned conventional technology obviously has inconveniences and defects in practical use, and needs to be improved. The reason is that the inventor felt the above-mentioned defects. Can be improved, Naite researched it, and finally proposed a rational design and effective improvement

invention. [Summary of the Invention] The main object of the present invention is to provide a SOI wafer structure with a double-thickness element layer. As a shallower oxide region is formed on the first wafer—and the oxide region surrounds the oxide region and the depth is greater than the oxidation The depth of the deep groove in the area is set, and the thickness of the element layer is smaller than that of the shallower oxidation area (above). The thickness of the element layer is not provided in the shallower oxidation area (above), and it can provide a variety of different types of component layouts. On the first wafer element layer. This first wafer will be flipped later, and bonded to another second wafer (also referred to as a handle wafer) as a ground layer, and then the first wafer after bonding will be bonded. Slicing (sp 1 it) and subsequent surface treatment to form a SO I wafer with a double-thickness element layer.

Page 7 200418181 V. Description of the invention (4) Another object of the present invention is to provide a method for manufacturing the above-mentioned SOI wafer structure. A pair of alignment marks is set at a first predetermined position on a first wafer, and At least one annular deep groove having a first predetermined setting depth is set at two predetermined positions, and then a second predetermined setting depth (thermal oxidation) is formed inside the second predetermined position (that is, the deep groove) by thermal oxidation. This second predetermined setting depth is smaller than the first predetermined setting depth). Because the setting depth of the deep trench (the first predetermined setting depth) is greater than the setting depth of the oxide region (the second predetermined setting depth) formed later, and the surface of the deep trench (and the surface of the wafer) has a silicon nitride (si 1 icon ni tr i de) The thin film protection prevents the bird's beak effect caused by the uneven expansion of the silicon lattice during the thermal oxidation of the silicon lattice during the formation of the oxidized region, and thus does not cause damage to the adjacent element layers. After processing the deep trenches and oxidized areas on the first wafer, the first wafer is turned over and may have a surface pure silicon layer (si 1 ic ο η 1 ayer) or a surface oxide layer (oxidized layer) or A second wafer (also called a carrier wafer) with a metal layer on the surface is bonded, and then the bonded first wafer is cut and subjected to subsequent surface treatment to obtain the S 0 I wafer structure of the present invention. . In order to achieve the above object, the present invention is mainly to provide a SOI wafer structure having a double-thickness element layer and a manufacturing method thereof. The wafer structure with a double-thickness element layer S 0 I includes: an element layer (which can be subdivided into a thinner element layer and a thicker element layer); at least one shallower oxide region is disposed at a predetermined position of the element layer At least one deep trench surrounds the oxidized region, and the deep trench is 200418181 V. Description of the invention (5) The set depth is greater than the set depth of the oxidized region; and a ground layer is connected to the element < The method for manufacturing the SOI wafer structure of the double-thickness element layer includes the following steps: providing a first wafer; setting at least a pair of alignment marks at a first predetermined position of the first wafer ( alignment marks); at the second predetermined position of the first wafer, at least a ring-shaped deep trench having a first predetermined set depth is etched; a silicon nitride (si 1) is deposited on the deep trench (and the wafer surface) icon nitride) thin film; #etch one (less than the first predetermined setting depth) of the fourth predetermined setting depth of the Shi Xi material area inside the deep trench at the second predetermined position; the second predetermined On the surface of Shi Xi inside the site, thermal oxidation is used to thermally oxidize the Shi Xi lattice to form an oxidation zone of the thermo 1 oxide material; by a chemical vapor deposition method ( CVD) deposited on the deep trench and filled with a crystalline oxide oxide ^ amorphous si 1 icon oxide); a chemical mechanical polishing method (CMP) was used to planarize and remove excess silicon oxide and gasified stones on the surface Thin film; providing a second wafer and flipping the first wafer, and simultaneously connecting the first wafer with the second wafer by means of wafer bonding; and cutting the flipped first at a second predetermined set depth Wafer; final surface treatment. In order to allow your reviewers to further understand the technology, means and effects adopted by the present invention to achieve the intended purpose, please refer to the following detailed description and accompanying drawings of the present invention. I believe that the purpose, characteristics and special black of the present invention1. This can lead to a deep and specific understanding '

Page 9 200418181

For reference and explanation, 'is not intended to limit the invention. [Embodiment] Please refer to the second diagram A, the second diagram β, and the second diagram c. The second diagram A is a schematic diagram of the first embodiment 50 of the SOI wafer structure with double and thick element layers. FIG. B is a top view of the first wafer 60 in FIG. 2 after the manufacturing is completed. The first image C is another embodiment of the second image a. The 50 I wafer structure 50 of the present invention includes a first wafer 60 and a second wafer 6 丨. The first wafer 60 and the first wafer 61 will use a wafer in the production process. The bonding methods are bonded to each other to form an SO I wafer structure 50 after dicing. The first embodiment 50 includes an element layer 62 for layout of integrated circuit components, at least one deep trench 64, and a buried oxide layer (BOX) (i.e., hafnium oxide region) element layer 62 and oxide surrounded by the deep trench. Region 65 is connected to a silicon layer 61 below. The buried oxide region W surrounded by the element layer 62, the deep trench 64, and the deep trench 64 is a part of the first wafer 60. The silicon layer 61 under the element layer 62 and the oxide region 65 is the silicon layer of the second carrier wafer 6 and functions as the same ground layer. As shown in the upper view of the second figure B, the deep trenches 6 4 are arranged around the buried oxide layer 6 5, and the setting depth D 1 is greater than the setting depth D 2 of the buried oxide layer 65. Each of the oxidized regions 65 is disposed at a predetermined position on the first wafer 60, and it can also be said that it is disposed inside the deep trench 64. In practice, since the deep groove 64 < art system is formed earlier than this oxidation zone 65, after determining the predetermined position as long as the oxidation zone 65 is set, the reverse depth of the deep groove 64 4 should be set. Bit-

Page 10 200418181 V. Description of the invention.

Since the buried oxide layer 65 is formed by a thermal oxidation lattice expansion, if there is no arrangement surrounding the deep trench 64 during the formation process, due to the heating and oxidation of some silicon substrates, the lattice will expand up and down, making The first wafer element layer 62 is easily generated due to a lattice crack caused by the bird's beak effect around the oxidized region 65 during the thermal oxidation formation process. After the first trench 60 and the oxidized region 65 are formed, the first wafer 60 will be inverted (f 1 i p) and bonded to the second wafer 61. In this way, both the (thermally oxidized) oxidized region 65 and the element layer 62 of the first wafer 60 can be bonded to the silicon surface of the second wafer 61. In the SOI wafer structure 50, the 'second wafer 61 is the same ground layer, so that the integrated circuit components other than the element layer 62 disposed above the oxidized region 65 can be referred to the ground. From the perspective of the element layer 62, the thickness D 3 of the corresponding element layer 6 2 (ie, a thinner element layer) at a predetermined position where the oxidized region 65 is provided will be significantly smaller than that where the oxidized region 65 is not provided. The thickness D4 of the corresponding element layer 62 (ie, a thicker element layer). With this double thickness element

The component layers (thicknesses D3 and D4) of the SO I wafer structure 50 are provided, and the component layer 62 can be used to set different types of circuit components. The circuit elements may have different thicknesses of the element layers 62 at suitable positions due to differences in required operating voltage, current, or heat dissipation requirements. Some circuit components that require higher operating voltage, current, or higher power consumption or larger ground current can be placed at the position of the component layer 62 with a thickness equal to D4. Other operating currents or heat dissipation requirements are not Such a high circuit element may be provided at the position of the element layer 62 having a thickness equal to D3. So designed for

Page 11 200418181 V. Description of the invention (8) In addition to the requirements of matching circuit components, compared with the S0 I chip structure with only a single component layer thickness, there will not be a circuit with a large operating current and a large heat dissipation requirement. The components need to occupy a large wafer area and affect the number of chips carried on the entire wafer. In addition, 'taking the second wafer 61 as the ground layer' will make the present and future SOI wafer structure 50 more effective against the electrostatic discharge phenomenon. The first wafer 60 further includes at least a pair of alignment marks 67 arranged at a first predetermined position, which are located on the plane of the element layer and buried in the oxide layer. The purpose of setting the alignment marks is to allow the setting of the deep groove 64 and the oxidized area 65 afterwards (both by lithography and etching), so that the stepper and its mask can directly correspond to the above alignment marks. 6 7. When the two alignment marks can provide the alignment mechanism of a certain stepper, it will be convenient to lithography and etch the required deep grooves at the predetermined position of the first wafer 60 and even to form the oxidized area. Please refer to the second diagram C. The second diagram C is another schematic diagram of the tongue 0 of the first embodiment of the SOI wafer structure with a double-thickness element layer, which is another embodiment of the second diagram A. The depth D 1 of the deep groove 64 and the outer surface of the first wafer 60 after the wafer cutting (ie, the wafer cutting surface) 6 9 and the lower surface (ie, the lower silicon surface is also the wafer bonding surface). 6 8. Please refer to the third diagram A, which is a schematic diagram of the second embodiment 80 of the SO I wafer structure of the present invention. This second embodiment 80 includes an element layer.

Page 12 200418181 V. Description of the invention (9) 8 3 'At least one deep trench 8 4 and a buried oxide region' 85 surrounded by the deep trench 8 4. A buried oxide layer 87 is connected below the element layer 83 and the oxidized region 85. A silicon layer 88 functions as the same ground layer under the buried oxide layer 87. The element layer 83, the deep trench 84, and the buried oxide region 85 surrounded by the deep trench 84 are part of the first wafer 811. The buried oxide layer 87 and the underlying silicon layer 88 are the surface oxide layer and the silicon layer of the second carrier wafer 82.

The second carrier wafer 82 is used for carrying and grounding the SO I wafer structure 80 after being flipped and bonded with the first wafer 81. In the process of processing the first wafer 8 1, the deep trench 8 4 is filled with a silicon nitride (si 1 icon nitride) film in advance, and then a chemical vapor deposition (CVD) method is used after the oxide region 8 5 is formed. The generated silicon dioxide is filled, and the oxidized area 85 is thermal oxides. Regarding the choice of materials for the deep groove 84 and the oxidized area 85, there can be many different combinations of materials, and the same situation also occurs in the embodiments disclosed in the second figures A, B, and C. In addition, the width of the deep groove 84 is preferably 0.2 to 5 micrometers, and the depth (that is, the first predetermined setting depth) is preferably 0.1 to 10 micrometers.

Compared with the first embodiment of the present invention in the second diagram A and the second diagram B, the S 0 I wafer structure 80 of the third diagram A is connected to the first wafer 81 by the second wafer 82. Previously, a thermal oxide layer 87 had been formed on the surface of the second wafer 82 so that the thermal oxide layer 87 could be connected to the oxidized region 85 and the deep trench 84 after the two wafers were bonded. In terms of the angle of the element layer 8 3, the thickness D 5 of the element layer 8 3 (that is, a thinner element layer) provided with the oxidized region 85 will be smaller than that of the non-oxidized region 85.

Page 13 200418181 V. Description of the Invention (ίο). In other words, the board needs pieces; while the high-capacity electric 80 is also the same stepper that can set the bit thickness D6 at the first and last name, which is used to lay out circuit elements to lay out how high the film structure is. Such a groove 8 4 to remember 86 words The larger one has a speed or circuit element and one of its crystals is located outside the oxide layer 87, and the third SOI SOI element shown in Figure A (not shown) Layer 8 3 runs through to allow these SOI elements to be placed on the component layer 83 (that is, to put it lightly, there is no oxidized area 85J placement layer) the operating voltage may require a long time, 70 pieces of layer 8 3 will oxidize and disperse 3 The product of thermal power is the operating current. 'It doesn't need too much & it can be used specially. The third figure A has the VW / condition. This does not include at least one pair of alignment rods & several layers of so I crystal mask. Directly aligned with some of the 31 micro 6's on the micro circle 81, the predetermined micro-hi6 alignment is performed. The silicon handle of the oxidized area 85 (before formation) is etched deep and preferably aligned on the first wafer element. The two ends of the target. The second wafer 82 contains a silicon layer 88 in addition to the complex surface in advance, like the surface. Into a wafer structure of 8 G, even if it is already in the element layer. For example, even a Ϊ83 layout layer is set on the element layer) (also not shown) The S0 I element connected to the connection layer for current still needs to be guided. The so 1 non-conductive oxidation region 87 can be grounded to Shi Xizhan'f * tVia. 88 connection, please refer to the third figure B, the third figure 1 layer S (H chip structure of the second implementation g is a double-thickness element of the present invention

Another implementation aspect. The other intention of the deep groove 84 ^ is the setting depth of A # «4 in Figure 3 and the wafer cutting

200418181

Surface) 8 9 1 and the lower surface ('that is, the outer surface of the first wafer 8 1 (that is, the wafer cutting wafer bonding surface) 8 9 2. See the fourth figure A, the fourth figure is the invention s 〇I wafer structure Example 90, a schematic diagram. The third embodiment 90 has a device layer 93, at least one circle deep, 94, and a buried oxide region 95 surrounded by a deep trench 94. The device layer 93 and the oxide region 95 The lower layer is connected to a metal layer 96, and the metal layer "is a silicon layer 97 below, like the same ground layer.

The element layer 93, the deep trench 94, and the buried oxide region 95 surrounded by the deep trench 94 are part of the first and circle 81. A silicon layer 97 under the metal layer 96 is the silicon layer of the second carrier wafer 92. The metal layer 96 may be the surface metal layer of the second carrier wafer 92 or the surface metal of the first wafer 81.

It is the same as the actual example. The first wafer 9 1 also includes the element layer 9 3. The deep trench 9 4 with no depth equal to D 7 is surrounded by the deep trench 9 4, and an oxidation region with a depth equal to D 8 is set. 95. Due to the arrangement of the oxidized region 95, the relative thickness D 9 of the element layer 9 3 corresponding to the oxidized region 9 5 (ie, a thinner element layer) will be smaller than that of the element without the oxidized region 9 5. The thickness D1 0 of the layer 9 3 (that is, a thicker element layer). In this way, an SOI wafer structure with a double-thickness element layer is formed, so that different requirements of SO I are laid out at different thicknesses of the element layer 93. element. The deep trench 9 4 of the first wafer 91 is also filled with a silicon nitride film first 'before it is filled with the amorphous silicon oxide produced by the chemical vapor deposition method. The buried oxide region 9 5 is composed of thermal silicon oxide.

Page 15 200418181 V. Description of the invention (12) The difference between the fourth diagram A and the third diagram A is that the second wafer 92 of the fourth diagram A can be formed with a metal layer 96 on the surface, and the reversed The first wafer 91 is bonded. The metal layer 96 may be a metal system, that is, a metal layer 96 is a multilayer composite of many different metals, such as a metal layer or a metal alloy layer such as Ti, Ta, TiN, TaN, Au, or Cu. combination. Before the first wafer 91 is bonded, a thin metal layer may also be formed on its bonding surface to increase the bonding strength of the wafer.

In addition, in the fourth figure, when an SOI element such as 99 is laid out on the element layer 93 and grounded to the ground layer 9 7 with reference, its conductive plug 10 (covered by another insulating layer 102) need only be connected to The metal layer 9 6 is sufficient. The SO I element 919 is connected to the above-mentioned conductive plug 101 via an interconnect layer (not shown) provided on the element layer. The S 0 I wafer structure 90 of the fourth figure A also includes at least one pair of alignment marks g § located on both ends of the wafer of the first wafer element layer 93, the purpose of which has been described above. Please refer to the fourth diagram β, and the fourth diagram B is another schematic diagram of the third embodiment 80 of the SOI wafer junction having a double-thickness element layer according to the present invention, which is another embodiment of the fourth diagram A. The depth D7 of the deep trench 94 and the outer surface (ie, the wafer cutting surface) of the circle after cutting, and the lower surface (ie, the lower silicon surface) 104. π ®! r

Page 16 200418181 V. Description of the invention (13) Please refer to the fifth figure A to fifth figure J, and the fifth figure A to fifth figure J is a simplified manufacturing flowchart of the SOI wafer structure. Generally speaking, the entire manufacturing method process starts with the processing of the first wafer, and then the first wafer is flipped and connected to another second wafer used as a ground layer through a wafer bonding method. . The fifth graph A to the fifth graph Η focus on the processing of the first wafer. The fifth figure A is an ion implant—a layer of hydrogen ions—on the first surface 110 of the first wafer at a third predetermined setting depth, and the third predetermined setting depth of the first wafer The plane (forming a lattice-damaged silicon lattice layer) is the predetermined cutting plane 1 12 of the first wafer after the first surface 1 10 of the first wafer is bonded to the second wafer. The third predetermined setting depth (that is, the depth of the predetermined cutting plane 1 12) is determined by the energy of an implanted hydrogen ion beam. The fifth figure B is to set at least one pair of alignment marks at a first predetermined position of the element layer of the first wafer. The alignment marks are set to facilitate the alignment of the stepper and its photomask later, so that / A deep trench and a silicon material region surrounding the inner side can be etched at a second predetermined position of the first wafer and an inner side surrounding the second predetermined position, respectively. The fifth figure C discloses that a deep trench having a first predetermined set depth D 1 1 is etched at a second predetermined position. Afterwards, a thin film of gasified fossils is filled into the first surface 110 and the deep trench, as shown in FIG. 5D. After this second

200418181 V. Description of the invention (14) A silicon material region having a fourth predetermined setting depth 'D 1 2 is etched on the inner side surrounded by the predetermined position, where the fourth predetermined setting depth D1 2 is smaller than the first predetermined setting depth D1 1 (As shown in the fifth figure E). Later, the exposed stone lattice in the inner region of the second predetermined position (oxidized region, pre-formed stone material region) is thermally oxidized to form silicon dioxide by thermal oxidation, and nitrided. The thickness of the silicon film must protect the remaining covered silicon lattice from thermal oxidation. Because the silicon material area expands up and down during the process of thermal oxidation to form silicon dioxide, the deep groove is provided to avoid the so-called bird's beak effect, and the depth of the deep groove etching (the first predetermined setting depth) D 1 1 is more than twice the depth of the inner region etching (fourth predetermined setting depth) D 1 2. As shown in FIG. 5F, it is a schematic diagram after the oxidation region of the silicon dioxide is formed in the second predetermined position (that is, the deep trench) by thermal oxidation. The depth (second predetermined setting depth) D 1 3 of the oxidation zone is smaller than the depth (first predetermined setting depth) D 1 1 of the deep trench.

The fifth figure G shows the steps to fill the remaining space of the deep trench. It is filled on the previous silicon nitride layer. The amorphous silicon oxide layer is an amorphous silicon oxide layer produced by a chemical vapor deposition method. It will also cover the silicon dioxide layer (ie, the oxidized area) generated by thermal oxidation. After that, in addition to filling the deep trench, the excess CVD amorphous silicon oxide layer and nitride nitride film on the first surface 110 must be removed. A commonly used chemical mechanical polishing (CMP) method is used here to planarize and remove these excess CVDs.

Page 18 200418181 V. Oxygen-to-liquid-liquid liquid crystals are crystallized. After the step is completed, the steps are rounded. The same invention is explained. (15) Siliconized silicon and silicon nitride films, as shown in the fifth figure Η. Later, it may be added that the first surface 1 1 0 of the planarized wafer is subjected to a high temperature hydrogen anneal to repair the lattice damage that may have occurred in the previous process, and Hydrofluoric acid (HF) solution or steam is used to remove a small amount of surface oxide layer on the silicon surface of this first wafer. The fifth figure I shows that the first wafer which has been subjected to the step of the fifth figure is turned over, and a wafer bonding method is used to bond with the second circle used as the ground layer. Then, the plane position 1 1 2 (that is, at three predetermined setting depths) of the previously implanted hydrogen atom is cut with a water jet to form an SO I wafer structure as shown in the fifth figure J. Among them, this third preset depth is after dicing, and it is also necessary to use CMP to planarize the diced cutting surface (wafer surface), or perform a secondary high-temperature hydrogen tempering operation. If the second wafer is on the surface of the second wafer before bonding, a thermal oxidation step is performed to generate an oxide layer of the thermal silicon oxide material, or a conductive metal system is formed on the surface, and then the first wafer is bonded to the first wafer. Bonding can also obtain the same S0 I wafer structure with a double-thickness element layer as described in the third and fourth figures. Compared to the prior art, the S0 I wafer structure of the present invention uses the arrangement of oxidation regions in the crystals to Achieve results for different element layer thicknesses. This different component layer thickness will therefore be applicable to different integrated circuit components, and it is less necessary to accommodate the differences between these circuit components in order to achieve capacity

Page 19 200418181 V. Description of the invention (16) The result of placing circuit elements with different characteristics. In addition, because the wafer order method is used, the SOI wafer structure in the second and fourth figures has a direct ground plane. Relatively speaking, its resistance to electrostatic discharge also increases.

V The above description is only a preferred embodiment of the present invention. Any equal modifications and changes made in accordance with the scope of the patent application of the present invention shall fall within the scope of the patent of the present invention.

Page 20 200418181 Schematic illustration [Simplified illustration] f The first figure is a schematic cross-sectional view of a conventional SOI wafer structure < 3 The second diagram A is a diagram of a SOI wafer structure with a double-thickness element layer according to the present invention Schematic diagram of the first embodiment. The second figure B is the top view of the first wafer in the second figure A after the fabrication is completed. The second figure C is another implementation mode in the second figure A. The third figure A is an unintended view of the second embodiment of the SOI wafer structure of the present invention. The second figure B is another embodiment of the third figure A. The fourth diagram A is a schematic diagram of a third embodiment of the SOI wafer structure of the present invention. The fourth diagram B is another embodiment of the fourth diagram A. The fifth graph A to the fifth graph J are the simplified manufacturing process diagrams of the SOI crystal moon structure of the present invention. Symbols shown in the figure: 50 80 Λ 90 S 0 I Wafer structure 60, 81 91 First wafer (--part before wafer cutting) 61 82, 92 Second wafer 62 Λ 83 Λ 93 Element layer 64 Λ 84 Λ 94 Deep groove 65 Λ 85 Λ 95 Oxidation zone 67 86 98 Alignment mark

Page 21 200418181 Brief description of the diagram 87 Second wafer oxide layer 9 6 Metal system (ground layer) 88 > 97 Silicon layer 99 SOI element 101 conductive plug, 1 0 2 Insulating layer 1 1 0 1 surface 1 1 2 cutting plane (68 H 89 bu 892 surface and lower surface) predetermined setting depth) 103, 104 first round upper and lower surface (outside

Page 22

Claims (1)

200418181 VI. Application Patent Scope 1. A dual-thickness active (device layer) SOI (silicon on insulator) wafer structure, including: an element layer; at least >, oxidation regions, each of which is oxidized The region is arranged in a predetermined position of the element layer; at least one deep trench surrounds the oxidation region, and the depth of the deep trench is greater than that of the oxidation region; and a ground layer and the element layer and the oxidation region connection. 2. For the SO I wafer structure of the first patent application scope, wherein the element layer, the oxidized area and the deep trench are formed after processing a first wafer, the ground layer belongs to a second wafer, and the first A wafer and the second wafer are connected in a wafer bonding manner. 3. If the SO I wafer structure of the first scope of the patent application, the grounding layer is a single crystal silicon layer. 4. If the SO I wafer structure of the first scope of the patent application, Deep trenches are filled with silicon dioxide. 5. The SO I wafer structure according to item 4 of the patent application, wherein the silicon dioxide is produced by a chemical vapor deposition (CVD) method. Page 23 200418181 6. Scope of patent application t 6. For the SO I wafer structure of the scope of patent application item 4, wherein the deep trench is previously deposited with a silicon nitride film before being filled into the silicon dioxide. 7. The SO I wafer structure according to item 1 of the patent application scope, wherein the oxidation region is formed by a thermal oxides. 8. If the SO I wafer structure of the first patent application scope includes at least one pair of alignment marks arranged in the element layer of the first wafer, that is, in the wafer surface. 9. The SO I wafer structure according to item 1 of the patent application, wherein the width of the deep trench is 0.2 to 5 micrometers, and the depth of the deep trench is 0.1 to 10 micrometers. 10. According to the SOI wafer structure of the first scope of the patent application, the depth of the deep groove is set on the upper and lower surfaces of the first wafer after dicing, that is, the wafer surface (wafer cutting surface). It is bonded to the wafer. 1 1. A SOI wafer structure having a double-thickness element layer, comprising: an element layer; at least one oxidized region, each of which is disposed in a predetermined position of the element layer; at least one deep trench surrounding the oxidized region The setting depth of the deep trench is greater than the setting depth of the oxidation zone; Page 24 200418181 6. Scope of patent application: a ground layer; and ’an oxide layer is located on the ground layer, and is directly connected to the element layer and the oxide region above the oxide layer. 1 2. According to the SOI wafer structure of the 11th patent application scope, wherein the element layer, the oxidized area and the deep trench are formed after processing a first wafer, the ground layer and the oxide layer belong to a first Two wafers, the first wafer and the second wafer are connected in a wafer bonding manner. 1 3. The SO I wafer structure according to item 11 of the patent application scope, wherein the deep trench is filled with silicon dioxide. 14. The SO I wafer structure according to item 13 of the patent application scope, wherein the silicon dioxide is produced by a chemical vapor deposition method. 15. The SO I wafer structure according to item 13 of the patent application scope, wherein the deep trench is pre-deposited with a silicon nitride film before being filled with the silicon dioxide. 16. The SO I wafer structure according to item 11 of the patent application scope, wherein the oxidation region is formed by a thermally oxidized stone. 1 7. The SO I wafer structure according to item 11 of the patent application scope, wherein the ground layer is a single crystal; a delta layer. Page 25 200418181 6. Scope of patent application 1 8. The SOI wafer structure according to item 11 of the patent application scope, wherein the oxide layer located above the ground layer is a thermal silicon oxide. 19. The SO I wafer structure according to item 11 of the patent application scope, further comprising at least a pair of alignment marks, which are arranged in the element layer of the first wafer, that is, in the wafer surface. 20. The SO I wafer structure according to item 11 of the patent application scope, wherein the width of the deep trench is 0.2 to 5 microns, and the depth of the deep trench is 0.1 to 10 microns. 2 1. The SO I wafer structure according to item 11 of the scope of patent application, wherein the depth of the deep trench is set on the upper and lower surfaces of the first wafer after dicing, that is, the wafer surface (wafer cutting surface) ) Interface with the wafer. 2 2 · A SOI wafer structure with a double-thickness element layer, comprising: an element layer; at least one oxidized region, each of which is disposed at a predetermined position of the element layer; at least one deep trench surrounds the In the oxidized region, the depth of the deep trench is greater than the depth of the oxidized region; a ground layer; and a metal layer located on the ground layer and directly connected to the element layer and the oxidized region above the metal layer. Page 26, 200418181 VI. Patent application scope 2 3. For the SOI wafer structure of the 22nd patent application scope, wherein the element 'layer, the oxidized area and the deep trench are formed after processing a first wafer, The ground layer and the metal layer belong to a second wafer, and the first wafer and the second wafer are connected in a wafer bonding manner. The structure of the layer is gold, and the structure is 0 sheet crystals m) Ie otss sy item 1 2a 2 t Section me perimeter c Fan Tongli is exclusive, please apply for Jinshenyi as 25. If you apply for SO in item 22 of the patent scope The I-wafer structure further includes at least one pair of alignment marks, which are disposed in the element layer of the first wafer, that is, within the wafer surface. 26. The SO I wafer structure according to item 22 of the patent application scope, wherein the width of the deep trench is 0.2 to 5 microns, and the depth of the deep trench is 0.1 to 10 microns. 2 7. The SO I wafer structure according to item 22 of the patent application scope, wherein the deep trench is filled with a dioxide of oxidant. 2 8. The SO I wafer structure according to item 27 of the patent application scope, wherein the dioxide is generated by a chemical vapor deposition method. 29. The SOI wafer structure according to item 27 of the patent application scope, wherein the deep trench is previously deposited with a silicon nitride film before being filled with the silicon dioxide. Page 27 200418181 VI. Application scope of patent 30. For example, the SOI wafer structure of item 22 of the scope of patent application, in which the oxidation is formed by a thermally oxidized stone. 3 1. The SO I chip structure according to item 22 of the patent application scope, wherein the ground layer is a single, crystalline silicon layer. 3 2. The SO I wafer structure according to item 22 of the scope of the patent application, wherein the depth of the deep groove is set on the upper and lower surfaces of the first wafer after dicing, that is, the wafer surface (wafer cutting surface) It is bonded to the wafer. 3 3. A simplified manufacturing method of a SOI wafer structure with a double-thickness element layer, including the following steps: providing a first wafer; setting at least one pair of alignments at a first predetermined position of the first wafer Marking at least a deep trench having a first predetermined set depth at a second predetermined position of the first wafer; depositing a silicon nitride film on the deep trench; The first wafer is etched on the inside of the second predetermined position with a silicon material region of a fourth predetermined setting depth, wherein the fourth predetermined setting depth is smaller than the first predetermined setting depth; An oxidation region of a second predetermined set depth of the silicon oxide material is formed inside the predetermined position by thermal oxidation, wherein the second predetermined set depth is smaller than the first predetermined set depth. Page 28 200418181 Six patent application scopes; 'Deposit an amorphous silicon oxides on the deep trench by a chemical vapor deposition method; Provide a second wafer and flip the first wafer, while using a Wafer bonding connects the first wafer to the second wafer; and cuts at a third predetermined set depth (sp 1 it) The first circle after the inversion is defined, which defines the The area outside the deep trench and the oxidized area of the first wafer is an element layer of the first wafer, and the element layer is used to lay out at least one integrated circuit element. 3. The method according to item 33 of the scope of patent application, further comprising a step of implanting a layer of hydrogen ions on the first wafer to form a lattice-stressed silicon layer, wherein the The depth position of the implantation plane of the hydrogen ions is located at a third predetermined set depth at which the first wafer is cut. 3 5. The method according to item 33 of the scope of patent application, wherein before bonding with the first wafer, an oxide layer of thermal silicon oxide is additionally disposed on the second wafer, so that the oxide layer and the first crystal The round oxidized area is connected to the element layer. 3 6. The method according to item 33 of the scope of patent application, wherein the method is connected to the first wafer. Page 29 Department. The internal standard surface of the internal standard surface should be equal to or equal to the circle. The third round of the element of the Chinese-French square is the third circle of the crystal perimeter and the first one. Please apply in the application such as 200418181. 6. Apply for a patent Before the range is combined, a metal layer of a multi-layer metal composite is further provided on the second wafer, so that the metal layer is connected to the oxidation region of the first wafer and the element layer. 38. The method according to item 33 of the scope of patent application, wherein the step of etching at least one deep groove at the second predetermined position is to set the deep groove system to surround the oxidation region. 39. The method according to item 33 of the scope of patent application, after the step of cutting the first wafer after the flip, further includes a step of planarizing the chemical mechanical polishing (CMP) process. The first wafer is along a cut surface of the third predetermined setting depth. 40. According to the method of claim 39 in the scope of patent application, after the cutting surface grinding step is completed, it further comprises a step of subjecting the wafer surface that has been planarized to a high temperature hydrogen anneal ° 4 1. The method according to item 33 of the scope of patent application, after the step of depositing an amorphous silicon oxide on the deep trench by a chemical vapor deposition method, further comprising Page 30 200418181 6. Scope of patent application There is a step of planarizing the deep 'grooves, oxidized areas and element layer surfaces of the first wafer by a chemical mechanical polishing method.