TW200418109A - Epitaxy structure and manufacturing method of GaN-based compound semiconductor - Google Patents

Epitaxy structure and manufacturing method of GaN-based compound semiconductor Download PDF

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TW200418109A
TW200418109A TW92104899A TW92104899A TW200418109A TW 200418109 A TW200418109 A TW 200418109A TW 92104899 A TW92104899 A TW 92104899A TW 92104899 A TW92104899 A TW 92104899A TW 200418109 A TW200418109 A TW 200418109A
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buffer layer
temperature
boron phosphide
substrate
compound semiconductor
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TW92104899A
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TWI306633B (en
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Mu-Ren Lai
jia-cheng Liu
Jiung-Yu Jang
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Vtera Technology Inc
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Abstract

An epitaxy structure and manufacturing method of GaN series compound semiconductor are disclosed. After a single crystal boron phosphide buffer layer is epitaxially formed on the substrate, a III-group nitride buffer layer is formed on the boron phosphide buffer layer in low temperate environment. Then a high temperature grown III-group nitride buffer layer is formed on the low temperature III-group nitride buffer layer. Hence, a simple process and low cost buffer layer structure is provided to let the following epi-layer have a more perfect crystal structure, and to effectively achieve the intended effects such as increasing the device light emitting efficiency, light intensity and operation life.

Description

200418109 五、發明說明(1) 【發明所屬之技術領域】 本發明係有關一種半導體結構及製程,特別是藉由在 單晶磷化硼緩衝層上形成低溫及高溫I I I族—氮化物緩衝層 ,以提供氮化鎵系化合物半導體於後續磊晶時,產生較完 美之晶格匹配結構。 【先前技術】 按,氮化鎵系(GaN-based)化合物半導體材料用於製 作發光二極體(LED)、雷射二極體(LD)、高頻/高功率電晶 體及光债測器等元件。其中,發光二極體可發出藍、綠、 超紫和白光,由於LED具備省電、壽命長且安全性高等優 點’已被廣泛應用在照明設備方面。 誌,則以氡化鎵或第三族-氮化物為材料的二極體常利 :ί ί ί為基板,同時在基板上先成長-緩衝層,以降 Mitm 二族—氮化物的晶格常數不匹配程度(Latt ice 氮化鎵半導髀-曰曰古 間V曰格匹配程度係為影響 素,ϋ I 甘兀件之壳度、使用壽命等性能表現的關鍵因 不斷研於f板上先長緩衝層以克服磊晶問題的技術一直 美國專㈣6,475,882 B1;然而,在其緩 導致成具=戍長之磊晶層的晶格匹配程度仍然不夠完美, i i r成之氮化鎵元件的性能表現仍然不佳。讀 ^知技藝中,已有使用矽基 技術,JL在加 签攸木成長虱化鎵磊晶之 丁”係因矽基板具有成本低 獨特材料牿念A 並可將亂化鎵的 矽基板同揭★ 土的牛等體技術,然使用 7亦面臨晶格匹配程度之問題,有鑑於此,已有200418109 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a semiconductor structure and process, especially by forming a low-temperature and high-temperature Group III-nitride buffer layer on a single-crystal boron phosphide buffer layer, In order to provide a gallium nitride-based compound semiconductor during subsequent epitaxy, a more perfect lattice matching structure is generated. [Previous technology] According to GaN-based compound semiconductor materials used to make light-emitting diodes (LED), laser diodes (LD), high-frequency / high-power transistors and optical debt detectors And other components. Among them, light-emitting diodes can emit blue, green, ultra-violet, and white light, and LEDs have been widely used in lighting equipment because of their advantages such as power saving, long life, and high safety. Chi, using a gallium halide or a Group III-nitride as the material, Changli: ί ί as the substrate, and at the same time, a buffer layer is first grown on the substrate to reduce the lattice constant of the Mimt Group II-nitride. The degree of mismatch (Latt ice gallium nitride semiconducting 髀-古 古 间 间 V 格 匹配 素 匹配 匹配 匹配 匹配 匹配 匹配 匹配 匹配 曰 曰 程度 程度 程度 程度 程度 程度 程度 程度 程度 程度 程度 程度 程度 程度 程度 程度 程度 程度 匹配 The degree of matching is an influencing factor, the key factors of performance such as shell degree, service life, etc. are continuously researched on The technology of long buffer layer to overcome the epitaxial problem has been US-specific 6,475,882 B1; however, the degree of lattice matching of the epitaxial layer with a long length is still not perfect. The performance is still not good. In the reading technology, silicon-based technology has been used. JL is signing a lot of gallium epitaxial crystals. Because the silicon substrate has a low cost and unique materials, it can miss A and can mess up. The silicon substrate of gallium carbide is also revealed. However, the use of 7 also faces the problem of the degree of lattice matching. In view of this, there have been

第5頁 200418109 五、發明說明(2) 研究如美國專利第6 0 6 9 0 2 1號,其藉由磷化硼緩衝層來降 低矽基板與於磷化硼緩衝層上高溫產生之氮化鎵系磊晶層 (如束缚層及發光層)之晶格匹配結構。然而,事實上,上 述氮化鎵系磊晶層之晶格常數為4 · 5 1埃(A ),而磷化硼緩 衝層之晶格常數為4 · 5 3 8埃,二者之晶格匹配不但仍有差 異外,且氮化鎵系磊晶層於高溫下直接成長於上述二磷化 棚緩衝層表面上,仍會產生不明之線缺陷(1 i n e d e f e c t) ϊ目參。 有鑑於此,本發明係針對上述之困擾’ It由在皁晶填 化硼緩衝層上先行提供低溫之I I I族-氮化物緩衝層,接續_ 於相同製程中,形成高溫之I I I族-氮化物緩衝層,以提供 氮化鎵系化合物半導體於後續磊晶時,產生較完美之晶格 匹配結構。 【發明内容】 本發明之目的一,係在提供一種氮化鎵系化合物半導 體之磊晶結構及其製作方法,其係在同一製程中,利用低 溫與高溫的條件下成長氮化鎵系緩衝層,其不但與基板間 之晶格匹配度極佳,且可使後續之磊晶層具有較完美晶體 結構,以克服習知磊晶層之晶格匹配度差之問題。 本發明之目的二,藉由在矽或碳化矽基板上形成低Θ 與高溫條件下成長的氮化鎵系緩衝層,使氮化鎵系化合物 半導體元件具有極佳之晶體結構,且同時達成提昇元件發 光效率、亮度與使用壽命等效能之最終目的。 本發明之目的三,係藉由在矽或碳化矽基板,有別於Page 5 200418109 V. Description of the invention (2) Research such as US Patent No. 6 69 0 21, which uses a boron phosphide buffer layer to reduce the nitridation of silicon substrate and high temperature generated on the boron phosphide buffer layer. Lattice matching structure of a gallium-based epitaxial layer (such as a tie layer and a light emitting layer). However, in fact, the lattice constant of the above-mentioned gallium nitride-based epitaxial layer is 4.51 Angstrom (A), while the lattice constant of the boron phosphide buffer layer is 4.55 3.8 Angstrom. Not only is there a difference in matching, but also the gallium nitride-based epitaxial layer grows directly on the surface of the buffer layer of the above-mentioned diphosphide shed at high temperature, and still produces 1 inedefect. In view of this, the present invention addresses the above-mentioned problems. It consists of firstly providing a low-temperature group III-nitride buffer layer on the soap crystal-filled boron buffer layer, and then continuing to form a high-temperature group III-nitride in the same process. The buffer layer is used to provide a gallium nitride-based compound semiconductor to produce a perfect lattice matching structure during subsequent epitaxy. [Summary of the Invention] The first object of the present invention is to provide an epitaxial structure of a gallium nitride compound semiconductor and a manufacturing method thereof. The epitaxial structure of the gallium nitride compound semiconductor is grown under the conditions of low temperature and high temperature in the same process. It not only has excellent lattice matching with the substrate, but also enables subsequent epitaxial layers to have a more perfect crystal structure to overcome the problem of poor lattice matching of conventional epitaxial layers. The second object of the present invention is to form a gallium nitride-based buffer layer that grows under low Θ and high temperature conditions on a silicon or silicon carbide substrate, so that the gallium nitride-based compound semiconductor device has an excellent crystal structure and achieves improvement at the same time. The ultimate purpose of the device's luminous efficiency, brightness and service life. The third object of the present invention is that it is different from a silicon or silicon carbide substrate by

200418109 五、發明說明(3) 習知藍寶石基板之前提下,提供一種氮化鎵系化合物半導 體之磊晶缓衝層結構及製作方法,此舉,可具有成本低廉 之優點。 為達到上述之目的 衝層於一基板上,而後 化硼緩衝層上,且第一 成,接著在高溫下形成 且該第二緩衝層亦為I I 根據本發明,上述 衝層例如為早晶結構’ 之低溫磷化硼緩衝層及 高溫磷化硼緩衝層;上 2 0 0 °C至8 0 0 °C之間,上 8 0 0 °C 至 11 0 0 °C 之間。 根據本發明,上述 如為AlxInyGazN,其中〇 。上述第一緩衝層及第 中 0 Sx $1,〇 底下藉由具體實施 容易瞭解本發明之目的 效。 【實施方式】 第一圖至第五圖係 導體的磊晶結構剖視圖 ’奉發 在低溫 緩衝層 一第二 I族-氮 基板例 包括一 一在溫 述第一 述第二 —,▼〜 ^ Ίυ 下形成一第一緩衝層於該碟 由I I I族-氮化物之材料所組 緩衝層於該第一緩衝層上, 化物之材料所構成者。 如為單晶矽,上述磷化硼緩 在溫度30(TC至85(rc 丁形' 度80 0 t至ll00t下形成之’ 緩衝層之形成溫度例如介於 緩衝層之形成溫度例如介於 第一緩衝層及第二緩衝層例 二緩衝層之材料係為丨 Z 1 。么$1,x+y + z = 1。x ’zP ’其 例配合所附的圖式詳加說明,未 、技術内容、特點及其所達成:条 為本發明於製作氮化鎵系化 ,請先參閲第五圖所 :物半 馮本發明200418109 V. Description of the invention (3) Before the sapphire substrate is known, an epitaxial buffer layer structure and a manufacturing method of a gallium nitride compound semiconductor are provided, which may have the advantage of low cost. In order to achieve the above purpose, a layer is punched on a substrate, and then a boron buffer layer is formed, and the first component is formed at a high temperature and the second buffer layer is also II. According to the present invention, the above-mentioned punch layer is, for example, an early-crystal structure. 'Low-temperature boron phosphide buffer layer and high-temperature boron phosphide buffer layer; between 200 ° C and 800 ° C, between 800 ° C and 1100 ° C. According to the present invention, the above is AlxInyGazN, where 0. The purpose and effect of the present invention can be easily understood by implementing the first buffer layer and the middle 0 Sx $ 1,0 below. [Embodiment] Sectional views of the epitaxial structure of the conductors in the first to fifth series are shown in the example of a second group I-nitrogen substrate in a low-temperature buffer layer, including one in the first and second in the description— ▼▼ ^ A first buffer layer is formed under Ίυ. The disc is made of a group III-nitride material buffer layer on the first buffer layer. In the case of single crystal silicon, the formation temperature of the buffer layer formed by the above boron phosphide at a temperature of 30 (TC to 85 (rc T-shaped 'degree 80 0 t to l00t) is, for example, between the formation temperature of the buffer layer, such as between A buffer layer and a second buffer layer. Example 2 The material of the buffer layer is Z1. Modular $ 1, x + y + z = 1. x 'zP' This example is described in detail with the accompanying drawings. Contents, characteristics and achievement: The article refers to the invention in the production of gallium nitride, please refer to the fifth figure: the invention

第7頁 200418109 揭露之氮化 在基板1 0上 溫麟化爛緩 I族-氮化物 Π I族-氮化 體結構後, 請參閱第一 一基板1 0, 可先以適當 板1 0加熱至 用鹵化物氣 ,在基板1 〇 結構的低溫 上於高溫下 此南溫條件 早晶結構。 五、發明說明(4) 之結構示意圖,本發明 晶結構包括一基板1 〇, 硼(BP)缓衝層12及一高 緩衝層14上形成有一 π 一緩衝層16上形成有一 在了解本發明之整 各層結構及製作方法, ,如第一圖所示,提供 或碳化矽基板。基板1 〇 於氫氣之氣氛下,將基 二圖及第三圖所示,利 vapor phase epitaxy) 低溫下蟲晶成長一多晶 在低溫磷化硼緩衝層1 2 填化硼緩衝層14,且於 1 2會由多晶結構轉變為 鎵系化合物半導體之磊 依序形成有一低溫磷化 衝層14,在高溫磷化硼 之第一緩衝層16,且第 物之第二緩衝層1 8。 接續詳細說明本發明之 圖至第五圖所示。首先 此基板1 0可為一單晶矽 溶液進行化學清洗,再 約90 0 °C ;接著,如第_ 相蠢晶法(H a 1 i d e 之{100}晶面表面上於 磷化硼緩衝層1 2,接續 形成一單晶結構的高溫 下,低溫磷化硼緩衝層 其中,該齒化物氣相磊晶法係以氫氣作為載氣( Carrier gas),且以氯化硼(BCl3)及氯化磷(pci3)或氯化 棚(BCI3)及磷化氫(PH3)作為前驅物來進行反應,而低溫i 化侧緩衝層12係在溫度約30 0 °C至8 50 °C下長成,較佳者# 380 C ’其厚度約400奈米(nm)左右;高溫鱗化侧緩衝層14 係在溫度約800 °C至1100 °C下形成,較佳者為1 030 °C,形 成之厚度約4560nm。 而後,如第四圖及第五圖所示,利用金屬有機化學氣Page 7 200418109 The exposed nitride on the substrate 10 warms up the decayed Group I-nitride Π I-nitride structure. Please refer to the first substrate 10, which can be heated with an appropriate plate 10 first. Even with a halide gas, the structure of the substrate 10 has a low-temperature and early-temperature early-crystal structure at a low temperature under a high temperature. V. Explanation of the structure of the invention (4). The crystal structure of the present invention includes a substrate 10, a boron (BP) buffer layer 12 and a high buffer layer 14 formed with a π, and a buffer layer 16 formed with the present invention. The entire layer structure and manufacturing method, as shown in the first figure, provide or silicon carbide substrate. Under the atmosphere of hydrogen, the substrate 10 is shown in the second and third figures, and vapor phase epitaxy) is grown at a low temperature. A polycrystal is grown at a low temperature. The boron phosphide buffer layer 1 2 is filled with a boron buffer layer 14 and At 12, a polycrystalline structure is transformed into a gallium-based compound semiconductor, and a low-temperature phosphating layer 14 is formed in sequence, a first buffer layer 16 of boron phosphide at a high temperature, and a second buffer layer 18 of the first material. The detailed description of the present invention is shown in the fifth to fifth figures. First, the substrate 10 can be chemically cleaned by a single-crystal silicon solution, and then about 90 0 ° C; then, as described in the _ phase stupid method (H a 1 ide {100} crystal plane surface buffered on boron phosphide) Layer 12 successively forms a single crystal structure at high temperature and low temperature boron phosphide buffer layer. Among them, the dentate vapor phase epitaxy method uses hydrogen as a carrier gas, and boron chloride (BCl3) and Phosphorus chloride (pci3) or chlorinated shed (BCI3) and phosphine (PH3) are used as precursors to perform the reaction, and the low-temperature buffering layer 12 is grown at a temperature of about 30 0 ° C to 8 50 ° C. Cheng, preferably # 380 C 'has a thickness of about 400 nanometers (nm); the high-temperature scaled side buffer layer 14 is formed at a temperature of about 800 ° C to 1100 ° C, preferably 1 030 ° C, The formed thickness is about 4560 nm. Then, as shown in the fourth and fifth figures, metal organic chemical gas is used.

第8頁 200418109 五、發明說明(5)Page 8 200418109 V. Description of the invention (5)

相沈積法(Metal-organ chemical vapor deposition, MOCVD) ’在高溫填化蝴緩衝層14上依序形成一第一緩衝層 1 6及一第二緩衝層1 8,第一緩衝層丨6係在低溫下形成,其 蠢晶溫度可在2 0 0 °C至8 0 0 °C之間,較佳者為4 5 〇 °C至6 0 0 °C ;而位於第一緩衝層1 6上之第二緩衝層丨8係在高溫下形成 ’其蟲晶溫度係在80 0 °C至1100 t:之間較佳者係為8〇〇 t左 右。上述第一緩衝層1 6及第二緩衝層丨8之材料組成係由 I II族-氮化物所構成,且第一緩衝層16及第二緩衝層18之 材料係同為AlxInyGazN或同為InxGayNzP,其中〇 $1,〇 SySl,0$z$l,x + y + z = l。 其中’第一緩衝層16及第二緩衝層is因應不同ΠΙ - V 族化合物半導體之材料組成’其利用Mqcvd法形成磊晶之 前軀物通常/系選自曱基聯胺(mon〇methyl hydrazine,mmh )、二曱基鎵(t r i me thy 1 ga 11 i um,TMG)、三曱基!呂( trimethy aluminum ;TMA1)、三甲基銦(trimethy indium ; TM In)及NH3所組成之群組的其中之一者,至於如 何以M0CVD法將該些前軀物進行反應,則為熟習此項技藝 者所熟知的,故於此不贅述。 •由於本發明之基板材質為矽,其係為鑽石結構( Diamond structure),矽之晶格常數為 5.431埃(^,而 化硼為閃鋅礦結構(Zinc blende structure),其與鑽石 結構具有相同之晶格排列結構,且磷化硼之晶格、常數為 4. 538埃,因此磷化硼層與矽基板的晶格不匹配度約為a% ’與習知晶格不匹配度比較起來,係為一極低者,故可使 200418109 五、發明說明(6) 後續之磊晶層具有較完美之晶體結構。 因此,本發明利用先在基板上成長一磷化硼緩衝層, 使其先與基板間有最佳之晶格匹配度,再利用於同一製程 中,以低溫及高溫之條件下依序成長二氮化鎵系緩衝層, 使其與磷化硼緩衝層亦具有最佳之晶格匹配度。故本發明 在有別於習知藍寶石基板之前提下,不但具有成本低廉之 優點,且同時使後續之磊晶層可具有較完美之晶格結構, 進而達成提昇元件發光效率、亮度與使用壽命等效能之最 終目的。 以上所述係藉由實施例說明本發明之特點,其目的在φ 使熟習該技術者能暸解本發明之内容並據以實施,而非限 定本發明之專利範圍,故,凡其他未脫離本發明所揭示之 精神所完成之等效修飾或修改,仍應包含在以下所述之申 請專利範圍中。 【圖號簡單說明】 10基板 1 2低溫磷化硼緩衝層 1 4高溫磷化硼緩衝層 1 6第一緩衝層 1 8第二緩衝層 _Phase-deposition method (Metal-organ chemical vapor deposition (MOCVD)) A first buffer layer 16 and a second buffer layer 18 are sequentially formed on the high-temperature filled butterfly buffer layer 14. The first buffer layer 6 is It is formed at a low temperature, and its stupid crystal temperature may be between 200 ° C and 800 ° C, preferably between 450 ° C and 600 ° C; and on the first buffer layer 16 The second buffer layer 丨 8 is formed at a high temperature, and its worm crystal temperature is between 80 0 ° C and 1100 t: the better is about 800 t. The material composition of the first buffer layer 16 and the second buffer layer 8 described above is composed of group I II-nitride, and the materials of the first buffer layer 16 and the second buffer layer 18 are the same as AlxInyGazN or the same as InxGayNzP. Where 〇 $ 1, 〇SySl, 0 $ z $ l, x + y + z = l. Among them, 'the first buffer layer 16 and the second buffer layer is based on the material composition of different III-V compound semiconductors', and the body before or after the epitaxial formation by the Mqcvd method is usually / selected from monomethylhydrazine, mmh), tri methy 1 ga 11 i um (TMG), trifluorene! One of the groups consisting of trimethy aluminum (TMA1), trimethy indium (TMIn), and NH3. As for how to react these precursors by MOCVD method, it is familiar with this. The items are well-known to the artist, so I will not repeat them here. • Since the substrate material of the present invention is silicon, it is a diamond structure, and the lattice constant of silicon is 5.431 angstroms (^, and boron chloride is a zinc blend structure), which has the same structure as the diamond structure. The same lattice arrangement structure, and the constant of the lattice of boron phosphide is 4. 538 angstroms, so the lattice mismatch between the boron phosphide layer and the silicon substrate is about a% 'compared with the conventional lattice mismatch, It is a very low one, so 200418109 V. Description of the invention (6) The subsequent epitaxial layer has a more perfect crystal structure. Therefore, the present invention uses a boron phosphide buffer layer to be grown on the substrate first, so that it It has the best lattice matching degree with the substrate. It is reused in the same process, and the gallium nitride buffer layer is grown sequentially under low and high temperature conditions, so that it has the best balance with the boron phosphide buffer layer. Lattice matching degree. Therefore, the present invention is not only different from the conventional sapphire substrate, but also has the advantage of low cost. At the same time, the subsequent epitaxial layer can have a more perfect lattice structure, thereby achieving the improvement of the luminous efficiency of the device. ,brightness The ultimate purpose of performance such as service life. The above description is to explain the characteristics of the present invention through the examples, and its purpose is to enable those skilled in the art to understand and implement the content of the present invention, rather than to limit the patent scope of the present invention. Therefore, all other equivalent modifications or modifications made without departing from the spirit disclosed by the present invention should still be included in the scope of patent application described below. [Simplified description of drawing number] 10 substrate 1 2 low-temperature boron phosphide buffer Layer 1 4 High temperature boron phosphide buffer layer 16 First buffer layer 1 8 Second buffer layer _

第10頁 200418109Page 10 200418109

Claims (1)

200418109 六、申請專利範圍 1 · 一種氮化鎵系化合物半導體磊晶結構,包括: 一基板; 一單晶結構之磷化硼緩衝層,位於該基板上; 一第一緩衝層,係在溫度2 0 0°C至8 0 0°C之低溫下形成 於該磷化硼緩衝層上,且該第一緩衝層由I I I族-氮 化物之材料所組成;以及 一第二緩衝層,係在溫度8 0 0°C至1 1 0 0°C之高溫下形 成於該第一緩衝層上,且該第二缓衝層係由I I I族-氮化物之材料所組成。 2 ·如申請專利範圍第1項所述之氮化鎵系化合物半導體· 磊晶結構,其中,該基板係由單晶矽所構成。 3 ·如申請專利範圍第1項所述之氮化鎵系化合物半導體 磊晶結構,其中,該磷化硼緩衝層係包括一在溫度 3 0 0°C至8 5 0°C下形成之低溫磷化硼緩衝層及一在溫度 8 0 0°C至1 1 0 0°C下形成之高溫磷化硼緩衝層。 4 ·如申請專利範圍第1項所述之氮化鎵系化合物半導體 磊晶結構,其中,該第一緩衝層及該第二緩衝層之材 料係為 A1 XI n yGa ZN,其中 OS 1, OS 1, OS 1, x + y+ z二 1 o 5 ·如申請專利範圍第1項所述之氮化鎵系化合物半導體· 磊晶結構,其中,該第一緩衝層及該第二緩衝層之材 料係為 I n XG a yN ZP,其中 OS xS 1, OS 1, 0$ 1, x + y+ z = 1 o 6 · —種氮化鎵系化合物半導體磊晶結構之製作方法,包200418109 6. Scope of patent application 1. A gallium nitride compound semiconductor epitaxial structure, including: a substrate; a single crystal boron phosphide buffer layer on the substrate; a first buffer layer at a temperature of 2 Formed on the boron phosphide buffer layer at a low temperature of 0 0 ° C to 80 ° C, and the first buffer layer is composed of a group III-nitride material; and a second buffer layer is at a temperature The first buffer layer is formed at a high temperature of 80 ° C to 110 ° C, and the second buffer layer is composed of a group III-nitride material. 2. The gallium nitride-based compound semiconductor according to item 1 of the scope of the patent application. The epitaxial structure, wherein the substrate is made of single crystal silicon. 3. The gallium nitride-based compound semiconductor epitaxial structure according to item 1 of the scope of the patent application, wherein the boron phosphide buffer layer includes a low temperature formed at a temperature of 300 ° C to 850 ° C. A boron phosphide buffer layer and a high-temperature boron phosphide buffer layer formed at a temperature of 800 ° C to 110 ° C. 4. The gallium nitride-based compound semiconductor epitaxial structure according to item 1 of the scope of the patent application, wherein the material of the first buffer layer and the second buffer layer is A1 XI n yGa ZN, among which OS 1, OS 1, OS 1, x + y + z 2 1 o 5 · The gallium nitride-based compound semiconductor described in item 1 of the patent application scope · Epitaxial structure, wherein the materials of the first buffer layer and the second buffer layer It is I n XG a yN ZP, in which OS xS 1, OS 1, 0 $ 1, x + y + z = 1 o 6 ·-a method for manufacturing a gallium nitride compound semiconductor epitaxial structure, including 第12頁 200418109 六、申請專利範圍 括下列步驟: 提供一基板; 磊晶形成一單晶結構之磷化硼緩衝層於該基板上; 在溫度2 0 0°C至8 0 0°C之低溫下磊晶形成一第一緩衝層 於該填化硼緩衝層上,且該第一緩衝層係由I I 1族-氮化物之材料所組成;以及 在溫度8 0 0°C至1 1 0 0°C之高溫下磊晶形成一第二緩衝 層於該第一緩衝層上,且該第二緩衝層係由I I 1族-氮化物之材料所組成。 7 ·如申請專利範圍第6項所述之製作方法,其中,該基· 板係由單晶矽所構成。 8 ·如申請專利範圍第6項所述之製作方法,其中,該磷 化硼緩衝層係包括一在溫度3 0 0°C至8 5 0°C下形成之低 溫磷化硼緩衝層於該基板上以及一在溫度8 0 0°C至 1 1 0 0°C下形成之高溫磷化硼緩衝層。 9 ·如申請專利範圍第6項所述之製作方法,其中,該第 一緩衝層及該第二緩衝層之材料係為A 1 XI n yG a ZN,其 中 0$ xH,0$ yS 1,OS zS 1,x + y + z = lo 1 0 ·如申請專利範圍第6項所述之製作方法,其中,該第 一緩衝層及該第二緩衝層之材料係為I n xGa yN ZP,其 · 中 OS xS 1, yS 1, OS zS 1, x+y+z=loPage 12 200418109 6. The scope of patent application includes the following steps: providing a substrate; forming a single crystal boron phosphide buffer layer on the substrate by epitaxy; at a low temperature of 200 ° C to 800 ° C The lower epitaxial layer forms a first buffer layer on the filled boron buffer layer, and the first buffer layer is composed of a material of group II 1-nitride; and the temperature is 8 0 ° C to 1 1 0 0 At a high temperature of ° C, a second buffer layer is formed on the first buffer layer by epitaxy, and the second buffer layer is composed of a Group II 1-nitride material. 7. The manufacturing method according to item 6 of the scope of patent application, wherein the base plate is composed of single crystal silicon. 8. The manufacturing method as described in item 6 of the patent application scope, wherein the boron phosphide buffer layer includes a low-temperature boron phosphide buffer layer formed at a temperature of 300 ° C to 850 ° C. A high-temperature boron phosphide buffer layer formed on the substrate and at a temperature of 800 ° C to 110 ° C. 9 · The manufacturing method as described in item 6 of the scope of the patent application, wherein the material of the first buffer layer and the second buffer layer is A 1 XI n yG a ZN, where 0 $ xH, 0 $ yS 1, OS zS 1, x + y + z = lo 1 0 · The manufacturing method as described in item 6 of the scope of patent application, wherein the material of the first buffer layer and the second buffer layer is I n xGa yN ZP, Among them: OS xS 1, yS 1, OS zS 1, x + y + z = lo 第13頁Page 13
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