200414672 玖、發明說明： 【發明所屬之技術領域】 本發明係關於一種用於低壓差動信號（LVDS)接收機電路 之輸入級。更明確地，本發明係關於該接收機電路之比較 器。更明確地，本發明係關於在該輸入級進行位準偏移之 高速比較器。 【先前技術】 目前所用之大多數電子裝置係由許多不同積體電路組 成。由於積體電路之半導體元件尺寸之減小，這些電子裝 置中之積體電路變得越來越密集。半導體元件尺寸之減小 為不需要在比較大之功率或電流下運作之快速裝置奠定了 基礎。例如，許多常規半導體元件常常需要在3 3伏電源下 運作。然而，其他半導體元件，像電晶體需要在大約1.2伏 义電源下運作。採用對功率要求較低之元件對於諸如膝上 2電腦、行動電話等行動裝置很重要。低功率使得裝置之 包源（如電池）持續時間更長、體積更小。 一問遞是許多裝置仍然將高功率元件之積體電路和低功率 、一牛之％也包路合併在一起。這些裝置將低功率積體電路 ^ 2到问功率積體電路。因此，使用低電壓運作之積體電 路：接收到高電壓輸入。當來自高電壓積體電路之高壓信 她加於低電壓積體電路時，就會引發-項特殊問題。 兩上特殊問碭是低電壓積體電路之薄膜氧化物由於所承受 笔壓向於最大供庠兩 尨兒壓，而可能使氧化物被擊穿。這將使 _ % i Λ m電路之元件遭受到災難性的破壞。 86448 200414672 存在此特殊問題之另一區域是為積體電路提供1/0通訊之 低壓差動信號電路。典型地，低壓差動信號接收機在1.2伏 之笔壓下運作。然而，連接到低壓差動信號接收機之電路 卻可以在3 ·3伏之電壓下運作。 因此’這項技術領域需要一種用於限制施加至電路之信 號電壓之低功率低壓差動信號接收機電路之輸入級。 【發明内容】 根據本發明所設計之低壓差動信號電路之輸入級解決此 項技術中的上述問題和其他問題。根據本發明所設計之輸 入級將低壓電路連接到高壓電路，並阻止來自該高壓電路 之高壓信號施加於低壓電路，以防止損壞低壓電路。 根據本發明，該輸入級按下列方式配置。該輸入級有一 接收輻入仏號之一級式登接電路佈線。該二級式疊接電路 佈、、泉包括一第一輸入電路和一第二輸入電路。該第一輸入 私路接收來自一相連電路之第一輸入信號，該第二電路接 收來自該相連電路之第二輸入信號。一第一電流鏡接收來 ^該二級式疊接電路佈線之第-輸人電路之信號。-第二 迅：釦接收來自该第二輸入電路之信號。該第一電流鏡與 、、第私/瓜叙連接到一通用輸出，以合併該第一輸入電路 、4唬和居第—輸入電路之信號。一個二極體將該等信號 之電壓位準調整至一輸出電壓。 【實施方式】 根據本發明之雪放^ A 、 、 、、，、 各與万法炙上述特徵及其他特徵見以下 詳細說明和圖式。 86448 範圜pi 本1明ι τ範實施例說明之目的並非將本發明之 靶圍限制於衿μ 製作盥倭用：二列’而是希望使任何熟悉此項技術者 ι作與使用本發明。 踗 I月纟發明提供-種低壓差動信號接收機I/O電 由：：入級。該輸入級包括-比較器’用於將所接收信號 位準偏移至低壓位準。更佳地，該位準偏移係，足輸 ,=3.3伏（肩整）到運作電壓12伏，該運作電壓屬於低壓 差動信號接收機電路之運作範圍。 圖表不根據本發明之用於低壓差動信號接收機電路之輸 H00之方塊圖。輸入級1〇〇包括二級式叠接電路佈線 110。該二級式疊接電路佈線11〇接收電壓範圍變化很大之 共模信號。所接收共模信號之範圍以大約0伏i大約3伏為 佳。 、、 二級式疊接電路佈線包括第一輸入電路lu與第二傳入電 路112，該第一輸入電路lu經由路徑1〇5接收來自一輸入之 第一信號，該第二輸入電路112經由路徑1〇4接收來自一輸 入之第二信號。輸入lu和輸入112並聯配置，這樣對電壓 ’交化範圍很大之共模信號比較靈敏，其電壓範圍最好為大 約0伏到大約3伏。該信號經由路徑1〇4與路徑1〇5被接收。 這意味施加於路徑104與路徑1〇5信號之電壓差表示信號 值。第一輸入（電路）111和第二輸入（電路）112之精確配置見 以下對本發明之詳細實施例。 第一輸入111經由路徑113連接到第一電流鏡12〇，第二輸 入112經由路徑114連接到第二電流鏡125。電流鏡12〇和電 86448 200414672 ㈣叙125獒供輻出電流，該輸出電流為該所接收信號與一 系數相乘之I。冑流鏡12〇和電流鏡125之輸出經由路 徑127、路徑126連接到輸出128。 二極體130經由路徑1〇3連接到輸入源並且經由路徑丨31連 接到輻出128。一極體130將輸入之高電壓調整到輸出之期 望低電壓。 二極體140連接於輸出128與接地之間，這防止了 與 Vgs 〇 圖2表示一電路200之電路圖，電路2〇〇包含根據本發明之 電路圖100之元件。在圖！中，二級式疊接電路佈線電路ιι〇 包括一第一輸入111和一第二輸入112。在圖2中，第一輸入 111 (圖1)包含一第一電晶體對：電晶體21〇和電晶體。 較佳地，電晶體210與211係同一類型。就本討論而言，電 晶體之類型表示N通道金屬氧化物半導體電晶體或p通道金 屬氧化物半導體電晶體任一種。更佳地，電晶體21〇和電晶 體2 11是薄閘極電晶體。這允許電晶體在給定增益情況下， 電容較小。第一電晶體210之源極經由路徑2〇1和路徑2〇3連 接到輪入2 9 5。弟一電晶體210之沒極經由路徑2 1 3連接到一 電流鏡。第二電晶體2 11之源極經由路徑2〇 1和路徑204連接 到輸入2 9 5 ’第二電晶體211之沒極經由路徑214連接到一電 流鏡。 在圖2中，第一輸入112 (圖1)包括一第二電晶體對··電晶 體215和電晶體216。較佳地’電晶體215和電晶體216係同 一類型。更佳地，電晶體215、電晶體216之類型和電晶體 86448 200414672 2 1 0、電晶體2 11之類型相反。儘管熟悉此項技術者認可採 用其他配置以允許使用相同類型之電晶體。更佳地，電晶 體21 5和電晶體21 6是薄閘極電晶體。這允許電晶體在給定 增益情況下，電容較小。電晶體21 5之源極經由路徑202和 路徑205連接到輸入295。第一電晶體2 15之汲極經由路徑261 連接到一電流鏡。第二電晶體216之源極經由路徑202和路 徑206連接到輸入295。第二電晶體216之汲極經由路徑264 連接到一電流鏡。電晶體21 5之閘極與電晶體2 16之閘極也 彼此連接。 在圖2二極體1 3 0 (圖1)電路按以下方式配置。第一二極體 290之源極連接到路徑206。第一二極體290之汲極連接到路 徑298，路徑298連接到輸出299。第一二極體290之閘極連 接到控制電路（圖中沒有給出）。第二二極體291之源極經由 路徑207連接到輸入路徑205。第二二極體291之汲極經由路 徑283連接到路徑298，接著路徑298連接到輸出299。第二 二極體291之閘極連接到控制電路（圖中沒有給出）。較佳的， 電晶體290和電晶體291均係薄閘極電晶體。這允許電晶體 在給定增益情況下，電容較小。 在圖2中，第一電流鏡120 (圖1)按以下方式配置。起始於 電晶體203之汲極之路徑213連接到電晶體242之源極。電晶 體242之閘極連接到路徑213、電晶體245之閘極和電晶體240 之閘極。電晶體242之汲極連接到路徑255。路徑255經由路 徑298連接到輸出299。 路徑214連接到電晶體243之源極。電晶體243之閘極連接 86448 -10- 200414672 到路徑214、電晶體246之閘極和電晶體241之閘極。電晶體 243之汲極經由路徑253連接到路徑298。路徑298連接到輸 出 299。 路徑230將電晶體21 〇之汲極連接到電晶體241之源極。電 晶體241之閘極連接到路徑214、電晶體243之閘極和電晶體 246之閘極。電晶體241之沒極經由路徑25 1連接到路徑298。 較佳地，電晶體241係一薄閘極電晶體。這允許電晶體在給 定增益情況下，電容較小。 路徑23 1將電晶體211之汲極連接到電晶體24〇之源極。電 晶體240之閘極連接到路徑213、電晶體242之閘極和電晶體 245之閘極。電晶體240之汲極經由路徑250連接到路徑298。 較佳地，電晶體240是一薄閘極電晶體。這允許電晶體在給 定增益情況下，電容較小。 電晶體245具有一源極，該源極經由路徑232而連接至電 日曰fa 2 1 6之汲極。電晶體245之閘極連接至路徑2丨3以及電晶 體240及242之閘極。電晶體245之汲極經由路徑254而連接 至路徑298。較佳地，電晶體245為一薄閘電晶體。這使得 針對該等電晶體之給定增益而具有較少的電容。 電晶體246之源極經由路徑26卜路徑256連接到電晶體21 5 之沒極。電晶體246之閘極連接至路徑214、電晶體241之閉 極和243之閘極。電晶體246之汲極經由路徑257連接到路徑 298。#父佳地，電晶體246係一薄閘極電晶體。這允許電晶 體在給定增益情況下，電容較小。 在圖2中，第二電流鏡125按以下方式配置。起始於電晶 86448 -11 - 200414672 21 5之汲極之路徑26丨和電晶體1之源極連接。電晶體27 1 之閘極經由路徑273連接到電晶體272之閘極、經由路控 連接到控制電路。電晶體271之汲極經由路徑279連接至路 拴298。較佳地，電晶體27 1係一薄閘極電晶體。這允許電 晶體在給定增益情況下，電容較小。 路t 264將電晶體276之源極連接到電晶體216之汲極。電 晶體276之閘極經由路徑277連接到電晶體275之閘極、經由 路控278連接至控制電路（圖中沒有給出）。電晶體276之汲極 經由路徑281連接到路徑298。較佳地，電晶體276係一薄閘 極電晶體。這允許電晶體在給定增益情況下，電容較小。 路徑262經由路徑261將電晶體275之源極連接到電晶體 2 15之汲極。電晶體275之閘極連接到電晶體276之閘極連接 到控制電路（圖中沒有給出）。電晶體275之汲極經由路徑284 連接到路徑298。較佳地，電晶體275係一薄閘極電晶體。 這允终電晶體在給定增益情況下，電容較小。 路徑263經由路徑264將電晶體272之源極連接到電晶體 2 16之汲極。電晶體272之閘極經由路徑273連接到電晶fl. 271 之閘極，經由路徑274連接到控制電路（圖中沒有示出）。電 晶體272之汲極經由路徑280連接到路徑298。較佳地，電晶 體272是一薄閘極電晶體。這允許電晶體在給定增益情況 下，電容較小。 在圖2中，用於將輸出連接至接地之二極體1 40就是電晶 體2 9 3 ’電晶體2 9 3之源極連接到路徑2 9 8且沒極連接至接 地。電晶體293之閘極連接到控制電路（圖中沒有給出）。較 86448 -12 - 200414672 佳地，電晶晋# ? 〇。π ^ a 3係—薄閘極電晶體。電晶體293阻止電路200 中電晶體之▽心與¥以。 二上所述包括本發明之示例實施例。吾人預期熟悉此項 技術者此夠並很可能設計電路，對列於以下申請專利範圍 内《本♦明構成文意侵權或均等原則下之侵權。 【圖式簡單說明】 、回表丁根據本發明之低壓差動信號接收機電路之輸入級 <比較器之元件方塊圖圖；以及 圖2表示根據本發明之輸入級比較器之電路圖。 【圖式代表符號說明】 103路徑 104路徑 105路徑 11 〇二級式疊接電路佈線 111第一輸入電路 11 5第二輸入電路 116路徑 117路徑 1 21第一電流鏡 125第二電流鏡 128路徑 12 9路徑 128路徑 130二極體 86448 -13- 200414672 1 3 1路徑 140二極體 141路徑 201路徑 202路徑 203路徑 204路徑 205路徑 206路徑 207路徑 208路徑 21 0電晶體 211電晶體 2 1 3路徑 2 14路徑 2 1 5電晶體 2 1 6電晶體 2 17路徑 230路徑 231路徑 232路徑 240電晶體 241電晶體 242電晶體 -14- 86448 200414672 243電晶體 245電晶體 246電晶體 250路徑 251路徑 253路徑 254路徑 255路徑 256路徑 257路徑 261路徑 262路徑 263路徑 264路徑 271電晶體 272電晶體 273路徑 274路徑 275電晶體 276電晶體 277路徑 278路徑 280路徑 281路徑 -15- 86448 200414672 282路徑 283路徑 284路徑 290電晶體 291電晶體 293電晶體 298路徑 299路徑 16- 86448200414672 (1) Description of the invention: [Technical field to which the invention belongs] The present invention relates to an input stage for a low-voltage differential signal (LVDS) receiver circuit. More specifically, the present invention relates to a comparator for the receiver circuit. More specifically, the present invention relates to a high-speed comparator that performs a level shift at the input stage. [Previous Technology] Most electronic devices currently used are composed of many different integrated circuits. Due to the reduction in the size of semiconductor components of integrated circuits, the integrated circuits in these electronic devices have become increasingly dense. The reduction in the size of semiconductor components has laid the foundation for fast devices that do not need to operate at relatively high power or current. For example, many conventional semiconductor components often need to operate on a 33 volt power supply. However, other semiconductor components, such as transistors, need to operate on about 1.2 volts of power. The use of lower power components is important for mobile devices such as laptops and mobile phones. The low power makes the source of the device (such as a battery) longer and smaller. One problem is that many devices still combine the integrated circuits of high-power components and low-power, one-ox-percent. These devices will integrate low power integrated circuits ^ 2 to Q power integrated circuits. Therefore, an integrated circuit operating with a low voltage: a high voltage input is received. When a high-voltage signal from a high-voltage integrated circuit is applied to a low-voltage integrated circuit, a special problem arises. The special problem between the two is that the thin film oxide of the low voltage integrated circuit may be broken down due to the pen pressure to the maximum supply pressure. This will cause catastrophic damage to the components of the _% i Λ m circuit. 86448 200414672 Another area where this special problem exists is the low-voltage differential signal circuit that provides 1/0 communication for integrated circuits. Typically, low-voltage differential signal receivers operate at a 1.2-volt pen pressure. However, circuits connected to low-voltage differential signal receivers can operate at 3.3V. Therefore, this technology field requires an input stage for a low power low voltage differential signal receiver circuit for limiting the signal voltage applied to a circuit. SUMMARY OF THE INVENTION The input stage of a low-voltage differential signal circuit designed according to the present invention solves the above-mentioned problems and other problems in this technology. The input stage designed according to the present invention connects a low-voltage circuit to a high-voltage circuit and prevents high-voltage signals from the high-voltage circuit from being applied to the low-voltage circuit to prevent damage to the low-voltage circuit. According to the invention, the input stage is configured in the following manner. This input stage has a one-stage landing circuit wiring that receives the radiant signal. The two-stage laminated circuit cloth includes a first input circuit and a second input circuit. The first input private circuit receives a first input signal from a connected circuit, and the second circuit receives a second input signal from the connected circuit. A first current mirror receives a signal from the first-input circuit of the two-level laminated circuit wiring. -Second fast: The button receives a signal from the second input circuit. The first current mirror is connected to a common output with the, and the first / second circuit to combine the signals of the first input circuit, the first input circuit, and the first input circuit. A diode adjusts the voltage level of these signals to an output voltage. [Embodiment] According to the present invention, the above features and other features of each of the snow ^ A,,,,,,, and other methods can be found in the detailed description and drawings below. 86448 范 圜 pi The purpose of the description of this embodiment is not to limit the scope of the present invention to the production of toilets: two columns, but to make anyone skilled in the art to make and use the present invention. .踗 纟 月 纟 invention provides a kind of low-voltage differential signal receiver I / O power. The input stage includes a comparator 'for shifting the received signal level to a low voltage level. More preferably, the level shift system is from a foot loss of 3.3 volts (shoulder-to-shoulder) to an operating voltage of 12 volts, which belongs to the operating range of the low voltage differential signal receiver circuit. The diagram is not a block diagram of the input H00 for a low-voltage differential signal receiver circuit according to the present invention. The input stage 100 includes a two-stage stacked circuit wiring 110. The two-level superimposed circuit wiring 11 receives a common-mode signal whose voltage range varies greatly. The range of the received common mode signal is preferably about 0 volts i about 3 volts. The two-level stacked circuit wiring includes a first input circuit lu and a second incoming circuit 112. The first input circuit lu receives a first signal from an input via a path 105, and the second input circuit 112 via Path 104 receives a second signal from an input. The input lu and the input 112 are arranged in parallel, so that they are more sensitive to common mode signals with a wide range of voltages. The voltage range is preferably about 0 volts to about 3 volts. This signal is received via path 104 and path 105. This means that the voltage difference between the signal applied to path 104 and path 105 represents the signal value. For the precise configuration of the first input (circuit) 111 and the second input (circuit) 112, see the detailed embodiment of the present invention below. The first input 111 is connected to the first current mirror 120 via a path 113, and the second input 112 is connected to the second current mirror 125 via a path 114. The current mirror 120 and the electric 86448 200414672 are used to radiate the current, which is the I of the received signal multiplied by a coefficient. The outputs of the galvanometer mirror 120 and the current mirror 125 are connected to an output 128 via a path 127 and a path 126. Diode 130 is connected to the input source via path 103 and to spoke 128 via path 31. The unipolar body 130 adjusts the input high voltage to the output low voltage. The diode 140 is connected between the output 128 and the ground, which prevents Vgs. Figure 2 shows a circuit diagram of a circuit 200, which contains the components of the circuit diagram 100 according to the present invention. In the picture! The two-level stacked circuit wiring circuit includes a first input 111 and a second input 112. In FIG. 2, the first input 111 (FIG. 1) includes a first transistor pair: a transistor 21 and a transistor. Preferably, the transistors 210 and 211 are of the same type. For the purposes of this discussion, the type of transistor means either an N-channel metal oxide semiconductor transistor or a p-channel metal oxide semiconductor transistor. More preferably, transistors 21 and 21 are thin-gate transistors. This allows the transistor to have a smaller capacitance for a given gain. The source of the first transistor 210 is connected to the wheel-in 2 95 through a path 201 and a path 201. The terminal of the first transistor 210 is connected to a current mirror via a path 2 1 3. The source of the second transistor 2 11 is connected to the input 2 9 5 via the path 201 and the path 204. The non-electrode of the second transistor 211 is connected to a current mirror via the path 214. In FIG. 2, the first input 112 (FIG. 1) includes a second transistor pair 215 and a transistor 216. Preferably, the transistor 215 and the transistor 216 are of the same type. More preferably, the types of the transistor 215 and the transistor 216 are opposite to those of the transistor 86448 200414672 2 1 0 and the transistor 2 11. Although those skilled in the art will recognize other configurations to allow the use of the same type of transistor. More preferably, the transistor 21 5 and the transistor 21 6 are thin gate transistors. This allows the transistor to have a smaller capacitance for a given gain. The source of transistor 21 5 is connected to input 295 via path 202 and path 205. The drain of the first transistor 2 15 is connected to a current mirror via a path 261. The source of the second transistor 216 is connected to the input 295 via a path 202 and a path 206. The drain of the second transistor 216 is connected to a current mirror via a path 264. The gate of transistor 21 5 and the gate of transistor 2 16 are also connected to each other. The diode 1 3 0 (FIG. 1) circuit in FIG. 2 is configured as follows. The source of the first diode 290 is connected to the path 206. The drain of the first diode 290 is connected to path 298, which is connected to output 299. The gate of the first diode 290 is connected to the control circuit (not shown in the figure). The source of the second diode 291 is connected to the input path 205 via a path 207. The drain of the second diode 291 is connected to path 298 via path 283, and then path 298 is connected to output 299. The gate of the second diode 291 is connected to the control circuit (not shown). Preferably, the transistor 290 and the transistor 291 are both thin gate transistors. This allows the transistor to have a smaller capacitance for a given gain. In FIG. 2, the first current mirror 120 (FIG. 1) is configured as follows. A path 213 starting from the drain of the transistor 203 is connected to the source of the transistor 242. The gate of transistor 242 is connected to path 213, the gate of transistor 245, and the gate of transistor 240. The drain of transistor 242 is connected to path 255. Path 255 is connected to output 299 via path 298. The path 214 is connected to the source of the transistor 243. The gate of transistor 243 connects 86448 -10- 200414672 to path 214, the gate of transistor 246, and the gate of transistor 241. The drain of the transistor 243 is connected to the path 298 via a path 253. Path 298 is connected to output 299. Path 230 connects the drain of transistor 210 to the source of transistor 241. The gate of transistor 241 is connected to path 214, the gate of transistor 243, and the gate of transistor 246. The terminals of the transistor 241 are connected to a path 298 via a path 251. Preferably, the transistor 241 is a thin gate transistor. This allows the transistor to have a smaller capacitance for a given gain. Path 231 connects the drain of transistor 211 to the source of transistor 24. The gate of transistor 240 is connected to path 213, the gate of transistor 242, and the gate of transistor 245. The drain of transistor 240 is connected to path 298 via path 250. Preferably, the transistor 240 is a thin gate transistor. This allows the transistor to have a smaller capacitance for a given gain. Transistor 245 has a source connected to the drain of fa 2 16 via a path 232. The gate of the transistor 245 is connected to the paths 2 and 3 and the gates of the transistors 240 and 242. The drain of transistor 245 is connected to path 298 via path 254. Preferably, the transistor 245 is a thin gate transistor. This results in less capacitance for a given gain of these transistors. The source of the transistor 246 is connected to the terminal of the transistor 21 5 via a path 26 and a path 256. The gate of transistor 246 is connected to path 214, the gate of transistor 241, and the gate of 243. The drain of the transistor 246 is connected to a path 298 via a path 257. # 父 佳 地, the transistor 246 is a thin gate transistor. This allows the transistor to have a smaller capacitance for a given gain. In FIG. 2, the second current mirror 125 is configured as follows. The path 26 丨 from the drain of transistor 86448 -11-200414672 21 5 is connected to the source of transistor 1. The gate of the transistor 27 1 is connected to the gate of the transistor 272 via a path 273 and to a control circuit via a road control. The drain of the transistor 271 is connected to the link 298 via a path 279. Preferably, the transistor 271 is a thin gate transistor. This allows the transistor to have a smaller capacitance for a given gain. Circuit t 264 connects the source of transistor 276 to the drain of transistor 216. The gate of transistor 276 is connected to the gate of transistor 275 via path 277 and to a control circuit via circuit control 278 (not shown). The drain of the transistor 276 is connected to a path 298 via a path 281. Preferably, the transistor 276 is a thin gate transistor. This allows the transistor to have a smaller capacitance for a given gain. Path 262 connects the source of transistor 275 to the drain of transistor 2 15 via path 261. The gate of transistor 275 is connected to the gate of transistor 276 to the control circuit (not shown). The drain of transistor 275 is connected to path 298 via path 284. Preferably, the transistor 275 is a thin gate transistor. This allows the final transistor to have a smaller capacitance for a given gain. Path 263 connects the source of transistor 272 to the drain of transistor 2 16 via path 264. The gate of the transistor 272 is connected to the gate of the transistor fl. 271 via a path 273, and is connected to a control circuit (not shown) via a path 274. The drain of transistor 272 is connected to path 298 via path 280. Preferably, the transistor 272 is a thin gate transistor. This allows the transistor to have a smaller capacitance for a given gain. In FIG. 2, the diode 1 40 for connecting the output to the ground is the transistor 2 9 3 ′. The source of the transistor 2 9 3 is connected to the path 2 9 8 and the non-pole is connected to the ground. The gate of transistor 293 is connected to the control circuit (not shown). Better than 86448 -12-200414672, Dianjingjin #? 〇. π ^ a 3 series-thin gate transistor. Transistor 293 prevents the ▽ heart and ¥ of the transistor in circuit 200. The above description includes an exemplary embodiment of the present invention. I expect that those skilled in this technology will be sufficient and likely to design a circuit to infringe under the principle of "textual infringement or equality" within the scope of the patents listed below. [Brief description of the diagram], and a block diagram of an input stage < comparator of the low voltage differential signal receiver circuit according to the present invention; and FIG. 2 shows a circuit diagram of the input stage comparator according to the present invention. [Schematic representation of symbols] 103 path 104 path 105 path 11 〇 Two-level superposition circuit wiring 111 first input circuit 11 5 second input circuit 116 path 117 path 1 21 first current mirror 125 second current mirror 128 path 12 9 path 128 path 130 diode 86448 -13- 200414672 1 3 1 path 140 diode 141 path 201 path 202 path 203 path 204 path 205 path 206 path 207 path 208 path 21 0 transistor 211 transistor 2 1 3 Path 2 14 Path 2 1 5 Transistor 2 1 6 Transistor 2 17 Path 230 Path 231 Path 232 Path 240 Transistor 241 Transistor 242 Transistor -14- 86448 200414672 243 Transistor 245 Transistor 246 Transistor 250 Path 251 Path 253 Path 254 Path 255 Path 256 Path 257 Path 261 Path 262 Path 263 Path 264 Path 271 Transistor 272 Transistor 273 Path 274 Path 275 Path 275 Transistor 277 Path 278 Path 280 Path 281 Path-15- 86448 200414672 282 Path 283 Path 284 Path 290 Transistor 291 Transistor 293 Transistor 298 Path 299 Path 16- 86448