TW200414459A - Method of fabricating integrated circuits packaging structure - Google Patents

Abstract

A method of fabricating semiconductor devices with high density I/O connections is proposed. An insulated polymeric layer is formed on a circuit surface of the semiconductor chip, allowing an array of solder pads to then form in terms of redistribution technology thereon. Then, the insulated polymeric layer is electrically connected to the solder pads. As the array of solder bumps are allowed to be disposed on the area outside the circuit surface of the semiconductor chips, semiconductor chips with minimized size can be used for packages with various application.

Description

200414459 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a semiconductor wafer packaging technology, and more particularly to a semiconductor wafer packaging structure and process, which can be produced in batches on the same chip carrier A plurality of high-density and small-sized semiconductor chip packages. [Previous technology] Chip size packaging technology (Chip S ca 1 e Package, CSP) is an advanced packaging technology, which can make the size of the package only slightly larger than the size of the packaged wafer, so it can make The package is minimized to meet the requirements of thin, light and short. Wafer-level CSP packaging technology (Wafer Leve 1 CSP) is a more advanced packaging technology, which can be used to batch process all wafers cut out of each wafer In this way, multiple pieces can be completed at one time. Related patent technologies for wafer-level CSP packaging technology include, for example: • US Patent No. 5,886,409 “ELECTRODE STRUCTURE 0F WIRING SUBSTRATE OF SEMICONDUCTOR DEVICE HAVING EXPANDED PITCH, 1; • US Patent No. 5,892, 179 nSOLDER BUMPS AND STRUCTURES FOR INTEGRATED REDISTRIBUTION ROUTING CONDUCTORS n; • US Patent No. 6, 1 0 3, 5 5 2 "WAFER SCALE PACKAGING SCHEME ";

• US Patent No. 6, 3 50, 6 6 8 n LOW COST CHIP SIZE

17121.ptd Page 5 200414459 V. Description of the invention (2) PACKAGE AND METHOD OF FABRICATING THE SAME "; • US Patent No. 6, 433, 427 nWAFER LEVEL PACKAGE INCORPORATING DUAL STRESS BUFFER LAYERS FOR I / O REDISTRIBUTION AND, METHOD FOR FABRICATION '^ Wafer-level CSP packaging technology usually uses redistribution circuit technology to fly Redistribution Layer (RDL) to integrate non-equidistant power and k number of input and output points on the wafer through redistribution circuit technology. An equidistant array of solder pad arrays is defined in advance, and then solder bumps (s 〇 ^ er bumps) are bonded to the solder joint array to form a ball grid array (Bau #ray, BGA). Ball grid arrays bond packages to external printed circuit boards. % However, the above-mentioned redistribution circuit technology is to arrange the solder joint array on the surface. As the semiconductor process technology advances, the area gradually decreases, and the wafer with reduced size will have no extra surface space to accommodate the array of printed junctions. It is believed that in response to the end of the new _. 々 wiring, ΛΤ 4 ·, the day-to-day films are being miniaturized (such as below η Nanometer), and the main character of 90 锸 Jin is η & Potential + ¥ 脰 The industry needs to develop _ a new type of V-chip package structure and manufacturing process. [Summary of the invention] & ° The main purpose of the present invention lies in the percentage of ——I'm "The Criminal Servant 44" This kind of semiconductor is suitable for half of the present invention, such as the type below 90 nanometers, which is replaced by a chip package. Wafer sealing through ## 丨 丨 person. Structure and clothes. The carrier has a front surface and a lunar surface; (2) carrying out a meal for the skin, placing at least one chip in Ye Gong θ 罝 罝 fe sequence 'has a circuit surface and a Non-circuit surface, and the Japanese-Japanese film with-. ® and the majority of the solder formed on the 4 circuit surface

200414459 V. Description of the invention (3) Pad; (3) Perform an insulation layer process to form an insulation layer on the front side of the carrier, and make the insulation layer completely cover the wafer and expose it Solder pads on the circuit surface of the chip; (4) performing a redistribution line process, thereby forming a plurality of redistribution lines on the insulation layer; one end of each redistribution line is electrically connected to the chip One of the circuit surfaces corresponds to a solder pad, and the other end is intended to be a solder joint; (5) An insulation protection layer process is performed to form an insulation protection layer to cover each redistribution line, but exposed Predetermined solder joints of each redistribution line; (6) A ball-planting process is performed, whereby a plurality of solder balls are soldered to solder joints on each of the heavy wiring paths that are not covered by the insulating protective layer, so that Forming a ball grid array structure; and (7) performing all single processes, thereby cutting the carrier and dividing a plurality of individual semiconductor packages. The semiconductor wafer package structure of the present invention includes at least: (a) a carrier having a front surface and a back surface; (b) a wafer having a circuit surface and a non-circuit surface, and the circuit surface is formed with Most solder pads; (c) an insulating insulation layer that completely covers each wafer and exposes most of the solder pads on the circuit surface of each wafer; (d) a plurality of redistribution lines formed on the On the insulation layer, one end of each of the redistribution lines is electrically connected to a corresponding pad on the circuit surface of the chip, and the other end is predetermined as a solder joint; (e)-an insulation protection layer, It is used to cover each redistribution line, but exposes the predetermined solder joints of each redistribution line; and (f) a ball grid array including a plurality of solder balls, and each solder ball is soldered to each The solder joints on the heavy wiring paths that are not covered by the insulation protection layer. The semiconductor wafer package structure and manufacturing process of the present invention are characterized by the formation

17121.ptd Page 7 200414459 V. Description of the invention (4) Insulation insulation layer is formed on the wafer, and then a redistribution line is formed on the insulation insulation layer to form an array of solder joints. The redistribution lines are electrically connected to the wafer. This feature allows the fresh dot array that needs to be redistributed to be placed beyond the crystal surface and the surface of the wafer, ΔτλΓ. It is not confined to the surface of the wafer as in the conventional technology, so that new generations (such as 9 0 Micronized wafer below) can be borrowed. Resin layering technology can be used to make up for the lack of chip layout area. [Embodiment] The following is a detailed disclosure of the semiconductor chip package of the present invention with the accompanying drawings. Example of structure, process and process 0 One point to note here is that Figures 1 to 10 are simplified schematic diagrams:, which are only to illustrate the basics of the present invention in a schematic way. The idea is that it only shows elements related to the present invention and the displayed elements are not drawn with the number, shape, and size ratio in actual implementation. 'The number S, shape, and size ratio in actual implementation may be a random, meaning The nature of the ri-n. Ό is also selected and its component layout may be more complicated. First, please refer to FIG. 1 and 3. The semiconductor crystal of the present invention: 丨 The initial step of the packaging process is to prefabricate a carrier 10, The carrier 10 has a front surface 10 0a and a back surface 10b, and its selection is 3 female ports BTT α 5ismaleimide rp * 1 r 1 az] substrate, metal substrate (such as copper substrate) ceramic substrate, silicon In addition, a plurality of cutting lines 11 5 are pre-planned on the front of this carrier to distinguish the physical seals of each package. The above-mentioned carrier 10 is simultaneously equipped with a batch of wafers 20 (Note: As Said said said sheet package program 2.0 average is the same 7 because this is the simplified drawings and the Description to the first 1. view and a follow-up of the drawings will show only - - wafers Shu), and of such wafer 20

17121. ptd Page 8 V. Description of the invention ~ ^ ~ -------- The thickness of the wafer (not shown in the figure) below the basin is first ground to 3 m 1 1 circuit surface 20t Divide into a plurality of single wafers 20. However, each of the wafers 20 has / a plurality of pads 2 for providing electrical circuit surfaces 20b ', and a plurality of ^ at sources and h-number input / output pads formed on the circuit surface 20a. Please refer to FIG. 2 for the makeup. The next step is to perform a crystal process, and the non-circuit surface 20b of each wafer 20 is coated with an adhesive (such as silver glue. The front surface of the halberd 10 is 10a. So that the circuit surface 20a of the wafer 20 faces the host, please refer to FIG. 3. The next step is to perform an insulation and insulation t t to form a surface 10a on the front surface 10a of the implement 10. Insulation insulation layer ★ 'The insulation insulation layer 30 completely covers each wafer 20, but a plurality of openings 31 are formed to expose all the pads on the circuit surface 20a of the wafer 20. This insulation insulation layer process The conventional spin coating technology (sp 丄 n Coatln, g) is used to coat a dielectric material (dielectric) on the face ί 0 a of the carrier 10 to form the insulation layer 3 〇. And 'Please refer to FIG. 4, the next step is to perform a redistribution line process (R = dlstribution layer, RDL), so as to metallize the insulating layer 30 (meta 1 1 丨 zat 丨 〇). n) to form a plurality of redistribution lines 40, wherein one end of each redistribution line 40 is electrically connected to the electricity of the chip 20 A corresponding pad 21 on the surface 20a defines the other end of the circuit 40 as a fresh node 41. The redistribution circuit process can use sputtering or electroless plating (Electroiies — pUting) ) To form the redistribution circuit 4 above. After that, please refer to Figure 5, the next step is to perform an insulation protection.

17121. ptd 1 ^ · Page 9 200414459 V. Description of the invention (6) The layer process' forms 〆 * ,,,,, and 'passivation! Ayer' 50 to cover all the redistribution lines 4 0, but a plurality of openings 51 are formed in the insulating protective layer 50 to expose the predetermined solder joints 14 on each of the redistribution lines 40. This insulating protective layer 5 can be used as a long-distance Juya donkey. Amine (p 〇1 yimide), epoxy polymer (epoxy) or 〆 solder resist layer (Solder Mask) 〇 • Next, please refer to Figure 6 'The next step is to perform a ball-planting process, which will The ball 60 is soldered to each of the redistribution lines 4 0 on the solder joints 41 which are not covered by the insulating protective layer 50 to form a ball grid array. For more details, please refer to FIG. 7 'Next The steps are to make all single spears to cut the carrier 10 along its cutting line 11 so as to divide a plurality of individual packages to complete the semiconductor wafer packaging process of the present invention. The structure is-heavier Line products-domain generation · (-any example, example, corresponding to all in all, the present invention provides a novel The semiconductor wafer packaging and manufacturing process is characterized by forming an insulating isolation layer on the wafer, and then wiring technology to form a solder joint array on the insulating isolation layer, so that the wiring is electrically connected to the wafer pads. This feature The fresh spot array can be placed beyond the surface of the wafer instead of being limited to the surface of the wafer as in the known technique, so the new one is like a force of 90, a half, ten, and F. ) The miniaturized chip can be used by the packaging process of the present invention to make up for the lack of insufficient circuit layout area. = The figure shows the embodiment of the body chip packaging structure of the present invention. The process and structure using κ and ^ are roughly the same The aforementioned first implementation

The chip placement area with different dummy I in the pre-planned package range on the carrier 10 is provided with an area larger than that of the semiconductor wafer 20

200414459 V. Description of the invention (7) The opening 100 is used to stick the wafer 20 into the opening 100 when the crystal setting process is performed, so that the wafer 20 traditionally placed above the carrier 10 can be used. The storage of the opening 100 further reduces the overall height of the semiconductor package. The above descriptions are merely preferred embodiments of the present invention, and are not intended to limit the scope of the essential technical content of the present invention. The essential technical content of the present invention is broadly defined in the scope of the following patent applications. Any technical entity or method completed by another person that is completely the same as defined in the scope of patent application below, or an equivalent change, will be considered to be covered by this patent.

17121. ptd Page 11 200414459 Brief description of diagrams> [Simplified diagram] Figure 1 is a schematic cross-sectional structure diagram showing the semiconductor wafer package structure and the cross-sectional structure of the carrier and the wafer used in the process of the present invention Figure 2 is a schematic cross-sectional structure diagram showing the chip placement procedure in the semiconductor wafer packaging process of the present invention; Figure 3 is a schematic cross-sectional structure diagram showing the insulation barrier process in the semiconductor wafer packaging process of the present invention; FIG. 4 is a schematic cross-sectional structure diagram showing the redistribution wiring process in the semiconductor chip packaging process of the present invention, and FIG. 5 is a schematic cross-sectional structure diagram showing the insulation protective layer process in the semiconductor wafer packaging process of the present invention Figure 6 is a schematic cross-sectional structure diagram showing the semiconductor wafer of the present invention. The ball-planting process in the packaging process; Figure 7 is a schematic cross-sectional structure diagram showing the division process in the semiconductor wafer packaging process of the present invention; FIG. 8 is a schematic cross-sectional structure diagram showing a semiconductor chip package of the present invention Another configuration of the embodiment. Body Carrier 100 Carrier Opening 10a Carrier Front I 0 ti Carrier Back II Cutting Line

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Claims (1)

200414459 6. Scope of applying for a patent. A semiconductor wafer packaging process includes the following steps: (1) a carrier is prefabricated, which has a front surface and a back surface (2) a wafer placement process for placing at least one semiconductor wafer to On the front side of the carrier, the wafer has an active surface and an opposite non-active surface, and most of the bonding pads are formed on the active surface; (3) an insulation layer process is performed to form the wafer and the carrier; An insulation layer, with a plurality of openings formed on the insulation layer to expose each of the bonding pads on the wafer; (4) performing a redistribution line process to form a plurality of redistribution lines on the insulation layer, wherein, Each redistribution line is electrically connected to a corresponding solder pad on the chip, and a solder joint (5) is formed at the end of the line for an insulation protection layer process to form an insulation covering each redistribution line. A protective layer and exposing the solder-nodes of each redistribution line; (6) performing a ball-planting procedure to plant solder balls on each exposed red-distribution line solder node to form a ball grid array; And (7) all single process, to cut the carrier to form a plurality of individual semiconductor packages. According to the semiconductor wafer packaging process described in item 1 of the scope of patent application, the carrier described in step (1) is a silicon substrate. 3. The semiconductor wafer packaging process described in item 1 of the scope of patent application, wherein the carrier described in step (1) is a copper substrate. 4 The semiconductor wafer packaging process as described in item 1 of the patent application scope, which 17121. ptd Page 14 200414459 VI. Scope of Patent Application _ The carrier described in step (1) is a BT (Bismaleimide Triazine) substrate. _ 5. The semiconductor wafer packaging process according to item 1 of the scope of patent application, wherein the carrier described in step (1) is a ceramic substrate. 6. The semiconductor wafer packaging process as described in item 1 of the scope of patent application, wherein the insulating layer process described in step (3) uses a spin coating technology to apply a dielectric material to the carrier. The insulating layer is formed on the front surface of the tool. 7. The semiconductor chip packaging process according to item 1 of the scope of the patent application, wherein the redistribution circuit process described in step (4) uses sputtering technology (spu 11 ering) to form the heavy layers on the insulation layer. The wiring circuit 08. The semiconductor chip packaging process as described in item 1 of the scope of the patent application, wherein the redistribution circuit process described in step (4) uses electroless-plating on the insulation layer These redistribution lines are formed. 9. The semiconductor wafer package manufacturing process as described in item 1 of the scope of the patent application, wherein the insulation protection layer process described in step (5) uses polyimide (P ο 1 y i m i d e) to form the insulation protection layer. 10. The semiconductor chip packaging process as described in item 1 of the scope of the patent application, wherein the insulating protective layer process described in step (5) uses an epoxy polymer to form the insulating protective layer. 1 1. The semiconductor wafer packaging process as described in item 1 of the scope of patent application, wherein the process of insulating protection layer described in step (5) uses a solder resist layer 17121. ptd page 15 200414459 6. The scope of patent application w (Sο 1 der Mas k) to form the insulation protection layer. 1 2. A semiconductor chip packaging structure including at least: a carrier having a front surface and a back surface; a wafer having a circuit surface and a non-circuit surface, and a set of solders is provided on the circuit surface An insulating layer, and the insulating layer completely covers each wafer, but the pads on the circuit surface of each wafer are exposed; a plurality of redistribution lines are formed on the insulating layer, wherein each The redistribution circuit is electrically connected to a corresponding solder II pad on the chip, and a solder joint is formed at the end of the circuit; an insulation protection layer covers each redistribution circuit, and exposes each redistribution circuit Solder joints; and a ball grid array, further comprising a plurality of solder balls planted on the exposed solder joints of the redistributed κ line. u. The semiconductor chip package structure according to item 12 of the scope of patent application, wherein the carrier is a silicon substrate. 14. The semiconductor chip package structure as described in item 12 of the scope of patent application, wherein the carrier is a copper substrate. According to the semiconductor chip package structure described in item 12 of the patent application scope, wherein the carrier is a BT (Bismaleimide Triazine) substrate. 16. The semiconductor chip package structure according to item 12 of the scope of patent application, wherein the carrier is a ceramic substrate. 17. The semiconductor chip packaging structure as described in item 12 of the scope of patent application, wherein the front surface of the carrier corresponds to the region where the semiconductor wafer is placed. 17121. ptd Page 16 200414459 6. Scope of patent application There is an opening for receiving the wafer. 18. The semiconductor chip packaging structure according to item 12 of the scope of the patent application, wherein the material of the insulating protection layer is polyimide (P ο 1 y i m i d e). 19. The semiconductor chip package structure according to item 12 of the scope of patent application, wherein the material of the insulation and protection layer is epoxy resin (E ρ ο X y). 2 〇 The semiconductor chip package structure described in item 12 of the scope of the patent application, wherein the material of the insulating protection layer is a solder resist layer (S ο 1 d e r M a sk) 17121.ptd Page 17