TW200414125A - System and method of synthesizing a plurality of voices - Google Patents

Abstract

A system and method of synthesizing a plurality of voices are described. The system has a processing unit, a register, a latch unit, a timer and a digital/analog converter. The processing unit decodes voice data into decoded voices and the decoded data are then transmitted to the register. A plurality of different sampling signals of the timer are sent to the latch unit to trigger periodically the latch unit so that latch unit sequentially acquires the decoded voices stored in the register to avoid effectively jitters when the voice data are synthesized.

Description

200414125 V. Description of the Invention (l) Technical Field of the Invention The present invention relates to a speech synthesis system and method, and more particularly, to a speech synthesis system and method using a latching device to avoid Jitter. Prior art

With the rapid development of information technology and the popularization of communication networks, digital speech synthesis applications are becoming more common. For example, in electronic toys or mobile phones, speech coding is often used to process speech transmission, especially using speech synthesis technology. Voice compression processing, so that the operator can clearly hear the effect after sound synthesis to achieve the purpose of entertainment and mutual communication. Figure 1 is a block diagram of a conventional speech synthesis system. The main line of the speech synthesis system includes a processor 100, a register 102, a digital / analog converter 104, and a speaker 106. When performing the operation, firstly input a clock signal 丨 〇8 into the processor i 〇 and the register 102, so that the processor 〇〇 enters a step of calculating and decoding audio data according to the cycle of the clock signal 008. To generate decoded audio. Next, the register, 102 also uses the pulse signal 108 at this time to trigger the register 102 to receive the decoded audio of \ 理 mushroom 100 0, and convert the calculated decoded audio according to = to digital / analog conversion Device 104 and speaker 106.汴 1 Looking for deceased

Figure 2 shows the output axis of the speech synthesis system in Figure i. The vertical axis is the amplitude of the signal, which is equal to τ master- and glaze (Sampling Cycl; Vp; / DrD2). 9,,, 11 1 means shoulders. Ri7., Γmonth (, T2, ···, Tn), use Zhinuo ^ formula (F 1 rmware) to perform the deputy silence 4, macro # 1 for text Decoded audio obtained from private operation of firmware

Page 5 200414125 5. In the description of the invention, the processor must sequentially transmit the decoded audio (D1, D2) to the temporary register before the end of sampling (TIT2), so that the digital 1 can capture the decoded audio, and The rest of the decoded audio and so on. In fact, in the execution cycle T2 of the processor 100, in addition to decoding the audio calculations, it must also accept interrupt signals from other peripherals. This makes the processor 100 need to spend extra instruction time to process these ^ No. 11, so that the processor 100 cannot complete the calculation of the decoded audio D2 within the sampling period 72, and must delay to the next sampling period T3. That is, the processing device 1 0 0 cannot transmit the decoded audio D 2 to the temporary register i 〇 2 within the range of T 2.

Can be postponed until T3. ^ Especially in a multiplexed speech synthesis system, the processor 100 will receive multiple interrupt signals I η within the execution cycle range. Because the interrupt signal will occupy the instruction time occupied by the processor 100, so that Decoding audio cannot be generated in a specific sampling period in time, making the digital / analog converter 104 unable to read the de-encoding audio from the register, resulting in distortion (Distortion) of the entire audio synthesized waveform, causing audio jitter (Jitter) Effect. In other words, "bounce" means that when the processor 100 performs audio synthesis on audio data, there will be signal distortion or noise in the synthesized audio, which significantly reduces the quality of speech synthesis.

Therefore, 'how to use the speech synthesis system to eliminate the phenomenon of audio bounce, so that the speech synthesis system generates clear speech synthesis signals to improve the quality of audio synthesis' has become an urgent issue for the industry. Summary of the Invention

Page 6 (3) ^ ----------- 200414125 Description of the invention The device of the invention generates a register for use in the present invention, and synchronizes several synchronizing sounds based on sampled signals. The memory space of different memories is based on the above-mentioned voice synchronizer and clock signal data. Temporarily make the register latch device lock device capture the number to check the lock latch set five copies to apply

The purpose is to provide a speech synthesis system and method, which uses a direction-sampling signal to control a latching device, so that latching = de-gamma, solves the instruction time in the processor ⑷ _ ′ to improve the performance of the multiplexing performed by the processor. In order to provide a speech synthesis system and method, wt. generates multiple non-synchronous sampling signals for each other, and triggers a plurality of latching devices with each = sample signal, so that the latching devices are transmitted according to the periodicity. Decode audio to avoid audio bounce between channels. : ^ 'S is to provide a speech synthesis system and method, which uses complex ^ cutters to generate a plurality of asynchronous sampling signals to form an audio channel of complex frequency f, reducing the number of records required to store and decode audio to save the overall manufacturing of speech synthesis system cost. The present invention proposes a speech synthesis system and method. The system mainly includes a processor, a register, a latching device, and a counting / analog converter. The processor is connected to the memory, and the processor uses the processor to send and receive audio signals from the memory. The processor is used to decode audio data to form a decoder. The decoder is connected to the processor and uses the clock signal. Trigger the register to receive decoded audio from the processor. Connected to the register, the latching device is controlled by a timer, so that the decoded audio in the register is captured, wherein the timer sends a sampling signal device 'the latching device triggers periodically' the latching device according to the cycle of the sampling signal Actively receive decoded audio from the processor. Page 7 200414125 V. Description of the invention (4) --- ^ The digital analog converter is connected to the latching device. This digital / analog converter converts the digital type decoded audio into the analog type synthesized audio, and I-out to speaker. Thousands of two bodies, δ, the present invention uses a latching device with one or a plurality of timings to control the latching by forming a sampling signal by the σ ten-day guard: the access of the locking device, so that the latching device is at a predetermined period Download the audio data in the internal register and send it to the speaker to replace the traditional processor-controlled transmission board f ° Since each decoded audio of the present invention can be transmitted periodically according to the cycle of the sampling signal, the present invention The speech synthesis system can completely solve the phenomenon of audio beating. Since the 2 timer and the processor operate independently and the latching device is in a hardware synthesis type and is placed in the speech synthesis system, the latching device will not affect the processing. That is, the latching device will not occupy the instruction time of the processor, so that the pass finger: the latching device can periodically capture and transmit the calculation to complete the $ decoding audio according to the sampling period, and then the latching device transmits the decoding signal periodically at predetermined times.计算 Calculate audio data when there are sufficient instructions within the range of the processor's execution cycle to form two or more different sampling cycles. Decoding ^^ The latching device of the present invention can be equipped with more than two timers, making The lock device captures and transmits decoded tones according to the sampling period of each timer. More importantly, the two-channel speech synthesis system is a multi-channel speech synthesis system. The present invention is particularly suitable because traditionally, it is necessary to control the decoding on a poisoned time ^ Audio transmission, where the processor must complete the decoding of one channel or multiple voice channels on time within a line cycle

V. Description of Invention (5). In order to simplify the stability of the operation of the speech synthesis system, the speech synthesis system is not open to everyone: Immediately improve the operation of the system Signals are mutually used. That is, in the process of transmitting decoded audio between the first and second channels, if the first sampling period is used to transmit the second sampling period, the unsound sound is transmitted. The channel requires the processor to use the action of transmitting the decoded audio. Zhilu must wait until the first voice channel is interrupted. < 'The processor will only process the second voice. The latching device of the present invention cooperates with Fu Shizhi, so that the latching device actively triggers the decoding in the latching and retrieving register according to the inch 4 device ^ sir ^ The sampling period and the second sampling period come from the strings in each voice channel, and the decoded audio is transmitted regularly, so that there is no hysteresis in decoding between each voice channel. In other words, the sampling period of the timer is not determined, but it will not affect each other. Instead, the multi-channel speech will be greatly solved according to the proper sequence of the audio beat in the system. In summary, the present invention uses a speech synthesis latching device to make The main device of the latching device, method 4 and method, utilizes timer control to solve the performance of instruction processing in the processor to retrieve decoded audio in the register to perform multi-processing. Special ^ ^ ^ problem, in order to improve the processor to execute a number of asynchronous sampling signals, several timers "to generate a complex cycle to sequentially transmit decoded signals, and the lock device according to each sampling signal. In order to avoid the phenomenon of audio bounce. Embodiments Aiming at the shortcomings of traditional speech synthesis systems and methods, systems and methods, the present invention provides a language that uses a timer to control the latching device to enable latching.

$ 9 pages 200414125 V. Description of the invention (6) The device actively captures the decoded audio in the register to solve the problem of insufficient instruction time (M I P S) in the processor. Furthermore, a plurality of timers are respectively used to form a plurality of asynchronous sampling signals, and the latching device is triggered by each asynchronous sampling signal, so that the latching device sequentially transmits decoding of different channels according to each sampling signal cycle. Audio to avoid the phenomenon of audio bounce in the synthesized audio between each channel. First, referring to FIG. 3, a block diagram of a speech synthesis system according to the present invention is shown.

Illustration. This speech synthesis system forms synthesized audio by calculating audio data to avoid the phenomenon of audio bounce in the synthesized audio. The audio data is first stored in the memory. Basically, the speech synthesis system mainly includes a processor 200, a register 202, a latching device 204, a timer 206 (Ti, T2, ..., Tn) and a digital / analog converter 208. The processor 200 is connected to the memory 2 10, and the clock signal 2 1 2 is used to trigger the processor 2 0, so that the processor 2 0 reads the audio data in the memory 2 1 0, and the processor is used for 2 0. 〇 Decode audio data to form decoded audio. The register 2 02 is connected to the processor 200, and also uses the clock signal 21 2 to trigger the register 2 02, so that the register 2 02 receives the decoded audio from the processor 200.

The technology lock device 2 0 4 is connected to the register 200, and the timer 204 is used to control the lock body 204, so that the lock device 2 04 captures the decoded audio in the register 200, basin 1. The leaf timer 2 06 sends the sampling signal to the latching device 204, and the latching device 204 periodically triggers the latching device 204 according to the period of the sampling signal, so that the latching device receives the signal from the processor 20 Decode audio. In a preferred embodiment, the voltage measurement may be, for example, one or a plurality of counting devices (η ratio converter m is connected to the latch ... 〇4’㈣

200414125 V. Description of the invention (Ό Convert digital-type decoded audio into analog-type synthesized audio and output it to speakers 2 1 4 to listen to synthesized audio, such as a loudspeaker. In a preferred embodiment of the present invention, the latch Device 204 has a multiple-layer data structure for storing multiple layers of decoded audio. The multiple-layer data structure uses the first-in-first-out (FIF 0) rule to enable the latching device 2 0 4 to be based on the first-in-first-out (FIF 0 ) Sends the decoded audio to the digital / analog converter 208. The processor 2 0 can be, for example, a micro controller of the 502 series, a single chip, or a general-purpose central processing unit. 200 (Centiral Proeessirig Unit, CPU).

In addition, the decoded audio in the processor 2 0 is used to encode audio data in a waveform encoding method used in the time domain (τ ime D omai η). The waveform encoding method may be, for example, adaptive differential pulse code modulation (Adaptive Differential Pulse Code Modulation (ADPCM) and Differential Pulse Code Modulation (DPCM). Among them, adaptive differential pulse code modulation (ADPCM) uses digital sampling coding technology to convert an analog voice signal into a digital signal. And the adaptive differential pulse code modulation (ADPCM) takes the difference between two adjacent samples for recording ’, so the adaptive differential pulse code modulation (ADPCM) needs to store the same sound.

The space is smaller than the general Pulse Code Modulation (PCM) coding technology. '^ f And Lu, the present invention uses the latching device 20 4 with one or a plurality of t timers 2 06, and the sampling signal is formed by the timer 20 to control the latching device 2? Make the latching device 20 4 download the temporary information in a predetermined period] and send it to the speaker 214 to replace the traditional

200414125 V. Description of the invention (8) The mode of processing control transmission greatly saves the instructions that the processor 2000 can use. Since each decoded audio of the present invention can be transmitted periodically according to the cycle of the sampler number, the speech synthesis system of the present invention can completely resolve the phenomenon of audio bounce. Next, the operation timing diagrams of one or a plurality of timing and latching devices will be described in detail, and each different timer 2 06 is defined as a voice channel. In other words, the plurality of channels cooperate with the plurality of timers 206, the plurality of latching devices 204, the plurality of registers 202 (or random access memory), and the plurality of firmware programs, respectively. Please refer to FIG. 4, which illustrates a timing diagram of a speech synthesis system using a single timer 206 according to FIG. 3 of the present invention. The horizontal axis is the time axis, and the vertical axis is the amplitude of the signal. SC represents the working signal of the processor, where TC is the execution cycle of the working signal, and D1 is the decoded audio that the processor 2000 has calculated in one execution cycle. SL indicates the sampling signal of the timer 206, and TL indicates the sampling period of the sampling signal SL. During operation, the timer 2 06 triggers the latching device 204 by using a sampling signal, so that the latching device 204 captures the decoded audio D1 in the register 2 02 and decodes the audio D 丨 at a predetermined time p 丨It is sent to a digital / analog converter 2 0 8 to be converted into synthesized audio, and then the synthesized audio is output to a speaker 2 1 4. By analogy, the latching device 204 sequentially receives the decoded audio such as D 2, ..., D η by using the trigger mechanism of the timer 206, and transmits the decoded audio at predetermined times p 2,... The latching device 204 of the present invention uses the sampling signal of the timer 2 06 to receive the data of the register 2 0. Since the timer 2 06 and the processor 2 0 operate independently and independently, the latching device 2 0 4 does not affect the operation of the processor 2 0, that is, the latching device 2 4 does not occupy the instruction time of the processor 2 0. in particular,

Page 12 200414125 V. Description of the invention (9) If the processor 2 0 0 samples the decoded audio of the sampling period in the latching device 204 and sets the decoded sound to be within, the latching device 2 0 4 can be based on Take the tone; a state 2 0 2 message, to regularly access and transmit the data extraction code sample tone weekly pass Y to the geo-teach extraction de-muffler 2 08, to solve the voice in a single channel ^ Special ^ Audio bounce caused by digital / analog conversion decoded audio. μ, 'First because of delayed transmission? Second :! This is a timing diagram of using a plurality of timers H = in accordance with the third figure of the present invention. Basically, the fifth figure of the present invention is similar to the third figure, the main difference is that 筮 R and you ^ Μ 观 1M ^ ^ 9π, Figure 5 uses * several timers 2 0 64 to control the latching device 204, For the convenience of description, two timers 20 will be described, which are defined as the first timer T1 and the second timer 2 respectively. The horizontal axis is the time axis, the vertical axis is the amplitude of the signal, sc is the working signal of the processor, where TC represents the execution cycle of the processor 2 0 0, Du, ^ 丨 represents the calculation of the processor 2 0 within one execution cycle Two decoded audio completed. su indicates the sampling signal of the first timer T1, and TL1 indicates the sampling period of the sampling signal SL1. SL2 indicates the sampling signal of the second timer T2, and TL2 indicates the sampling period of the sampling signal SL2. During operation, the first timer τ 1 and the second timer T 2 make the decoded audio D 1 1 and D 2 in the register 2 0 2 according to the first sampling period τ L1 and the second sampling period TL 2, respectively. 1 At a predetermined time P 1 1, P 2 1, the first timer 2 0 6 and the second timer 2 0 6 are used to trigger the latching device 2 0 4 to cause the latching device 2 0 4 to capture the decoded audio D1 1 , D2 1. By analogy, the latching device 204 uses the triggering mechanism of the first timer T 1 and the second timer T 2 to sequentially receive decoded audio such as (1) 11,021), (012,013,022), (01111,0211), etc. To the predetermined time (Pll, P21), (P12, P13, P22), ~, (Plm, P2n)

Page 13 200414125

V. Description of the invention (10) Transmission. Since the first timer 2 0 6 and the second timer 2 0 6 operate independently from the processor 2 0, and the latching device 2 0 4 is set in the speech synthesis system in a hardware manner, the latching device 2 0 4 does not affect the operation of processor 2 0 0. That is, the latching device 204 will not occupy the instruction time of the processor 2000, so that the latching device 204 can periodically capture and transmit the decoded audio that has been calculated according to the first sampling period and the second sampling period. , And then the latching device 2 0 4 transmits the decoded audio signals d 1 1 and D 2 1 at predetermined time intervals. Therefore, during the execution cycle of the processor 20 0, the decoded audio D 11 and D 2 1 TC take care of and transmit the decoded audio through the first sampling period and the second sampling period without causing signal distortion in the synthesized audio. In other words, if there is sufficient instruction time in the range of the execution cycle (TC) of the processor 200 to calculate audio data to form decoded audio with two or more different sampling periods, the latching device 2 0 4 of the present invention may More than two timers 206 are configured so that the latching device 204 can capture and transmit decoded audio according to the sampling period of each timer 206. The invention is particularly suitable for a multi-channel speech synthesis system with a plurality of different sampling periods (asynchronous sampling signals). Because the processor 2000 traditionally controls the transmission of decoded audio, the processor 2000 must complete the decoded audio of one channel or multiple voice channels on time within an execution cycle. In order to simplify the operation of the speech synthesis system and improve the stability of the system's operation, the speech synthesis system does not open the interrupt signals between each speech channel to use each other. That is, when the first voice channel uses the first sampling period to transmit t-code audio, if the second voice channel requires the processor 200 to use the first

200414125 V. Description of the invention (11) Decoding audio is transmitted in the second sampling period. After the first voice channel finishes transmitting the decoded audio, the processor 200 will process the interruption request of the second voice channel. Therefore, in the conventional speech synthesis system, the decoded audio in the second speech channel is bound to be restricted by the first speech channel, so that the output synthesized audio has audio bounce. In contrast, the latching device 204 of the present invention is completely separated from the processor 2000, and cooperates with a plurality of timers 20 to individually trigger the latching device 2 04, so that the latching device 2 0 4 actively follows the first A sampling period and a second sampling period

Take the decoded audio in the register 200, and transmit the decoded audio periodically, so that the decoded audio in each voice channel will not lag. In other words, the decoding of audio between each voice channel does not affect each other, but rather determines the transmission order based on the sampling period of the timer 206, which greatly solves the phenomenon of audio bounce in a multi-channel voice generation system. FIG. 6 shows an operation flowchart of the speech synthesis system according to the present invention. First loss ^ 600, step. The clock frequency is used to trigger the processor, so that the processor reads the a data in the record. Then in step 602, the processor decodes the audio data money into three steps: Z5 and T5. Then in step 604, use the domain to send temporary storage, so that the processor directly loads the decoded audio directly to the receiver. In step 606, the plural latches are used to trigger the latching device. A plurality of sampled 'unnumbered' audios, each of which = the device actively captures the signal from the processor, and the latching device sends each channel ’s synthesizing sound on each channel in a timely manner to send the

200414125 V. Description of the invention (12) ~ '~-into audio' to avoid the phenomenon of audio bounce in synthesized audio. Then in step 6 08 ', the digital-to-analog converter converts the decoded audio into an analog penalty-type decoded signal. Finally, in step 610, the digital-to-analog converter outputs the decoded audio of the analog format to the speaker. In summary, the present invention utilizes a register of a speech synthesis system, and uses a timer to control the stationery. The headphone directly controls the decoded sound in the register; the device actively captures the temporary use problem to improve The effect of using a plurality of timers 21 is insufficient. According to the present invention, each non-synchronous sampling signal device generates a plurality of non-synchronous sampling signal devices to trigger the latching device according to each sampling signal and sample signal, so that the latching is free of audio jumping. The decoded audio is transmitted in order to avoid generating a plurality of non-synchronized fetching m 2. The present invention uses a plurality of timers to reduce the storage cost of the decoded audio respectively; the manufacturing cost of the “channels with no rate” is reduced. The present invention of the speech synthesis system has been revealed to be better implemented. The use of ri m ΐ Γ is as above. It is only used to help understand the spirit of the present invention. ^ The spirit of the invention is appreciated by those skilled in the art. The scope of patent protection varies according to the scope of the patent and its equivalent.

Page 16 200414125 Schematic illustration Schematic illustration To make the above and other objects, features, and advantages of the present invention more comprehensible, the following detailed description is given in conjunction with the following drawings: Figure 1 shows a traditional speech synthesis system Figure 2 shows the output timing diagram of the speech synthesis system of Figure 1; Figure 3 shows the block diagram of the speech synthesis system according to the invention; Figure 4 shows the use of Figure 3 according to the invention Output timing diagram of a single timer speech synthesis system; Figure 5 illustrates the output timing diagram of a speech synthesis system using multiple timers according to Figure 3 of the present invention; and Figure 6 illustrates the speech synthesis according to the present invention System operation flowchart. Description of the graphical symbols 1 0 0, 2 0 0 ·· Processor 1 0 2, 2 0 2: Register 1 0 4, 2 0 8: Digital / analog converter 106, 214: Speaker 1 0 8, 2 1 2: Clock signal 2 0 4: Latching device 2 0 6: Timer 210: Memory

Page 17

Claims (1)

200414125 VI. Application Patent Scope 1. A speech synthesis system that forms synthesized audio by calculating audio data and avoids the phenomenon of audio bounce in the synthesized audio. The speech synthesis system includes at least: a memory for storing the Audio data; a processor is connected to the memory, triggers the processor with a clock signal, causes the processor to read the audio data in the memory, and the processor decodes the audio data to form a decode Audio; a register is connected to the processor, and the register is triggered by the clock signal so that the register receives the decoded audio from the processor; a latching device is connected to the register, The latching device is controlled by a timer, so that the latching device captures the decoded audio in the register, wherein the timer sends a sampling signal to the latching device, and the latching device is based on the sampling signal. The latching device is triggered periodically and periodically, so that the latching device actively receives the decoded audio from the processor to avoid generating audio in the synthesized audio. Phenomenon of signal bounce; and a digital / analog converter connected to the latching device, the digital / analog converter converts the digital audio decoded audio into an analog analog audio, and outputs the analog audio to a speaker, To listen to the synthesized audio. 2. The speech synthesis system described in item 1 of the scope of patent application, wherein the latching device is provided with a plurality of layers of data structure for receiving the decoded audio. 3. The speech synthesis system as described in item 2 of the scope of patent application, wherein the temporary storage Page 18 200414125 6. Scope of Patent Application The device contains at least Random Access Memory (RAM). 4. The speech synthesis system as described in item 2 of the scope of the patent application, wherein the data structures of the layers include at least a first-in-first-out (F I F 0) rule to transmit the decoded audio to the lock detection device. 5. The speech synthesis system as described in item 1 of the scope of patent application, wherein the processor includes at least a microcontroller (Micro-controller) or a central processing unit (Centra 1 P r cessing Unit, CPU). 6. The speech synthesis system according to item 1 of the scope of patent application, wherein the processor includes encoding the audio data using a Waveform Coding rule. 7. The speech synthesis system as described in item 6 of the scope of patent application, wherein the Waveform Coding rule includes at least a Code Excited Linear Prediction (CELP) rule. 8. The speech synthesis system as described in item 6 of the scope of patent application, wherein the waveform coding rule includes at least the adaptive differential pulse code modulation (ADPCM) rule. 9 · The speech synthesis system as described in item 6 of the patent application scope, wherein the waveform coding rule includes at least a differential pulse code modulation (DPCM) rule. Page 19 200414125 VI. Patent application scope Data 1 · A kind of speech synthesis system, by calculating only the audio in the memory, forming a composite audio of a plurality of channels, and avoiding the phenomenon of audio bounce in the synthesized audio The speech synthesis system includes at least a processor connected to the memory, triggers the processor with a clock signal, causes the processor to read the audio data in the memory, and the processor processes the audio data Decode to form decoded audio; a register is connected to the processor, and the clock signal is used to trigger the temporary Is to enable the register to receive the decoded audio from the processor;-latching device connection In the Y device, M uses a plurality of devices to form a plurality of sampling signals to control the t-locking device. The mobile devices extract the unlocking device from the process II; the lock device 'makes the main number of the latching device corresponding to each of the The combination of these channels, each of the samples, the samples, and the samples are transmitted periodically by the latching device by avoiding audio skipping in the synthesized audio channels. The synthesized audio, a phenomenon that a digital / analog converter is connected to the pick-up lock, and a digital type analog decoding converter & device, and the digital / analog conversion signal is used to output to a speaker to : 2 analog types of the synthesized sound ^ the synthesized audio. 11. As described in item 10 of the scope of the patent application, the human lock device is provided with a plurality of layers of data structure, and s σ is used to form a system ', wherein the plug is used to receive the decoded audio. 1 2. The speech synthesis system as described in item 11 of the scope of patent application 200414125 6. Scope of patent application The layer data structure includes at least the first-in-first-out (F I F0) rule to transmit the decoded audio to the latching device. 1 3 · The speech synthesis system as described in item 10 of the scope of patent application, wherein the processor includes at least a micro-controller or a central processing unit (CPU). 14. The speech synthesis system as described in item 10 of the scope of patent application, wherein the processor includes encoding the audio data using a Waveform Coding rule. 15 · The speech synthesis system as described in item 14 of the scope of patent application, wherein the Waveform Coding rule includes at least a Code Excited Linear Prediction (CELP) rule. 16. The speech synthesis system according to item 14 of the scope of patent application, wherein the waveform coding rule includes at least the adaptive differential pulse code modulation (ADPCM) rule. 17 • The speech synthesis system as described in item 14 of the scope of patent application, wherein the waveform coding rule includes at least the differential pulse code modulation (DPCM) rule. 1 8 · A method of speech synthesis, which calculates the audio data in the memory to form a plurality of channels of synthesized audio, and avoids the phenomenon of audio bounce in the synthesized audio. The audio synthesis method includes at least the following steps: Page 21 200414125 Enabling the processor to read the memory within the scope of the patent application; use the Japanese pulse signal to trigger processing to write the audio data; the processor uses the clock signal to trigger the decoded audio of temporary storage benefits; Decoding to form a decoding audio device, so that the register receives it there = triggering with a plurality of sampling signals formed by a plurality of counting devices ^ the latching device is based on each of the sampling signals = The latching device enables the latching device to actively capture audio from the processing code, wherein each of the sampling signals corresponds to each of the channels = numbers and becomes audio, and the latching device passes each of the samples The signal is transmitted on time ^ the synthesized audio of each of the channels to avoid the phenomenon of ^ signal jitter in the synthesized audio; and the digital / analog converter converts the decoded audio into an analog type of the dema signal, and Output to audio generating device. 19 · The speech synthesis method according to item 18 of the scope of patent application, wherein the lock device is provided with a plurality of layers of data structure for receiving the decoded audio. 2 0. The speech synthesis method described in item 19 of the scope of the patent application, wherein the data structures of these layers at least include the rule of first in, first out (F 1 F 0) to transmit the _ decoded audio to the latch Device. 2 1 · The speech synthesis method described in item 18 of the scope of patent application ’, wherein the processor includes at least a microcontroller (micro-contro1 ler) or a central processing unit Page 22 200414125 VI. Patent Application Central Processing Unit (CPU). 2 2 · The speech synthesis method described in item 18 of the scope of patent application, wherein the processor includes encoding the audio data using a Waveform Coding rule. 2 3 · The speech synthesis system as described in item 22 of the scope of patent application, wherein the Waveform Coding rule includes at least the Code Excited Linear Prediction (CELP) rule. 2 4 · The speech synthesis method as described in item 22 of the patent claim, wherein the waveform coding method includes at least the adaptive differential pulse code modulation (ADPCM) rule. 2 5 _ The speech synthesis method described in item 22 of the scope of patent application, wherein the waveform coding rule includes at least the differential pulse code modulation (j) PCM) rule.