JP2004226968A - Device and method for speech synthesis - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a device and a method for speech synthesis whose processing capability is increased by solving a problem of contention of instruction timings of a processor. <P>SOLUTION: Provided are a memory, a processor, a register, a latch circuit, a timer means, and an D/A converter; and the processor decodes speech signal data and outputs the decoded speech signal to the register and the latch circuit is triggered with a sampling signal outputted from the timer means to read the decoded speech signal out of the register in cycles of the sampling signal and transfer the decoded speech signal to the D/A converter at fixed time. Consequently, jitters of a synthesized speech signal are suppressed. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to a voice synthesizing apparatus and method, and more particularly, to a voice synthesizing apparatus and method for preventing jitter of a voice signal using a latch circuit.

  With the rapid development of information technology and the spread of communication networks, digitized speech synthesis technology has been widely applied. For example, in an electronic toy, a mobile phone, or the like, a voice coding technique is often used for voice transfer. In particular, by using the voice synthesis technology for voice compression, the user can clearly view the voice effect after the synthesis, thereby achieving the purpose of entertainment and mutual exchange.

  FIG. 1 is a block diagram showing the configuration of a conventional speech synthesis system.

  The speech synthesis system shown in FIG. 1 includes a processor 100, a register 102, a digital / analog (D / A) converter 104, and a speaker 106.

  During operation, the clock signal 108 is input to the processor 100 and the register 102, and the processor 100 performs a decoding calculation on the audio signal data at a cycle of the clock signal 108 to generate a decoded audio signal (hereinafter, the processor 100). The output decoded audio signal is called a decoded audio signal). The register 102 is also triggered by the clock signal 108 and takes in the decoded audio signal output from the processor 100, and the signal is sequentially transferred to the D / A converter 104 and the speaker 106.

  FIG. 2 is a timing chart of the output of the speech synthesis system shown in FIG.

  In FIG. 2, the horizontal axis represents time, the vertical axis represents signal amplitude, T1, T2,..., And Tn represent sampling cycles (SP) of the audio signal, and D1, D2,. , Tn represents the decoded audio signal obtained by the subroutine calculation by the firmware within the range of each sampling cycle (T1, T2,..., Tn).

  In theory, taking the signals D1 and D2 as an example, the processor 100 would transfer the signals D1 and D2 to the register 102 sequentially before the end of the sampling cycles T1 and T2, respectively. And D2 can be supplied. The same applies to other signals such as D3.

  However, in practice, for example, in the sampling cycle T2, the processor 100 may receive an interrupt signal I1 from the surroundings other than decoding the audio data, so that the processor 100 uses the instruction time to execute the decoding. Such an interrupt signal I1 must be processed, so that the processor 100 cannot complete the calculation to obtain the signal D2 within the sampling cycle T2 and will be delayed to the next sampling cycle T3. That is, the processor 100 cannot transfer the audio signal D2 to the register 102 within the sampling cycle T2, and the transfer is delayed to the next sampling cycle T3.

  Particularly in a multimedia speech synthesis system, in one sampling cycle, the processor 100 may receive many interrupt signals In. Since processing of such an interrupt signal uses the instruction time of the processor 100, the processor 100 cannot generate a decoded audio signal within a given sampling cycle. As a result, the D / A converter 104 cannot read the audio signal from the register 102 as scheduled, so that the synthesized waveform of the entire audio signal is distorted, and a jitter phenomenon of the audio signal occurs. In other words, the jitter of the audio signal is accompanied by signal distortion or noise in the synthesized audio signal when the processor 100 synthesizes the audio data, and reduces the quality of the audio synthesis.

  Therefore, how to remove jitter of a voice signal and generate a high-quality voice synthesized signal in a voice synthesis system is an important issue in this field.

  One object of the present invention is to solve the problem of instruction time contention in a processor by controlling a latch circuit using a sampling signal from a timing unit and reading a decoded audio signal from a register, thereby improving audio processing. An object of the present invention is to provide a synthesizing apparatus and method.

  Further, another object of the present invention is to trigger a plurality of latch circuits by a plurality of asynchronous sampling signals from a plurality of time measuring means, and to transfer a decoded voice signal at a period of the sampling signal, thereby obtaining a synthesized voice signal. It is an object of the present invention to provide a voice synthesizing apparatus and method capable of preventing jitter.

  Further, another object of the present invention is to generate a plurality of channels of audio signals having different sampling frequencies by using a plurality of asynchronous sampling signals from a plurality of time measuring means, so that a storage capacity required for storing decoded audio signals is obtained. It is an object of the present invention to provide a speech synthesizing apparatus and method that can reduce the cost of the system and reduce the manufacturing cost of the system.

  In order to achieve the above object, a voice synthesizer of the present invention is a voice synthesizer that generates a synthesized voice signal from voice signal data, wherein the memory stores the voice signal data, and is triggered by a clock signal. A processor that reads and decodes the audio signal data from a memory to generate a decoded audio signal; a register that is triggered by the clock signal to receive the decoded audio signal from the processor; a timer that outputs a sampling signal; A latch circuit that is triggered by the sampling signal output by the sampling signal and reads the decoded audio signal from the register, and converts the decoded audio signal from the latch circuit from a digital signal to an analog signal, Digital for generating the synthesized speech signal Including analog converter.

  Specifically, by providing one or a plurality of timing means and controlling the operation of the latch circuit using the sampling signal from the timing means, the latch circuit reads the register decoded audio signal at a predetermined cycle, and To the circuit. According to the present invention, all decoded audio signals can be transferred in synchronization with the sampling signal, so that jitter in the synthesized audio signal can be removed.

  In addition, the clock means and the processor operate independently, and the operation of the processor is not affected since the latch circuit is provided as hardware in the speech synthesizer. That is, the latch circuit does not use the instruction time of the processor, so that the latch circuit can fetch and transfer the decoded audio signal periodically at the cycle of the sampling signal.

  If the instruction time for calculating the audio signal data is sufficiently long within the execution cycle of the processor and a decoded audio signal corresponding to two or more sampling cycles can be formed, the speech synthesis apparatus according to the present invention is used. Provided with two or more clocking means, and can fetch and transfer the decoded audio signal in synchronization with the sampling signal of each clocking means.

  The present invention is particularly suitable for a multi-channel speech synthesis system using a plurality of different sampling periods (asynchronous sampling signals). In the conventional multi-channel speech synthesis system, since the processor controls the transfer of the decoded speech signal, the processor needs to complete the decoding of the speech signal data of one or more speech channels within one execution cycle. Also, for simplification of system operation and stability of operation, sharing of interrupt signals between audio channels is prohibited, that is, the first audio channel is decoded using the first sampling signal. While transmitting the decoded audio signal, if the second audio channel requests to transmit the decoded audio signal using the second sampling signal, the first audio channel may transmit the audio signal. Only after completion, the processor will not process the interrupt request for the second audio channel.

  On the other hand, in the case of the present invention, the two timing means separately trigger the latch circuit, and the latch circuit takes in the decoded audio signal from the register at the first and second sampling periods and transfers it periodically. Therefore, the decoded audio signal is not delayed in each audio channel. In other words, between the audio channels, the decoded audio signals do not affect each other, and the transfer order is determined by the sampling period of each time-measurement means. Can be suppressed.

  According to the present invention, a latch circuit is controlled by using a timing unit, and the latch circuit reads a decoded audio signal from a register, thereby solving the problem of instruction time contention in a processor. Can increase the processing capability of the processor.

  Also, a plurality of asynchronous sampling signals are generated by using a plurality of timing means, and the latch circuit can prevent the jitter in the synthesized audio signal by sequentially transmitting the decoded audio signal at the cycle of each sampling signal. .

  In order to solve the problem of the conventional speech synthesizer, the latch circuit is controlled by using the sampling signal from the timing means, and the latch circuit is made to actively read the decoded speech signal from the register, thereby reducing the instruction time in the processor. Provided is a speech synthesis device and method capable of solving a contention problem. Also, a plurality of asynchronous sampling signals are generated by using a plurality of timing means, a plurality of latch circuits are triggered, and the latch circuits sequentially transfer decoded audio signals of different channels in a cycle of each sampling signal, thereby providing an audio channel. The present invention provides a voice synthesizing apparatus and method capable of preventing a jitter in a synthesized voice signal during the period.

  Next, embodiments of the present invention will be described with reference to the accompanying drawings.

  FIG. 3 is a block diagram showing the configuration of the speech synthesis system of the present invention.

  The voice synthesis system shown in FIG. 3 generates a synthesized voice signal from voice signal data and prevents jitter in the synthesized voice signal. The audio signal data is stored in the memory.

  The speech synthesis system includes a processor 200, a register 202, a latch circuit 204, a timer 206, a digital / analog (D / A) converter 208, a memory 210, and a speaker 214.

  The processor 200 is connected to the memory 210. In addition, the processor 200 is triggered by the clock signal 212 to read audio signal data from the memory 210, perform decoding in the processor 200, and generate a decoded audio signal.

  Register 202 is connected to processor 200. Register 202 is also triggered by clock signal 212 to receive the decoded audio signal from processor 200.

  The latch circuit 204 is connected to the register 202. Further, the latch circuit 204 is controlled by the timer 206 to read the decoded audio signal from the register 202.

  The timer 206 outputs the sampling signal to the latch circuit 204. The latch circuit 204 is triggered by the period of the sampling signal and actively reads the decoded audio signal from the register 202.

  For example, the timer 206 includes a counter (timer) that measures one or a plurality of times.

  The D / A converter 208 is connected to the latch circuit 204, converts the decoded audio signal from the latch circuit 204 from a digital signal to an analog signal, and generates a synthesized audio signal. The D / A converter 208 outputs the synthesized voice signal to the speaker 214.

  Preferably, the latch circuit 204 has a data structure of a plurality of layers and stores decoded audio signals of a plurality of layers. For example, these data structures include a FIFO (First In First Out) circuit, and transfer the decoded voice signal to the D / A converter 208 according to the First In First Out rule.

  The processor 200 includes, for example, a 6502 series microcontroller or a single board or a general-purpose central processing unit CPU (Central Processing Unit).

  The audio signal data in the memory 210 is, for example, encoded by waveform encoding used in the time domain, for example, an adaptive differential pulse code modulation (ADPCM) or a differential pulse. There is a code modulation method (Differential Pulse Code Modulation: DPCM) and the like.

  ADPCM converts an analog audio signal into a digital signal by using digital sampling encoding (Digital Sampling Encoding) technology. Since ADPCM records the difference between adjacent samples using the fact that speech continuously changes, the capacity required to store the same speech is smaller than that of other encoding schemes (eg, PCM). .

  Specifically, one or a plurality of timekeeping means 206 is provided for the latch circuit 204, the timekeeping means 206 generates a sampling signal, controls the read / write operation of the latch circuit, and the latch circuit outputs a signal from the register 202 at a predetermined cycle. The decoded audio signal is read and output to the speaker 214. Compared with the conventional method in which the processor controls the transfer of the decoded audio signal, the present invention can greatly reduce the available instruction time of the processor 200.

  In the present invention, all decoded audio signals can be transferred in synchronization with the sampling signal, so that jitter in the synthesized audio signal can be completely removed.

  Next, an operation in the case where one or a plurality of timing units 206 are provided for the latch circuit 204 will be described. When a plurality of timekeeping means 206 are provided, each timekeeping means 206 is defined as one audio channel. In other words, the plurality of audio channels correspond to the plurality of time counting means 206, the plurality of latch circuits 204, the plurality of registers 202 (or RAM: Random Access Memory), and the plurality of firmware.

  FIG. 4 is a timing chart in the case where one clock unit 206 is provided for the latch circuit 204 in the speech synthesis system shown in FIG.

  4, the horizontal axis represents time, the vertical axis represents signal amplitude, SC represents an input signal of the processor 200, and TC represents an execution cycle of the input signal SC. D1 represents the decoded audio signal calculated within one execution cycle of the processor 200. SL represents the sampling signal of the time counting means 206, and TL represents the period of the sampling signal SL.

  In operation, the timing means 206 triggers the latch circuit 204 using the sampling signal SL, so that the latch circuit 204 reads the decoded audio signal D1 from the register 202, and furthermore, at a predetermined time P1, the decoded audio signal D1 To the D / A converter 208. The D / A converter 208 converts the decoded audio signal D1 into a synthesized audio signal and outputs the synthesized audio signal to the speaker 214.

  Similarly, the latch circuit 204 sequentially reads the decoded audio signals D2,..., Dn from the register 202 and transfers them to the D / A converter 208 at predetermined times P1,.

  In the present invention, the latch circuit 204 reads a signal from the register 202 by using the sampling signal SL from the timer 206, and the timer 206 and the processor 200 operate independently. It has no effect on operation, ie, the latch circuit 204 does not use the instruction time of the processor 200.

  Specifically, the processor 200 completes the decoding of the audio signal data corresponding to the sampling cycle before the predetermined sampling cycle of the latch circuit 204, and stores the decoded audio signal in the register 202. Reference numeral 204 sequentially reads the decoded audio signal at the period of the sampling signal, and transfers the decoded audio signal to the D / A converter 208 on a regular basis. This makes it possible to completely suppress the jitter of the audio signal due to the delay in the transfer of the decoded signal in the single-channel audio synthesis system.

  FIG. 5 shows a timing chart in the case where a plurality of time measuring means 206 are provided for the latch circuit 204 in the speech synthesis system shown in FIG.

  FIG. 5 is basically the same as FIG. 4 except that FIG. 4 shows the case of one clock means 206, whereas FIG. 5 shows the case of a plurality of clock means 206. For convenience of explanation, it is assumed that there are two timekeeping means 206, which are T1 and T2, respectively.

  5, the horizontal axis represents time, the vertical axis represents signal amplitude, SC represents an input signal of the processor 200, and TC represents an execution cycle of the input signal SC. D11 and D21 represent two decoded audio signals calculated within one execution cycle of the processor 200. SL1 represents the sampling signal of the first clocking means T1, and TL1 represents the period of the sampling signal SL1. SL2 represents the sampling signal of the second clocking means T2, and TL2 represents the period of the sampling signal SL2.

  In operation, the first timing means T1 and the second timing means T2 trigger the latch circuit 204 with the sampling signal SL1 and the sampling signal SL2, respectively, whereby the latch circuit 204 outputs the decoded audio signal D11 from the register 202 and D21 is read, and the decoded audio signals D11 and D21 are transferred to the D / A converter 208 at predetermined times P11 and P21. The D / A converter 208 converts the decoded audio signals D11 and D21 into a synthesized audio signal and outputs the synthesized audio signal to the speaker 214. Similarly, the latch circuit 204 is sequentially triggered by the first timer T1 and the second timer T2, and sequentially decodes the decoded audio signals (D11, D21), (D12, D13, D22),. (D1m, D2n) is read and transferred to the D / A converter 208 at predetermined times (P11, P21), (P12, P13, P22),..., (P1m, P2n).

  In the present invention, the first clock unit T1, the second clock unit T2, and the processor 200 operate independently, and the latch circuit 204 is installed as hardware in the speech synthesis system. It does not affect the operation of the processor 200, that is, the latch circuit 204 does not use the instruction time of the processor 200. Therefore, the latch circuit 204 can read the decoded audio signals D11 and D21 periodically at the first sampling period and the second sampling period, and transfer them to the D / A converter 208 at predetermined times P11 and P21. it can. As a result, jitter in the synthesized voice signal is completely suppressed.

  In other words, the processor 200 determines that if the instruction time for calculating the audio signal data is sufficient and the decoded audio signal corresponding to two or more sampling periods can be formed within the execution period TC, Two or more clocking means 206 are provided for the latch circuit 204 in the voice synthesizing apparatus of the present invention, and the latch circuit 204 can read and transfer the decoded voice signal in synchronization with the sampling signal of each clocking means.

  The present invention is particularly suitable for a multi-channel speech synthesis system using a plurality of different sampling periods (asynchronous sampling signals). In the conventional multi-channel speech synthesis system, since the processor controls the transfer of the decoded speech signal, the processor needs to complete the decoding of the speech signal data of one or more speech channels within one execution cycle. Also, for simplification of system operation and stability of operation, sharing of interrupt signals between audio channels is prohibited, that is, the first audio channel is decoded using the first sampling signal. If the second audio channel uses the second sampling signal to request the transmission of the decoded audio signal while the encoded audio signal is being transmitted, the first audio channel can transmit the audio signal. Only after completion, the processor will not process the interrupt request for the second audio channel. For this reason, the decoded audio signal in the second audio channel is limited to the first audio channel, and jitter is generated in the output synthesized audio signal.

  On the other hand, in the case of the present invention, the latch circuit 204 and the processor 200 are independent, and the plurality of time counting means 206 separately trigger the latch circuit 204, and the latch circuit is actively activated by the first and second latch circuits. The decoded audio signal is read from the register 202 at the sampling period of 2 and is transmitted on a regular basis. Therefore, the decoded audio signal is not delayed in each audio channel. That is, since the decoded audio signals do not affect each other between the audio channels and the transfer order is determined by the sampling period of the respective time-measuring means, the jitter phenomenon of the synthesized audio signal in the multi-channel audio synthesis system is largely suppressed. Can be

  FIG. 6 is a flowchart showing the operation of the speech synthesis system of the present invention.

  In step S600, the processor 200 is triggered by the clock signal 212 to read audio signal data from the memory 210.

  At step S602, the processor 200 decodes the audio signal data to generate a decoded audio signal.

  In step S604, register 202 is triggered by clock signal 212, and register 202 receives the decoded audio signal from processor 200.

  In step S606, the latch circuit 204 is triggered at each cycle of the sampling signal by the plurality of sampling signals output from the plurality of timing units 206, and the latch circuit 204 corresponds to each of the plurality of sampling signals. A plurality of channels of decoded audio signals are read from the register 202. One sampling signal corresponds to a synthesized audio signal of one audio channel. The latch circuit 204 reads the decoded audio signal from the register 202 on a regular basis based on each sampling signal and transfers the decoded audio signal on a regular basis. Thereby, the jitter phenomenon of the synthesized voice signal is suppressed.

  In step S608, the multi-channel decoded audio signal is converted from a digital signal to an analog signal to generate a multi-channel synthesized audio signal.

  In step S610, an analog synthesized voice signal is output to a speaker.

  As described above, in the speech synthesizer of the present invention, the register is controlled by the latch circuit, the latch circuit is controlled by the timing unit, and the latch circuit can actively read the decoded speech signal from the register. As a result, the problem of instruction time contention in the processor can be solved, and the processing capability of the processor in the speech synthesis system can be increased.

  Also, the speech synthesizer of the present invention generates a plurality of asynchronous sampling signals using a plurality of time measuring means, and the latch circuit sequentially transfers the decoded speech signal at a cycle of each sampling signal, thereby obtaining a synthesized speech signal. Can be prevented.

  In addition, the speech synthesizer of the present invention generates a plurality of channels of audio signals having different sampling frequencies by using a plurality of asynchronous sampling signals from a plurality of time measuring means, so that a storage capacity required for storing a decoded audio signal is obtained. And the manufacturing cost of the system can be reduced.

  Although the preferred embodiment of the present invention has been described above, the present invention is not limited to this embodiment, and any modifications to the present invention fall within the scope of the present invention unless departing from the spirit of the present invention.

FIG. 11 is a block diagram illustrating a configuration of a conventional speech synthesis system. 2 is a timing chart of an output of the speech synthesis system shown in FIG. 1. 1 is a block diagram illustrating a configuration of a speech synthesis system according to the present invention. 4 shows a timing chart in the case where a single timing unit is used in the speech synthesis system shown in FIG. 3. 4 shows a timing chart when a plurality of timing units are used in the speech synthesis system shown in FIG. 3. 5 is a flowchart showing the operation of the speech synthesis system of the present invention.

Explanation of reference numerals

100, 200 Processor 102, 202 Register 204 Latch circuit 206 Timing means 104, 208 D / A converter 210 Memory 108, 212 Clock signal 106, 214 Speaker

Claims (4)

A speech synthesizer for generating a synthesized speech signal from speech signal data, comprising:
A memory for storing the audio signal data;
A processor triggered by a clock signal to read and decode the audio signal data from the memory to generate a decoded audio signal;
A register triggered by the clock signal and receiving the decoded audio signal from the processor;
Timing means for outputting a sampling signal;
A latch circuit that is triggered by the sampling signal output from the timing means and reads the decoded audio signal from the register; and converts the decoded audio signal from the latch circuit from a digital signal to an analog signal, and A digital-to-analog converter for generating an audio signal;
A speech synthesizer including: The latch circuit has a multi-layer data structure for storing the decoded audio signal,
At least one of the data structures includes a FIFO circuit;
The speech synthesizer according to claim 1. A speech synthesis method for generating a multi-channel synthesized speech signal from speech signal data stored in a memory, comprising:
Triggering a processor with a clock signal to read the audio signal data from the memory;
The processor decoding the audio signal data to generate a decoded audio signal;
Triggering a register with the clock signal and receiving the decoded audio signal from the processor;
A plurality of sampling signals output from a plurality of timing means triggers a latch circuit at each cycle of the sampling signal, and the plurality of channels of the decoded sound are output from the register in response to each of the plurality of sampling signals. Reading the signal; and converting the decoded audio signal of the plurality of channels from a digital signal to an analog signal to generate the synthesized audio signal of the plurality of channels;
A speech synthesis method that includes The latch circuit has a multi-layer data structure for storing the decoded audio signal,
At least one of the data structures includes a FIFO circuit;
The speech synthesis method according to claim 3.

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