200412726 (1) 玖、發明說明 【發明所屬之技術領域】 本發明係關於數位聲頻廣播用收訊機、以及適用於收 訊機之低消耗電力化的有效技術，例如，和利用於具有放 大收訊信號之放大電路、以及頻率轉換之混合器的收訊信 號處理用半導體積體電路之有效技術相關。 【先前技術】 目前，無線電廣播係以AM調變方式之AM聲音廣播 、及FM調變方式之FM聲音廣播爲主流，然而，近年來 ，以數位信號傳送聲音資訊之數位聲頻廣播不斷推動實用 化。數位聲頻廣播之1個電波不但可傳送聲音資訊，亦可 傳送新聞及交通資訊等複數之服務資訊。又，爲了可從此 含有複數資訊之信號取得期望之資訊，亦會將控制資訊載 置於同一電波上執行傳送。 接收數位聲頻廣播之信號的收訊機，會依據收訊信號 含有之控制資訊，從收訊信號含有之複數服務當中，由接 受服務提供之使用者選取希望之服務並執行再生（解碼）。 然而，若爲以電池驅動數位聲頻廣播用收訊機之行動 機器的構成時，則會要求各構成構件儘量降低消耗電力。 爲了滿足此要求，收訊機應不執行希望服務以外之服務的 信號處理，且以在此期間內停止構成收訊機之放大電路及 頻率轉換電路等的動作來減少消耗電力。 傳統之數位聲頻廣播用收訊機，有人提出一種發明， -5- (2) (2)200412726 就是爲了實現收訊機之低消耗電力化，而依據收訊信號含 有之部份資料的位置資訊，切斷對RF調整器之電力供給（ 參照日本特開200 1 -69023號公報）。然而，前述公報中， 並未具體明示如何切斷對RF調整器之電力供給的方法。 又，日本特開平1 1 -3 3 1 002號公報之發明的構成上， 係從構成收訊機之特定電路區塊取得時序信號，可選擇資 料收訊之期間以外的期間，會使RF放大部、頻率轉換部 、IF放大部、AD轉換部、正交解調部、FFT差動解調部 等特定電路區塊處於非動作狀態。 然而，不論前述任何一種發明中，並未針對可同時接 收L-band及Band-Ill之頻帶信號的系統，說明選取其中 任一種頻帶信號時如何執行各電路區塊之動作控制。因此 ，對於可接收2個頻帶信號之系統並無法充份達成低消耗 電力化。 又，具有如頻率轉換部之可產生振盪信號之振盪器的 電路，電路從斷開切換至導通狀態時，振盪器之輸出達到 安定爲止需要一些時間，故起動時序必須提早，故即使採 用上述任何一種發明，結果，總計停止時間較短，而無法 充份達成低消耗電力化。 另一方面，本發明者等爲了以減少數位聲頻廣播用收 訊機之構件點數來實現小型化，除了實施RF放大部、頻 率轉換部、及IF放大部之半導體積體電路化以外，系統 控制電路亦相樣採用實施半導體積體電路化之控制器，將 該控制器、及放大收訊信號並實施頻率轉換之半導體積體 -6- (3) (3)200412726 電路（以下稱爲RFIC)，以例如lie匯流排（稱爲I2C匯流 排）之串列匯流排進行連結，並針對以控制器控制RF 1C之 收訊機進行檢討。以IIC匯流排連結控制器及RFIC之系 統，利用經由IIC匯流排從控制器對RFIC傳送命令代碼 ，可控制RFIC之動作。 然而，數位聲頻廣播之傳輸框具有如第2圖（A)所示 之構成，此框會以第2圖（B)所示之方式接著被傳送。具 有此IIC匯流排之系統，若考慮從具有此種構成之框的主 服務通道（MSC)含有之複數服務當中，選取如服務S2時 ，會解讀最前之控制資訊通道FIC檢測期望之服務S2的 位置，然後如第7圖所示，從控制制分別對RFIC傳送命 令，如在不用之服務S1之前會傳送斷開命令CMD off、在 選擇服務S2之前會傳送導通命令CMDon、又、在下一不 用服務S3之前傳送斷開命令CMD off，故可減少RFIC之 消耗電力。 然而，以IIC匯流排連結控制器及RFIC之收訊系統 時，因爲亦需傳送以指定利用斷開命令CMD of停止動作 之電路的代碼，控制器提供給RF IC之命令代碼的長度會 達到1 〇〇位元程度之長度。又，爲了針對連續傳送之複數 框的各框，使RFIC在選擇服務期間執行動作，而使RFIC 在非選擇服務期間暫時停止動作，而必須依狀況來傳送命 令。因此可知，使用IIC匯流排時，命令之傳送及處理需 要較長時間，故無法獲得充分實現低消耗電力化之效果。 (4) (4)200412726 【發明內容】 此發明之目的係提供一種控制技術，數位聲頻廣播用 收訊機係以由複數半導體積體電路所構成之電路所構成， 且利用IIC匯流排等之匯流排實施連結來實現小型化時， 可以在選擇服務之收訊期間以外之期間，容易且瞬間停止 具有放大收訊信號並實施頻率轉換之機能的半導體積體電 路之動作，利用此方式，可更有效地降低數位聲頻廣播用 收訊機之消耗電力。 此發明之其他目的係提供一種控制技術，可對應選擇 頻帶使半導體積體電路內部之電路執行動作或非動作，進 而降低總計消耗電力，又，前述半導體積體電路可放大收 訊信號且執行頻率轉換，而可接收含L-band及Band-Ill 在內之複數頻帶信號的數位聲頻廣播用收訊機則由前述前 述半導體積體電路所構成。 此發明之另一其他目的則係提供一種控制技術，可對 應期望之服務在收訊期間選擇性的使半導體積體電路內部 之特定電路執行動作或非動作，進而降低總計消耗電力， 又’半導體積體電路係構成數位聲頻廣播用收訊機且可放 大收訊信號並執行頻率轉換。 此發明之前述及其他目的、以及新型特徴，由本說明 書之說明及附錄圖面可獲得了解。 本專利申請所示之發明當中，具代表性者之槪要如下 所述。 亦即’構成數位聲頻廣播用收訊機之可放大收訊信號 -8 - (5) (5)200412726 且執行頻率轉換之半導體積體電路內，設有具有和想要執 行動作控制之內部電路爲1: 1對應關係之位元的暫存器、 以及可對應該暫存器之設定値、及對應來自系統控制器之 導通/斷開控制信號而產生以控制內部電路之動作爲目的 之信號的動作控制電路。 利用上述手段，只要利用匯流排預先將指定想要停止 動作之電路的値設定至暫存器，其後，只需來自系統控制 器之導通/斷開控制信號即可停止期望之電路的動作。而 以可對應選擇服務執行動作停止之內部電路而言，可放大 收訊信號之放大電路、及可執行收訊信號之頻率轉換的混 合器係最有效之電路。又，若動作停止對象電路含有產生 特定頻率信號之振盪電路，則可進一步獲得降低消耗電力 之效果，又，混合器會混合收訊信號及前述特定頻率信號 〇 又，以利用系統控制器設定上述半導體積體電路內之 暫存器爲目的之匯流排，可以爲串列匯流排或平行匯流排 之其中任一種。使用平行匯流排時，利用在前述暫存器設 定導通/斷開控制位元，即無需導通/斷開控制信號。此導 通/斷開控制位元之設定，亦可同時將1 : 1對應之位元設 定於內部電路，亦可單獨構成。 又，本發明之半導體積體電路，係構成可接收含有 L-band及Band-Ill之複數頻率信號的數位聲頻廣播用收 訊機，可放大收訊信號並實施頻率轉換，又，以對應選擇 頻帶使內部電路執行動作或非動作，進一步降低總計消耗 -9- (6) (6)200412726 電力。 【實施方式】 以下，參照圖面說明本發明之良好實施例。 第1圖係應用本發明之數位聲頻廣播用收訊機的構成 例。 第1圖中，1 00係接收廣播站傳送之廣播電波的天線 ，110係可自動分離第1頻帶（L-b and)之信號及第2頻帶 (Band_III)之信號的分相器（選擇共振部），121係第1頻帶 之頻率信號可通過之瀘波器，122係第2頻帶之頻率信號 可通過之濾波器，200係放大通過濾波器121、122之信 號且實施頻率轉換（降頻器）之RFIC，130係將RFIC 200 之類比輸出轉換成數位信號之AD轉換器，3 00係以數位 處理對經過AD轉換之信號實施解調、解碼之基頻解碼器 ，400係控制系統整體之系統控制器，5 00係由操作者（使 用者）對系統控制器輸入指令之鍵輸入操作部5 1 0、及確 認動作狀態之顯示部520等所構成之人機介面。 RFIC 200具有：分別將通過濾波器121、122之收訊 信號進行放大之低雜訊放大器（LNA)21 1、212 ;將利用一 方之低雜訊放大器（LNA)21 1放大之信號、及第1振盪器 221產生之振盪信號0 1進行混合並轉換成Band-Ill頻率 之信號的第1混合器23 1 ;將經過頻率轉換之收訊信號或 利用另一方之低雜訊放大器（LNA)2 12放大之收訊信號、 及第2振盪器222產生之振盪信號0 2進行混合並轉換成 -10- (7) (7)200412726 第1中間頻率之信號的第2混合器232 ;放大經過頻率轉 換之信號的固定增益放大器241及可變增益放大器242 ; 將經過放大之信號、及來自RF合成器25 1之振盪信號0 3進行混合並轉換成第2中間頻率之信號的第3混合器 2 3 3 ;以及放大經過頻率轉換之信號的放大器2 4 3。 又，RFIC 200具有：將由具有水晶振盪器之外加基 準振盪器260提供之基準振盪信號4 ref、及上述第1振 盪器22 1回饋之振盪信號進行比較，產生可使頻率一致之 控制電壓，並將其提供給第1振盪器22 1之RF合成器 251 ;以及將基準振盪信號0 ref、及上述第 2振盪器222 回饋之振盪信號進行比較，產生可使頻率一致之控制電壓 ，並將其提供給第2振盪器222之IF合成器252。合成 器25 1及252係由分頻電路或位相比較電路、充電泵、及 迴路濾波器等所構成，以回饋振盪器221、222之振盪信 號來分別構成PLL迴路。振盪器 221、222採用例如以對 應控制電壓之頻率實施振盪之電壓控制振盪器（VCO)。 又，RFIC 200具有：撖取系統控制器400提供給串 列之命令代碼的移位暫存器261;對撖取之命令進行解碼 並產生內部控制信號之命令解碼器262 ;保存對應命令代 碼之控制代碼等的控制暫存器263 ;以及對應該暫存器 263之設定値、及來自系統控制器400之導通/斷開控制信 號ΟΝ/OFF產生控制內部電路動作之信號的動作控制電路 264 〇 基頻解碼器3 00具有：對經過AD轉換器130實施轉 -11 - (8) (8)200412726 換之信號進行垂直解調並產生I信號及Q信號之垂直解調 電路3 1 0 ;對經過解調之I、Q信號執行快速傅立葉轉換 處理之FFT解調電路3 20 ;對經過FFT轉換之信號執行弗 交插處理之非交插電路3 3 0 ;以尤最解碼法實施錯誤訂IE 之維特比解碼電路3 40 ;以及利用如MPEG聲頻規格之低 位元率編碼處理對經過壓縮之資料執行伸展之低位元率壓 縮解碼電路3 5 0等。 以FFT解調電路320及維特比解碼電路340實施解 碼後之資料會提供給系統控制器400，析出控制資訊通道 部含有之控制資訊，並依據該控制資訊及由鍵輸入操作部 5 1 〇輸入之指令，執行使用者指定之服務的選擇控制。 使用者指定之服務爲音樂服務時，在維特比解碼電路 3 4〇被解碼之資料（位元流），會提供給低位元率壓縮解碼 電路35〇，並實施伸展及輸出。第1圖中並未標示，在低 位元率壓縮解碼電路35〇被伸展之音樂資料，會在DA轉 換器被轉換成類比信號，且在放大器被放大並提供給喇叭 而當成再生聲音輸出。又，在基頻解碼器3 00接受解調、 解碼處理之收訊資料當中，音樂資料以外之資料會在圖上 未標示之資料解碼器接受解碼，並顯示於顯示器5 2 0、或 圖上未標示之圖像資料顯示用監視器。 第2圖（A)係使用於數位聲頻廣播之傳輸框的構成例 。如第2圖（A)所示，傳輸框係由代表框之前頭的無信號 部NULL、以框之同步爲目的之同步通道部SYNC、含有 服務選擇及解碼上必要之資訊的控制資訊通道部FIC、以 -12- 200412726 Ο) 及含有具體服務內容之主服務通道部MSC所構成。主服 務通道部MS C最多可含有64個服務內容。主服務通道部 MSC含有之服務數並非固定，若其中有任一之服務含有 Λ 之資料量較大時，則1個框可傳送之服務數會較少。 - 又，歐洲之數位聲頻廣播規格中，對傳送速度、及對 應框之構成而如表1所示之4個傳送模式有一定之規定。 第2圖（Α)係此4個傳送模式當中之模式2之框的各通道 ^ 符號數及時間。如表1所示，模式1、2、及4之每1框 ® 的符號數爲「76」，模式3之每1框的符號數爲「1 5 3」 。又，模式1、2、及4爲每1框內之控制資訊通道部FIC 及主服務通道部MSC的符號數分別爲「3」及「72」，模 式3之FIC及MSC的符號數爲「8」及「144」。 控制資訊通道部FIC內，主服務通道部MSC含有之 服務內容的位置，以64位元單位之CU(Capacitor Unit)値 表示。 表1 傳送模 式 1框 期間 每1框之 符號數 FIC之 符號數 MSC之 符號數 NULL 期 間 SYNC 期間 FIC期 間 每 1CU 之期間 模式1 96ms 76 3 72 〜1297//s 1.25ms 3.74ms 25.96//s 模式2 24ms 76 3 72 -324 β s 312/zs 935//s 25.96//s 模式3 24ms 153 8 144 〜168//s 156//s 1.25ms 25.96//s 模式4 48ms 76 3 72 -648 β s 623//s 1.87ms 25.96//s -13- (10) (10)200412726 由表1可知，依據傳送模式之不同，其照信號期間 NULL及各同步通道部SYNC之時間長度亦不同，另一方 面，每1 CU之期間卻是各傳送模式皆相同。因此，由接 收之信號的無信號期間NULL、及同步通道部SYNC之期 間可以知道傳送模式，又，由控制資訊通道部FIC內之 CU値可以知道使用者希望之服務的位置，而以選擇該服 務內容之方式來進行控制。又，因爲控制資訊通道部FIC 內亦含有代表其爲何種傳送模式之資訊，故可從該資訊判 定傳送模式。 例如，使用者希望之服務爲第2圖所示傳輸框中之第 2個服務S2時，因控制資訊通道部FIC爲72符號、 8 64CU，故每1符號之CU値爲「12」。希望之服務S2之 前的服務只有140單元之S1，因此，控制資訊通道部FIC 內含有代表服務S1儲存於MSC內之CU値爲「〇」至「 139」、希望之服務S2儲存於MSC內之CU値爲 ^40 」至「3 3 5」的資訊，由這些資訊、FIC之符號數爲「3」 、以及每1符號之CU値爲「12」可知，希望之服務係存 在於第16個符號至第32個符號。 因此，控制器400可以配合希望之服務的收訊時序來 執行RFIC 200之動作控制（命令之傳送）。又，傳送資料 之調變上若使用差動調變時，必須從相當於使用者希望之 服務之最前符號的前一個符號開始驅動RFIC 200內部之 電路。 第3圖係構成上可依據來自控制器400之控制命令停 -14- (11) (11)200412726 止內部電路之動作的RFIC 200之動作控制電路264、及 依據該控制信號停止動作之電路的具體實施例。又，和第 1圖所示電路相同之電路，會採用相同符號並省略重複説 明。 此實施例中，暫存器263具有和想要控制動作之電路 互相1:1對應之位元。具體而言，暫存器263之第1位元 及第2位元對應於低雜訊放大器（LNA)21 1、212，第3位 元〜第5位元對應於混合器231〜23 3，第6位元及第7 位元對應於振盪器22 1、222，第8位元及第9位元對應 於合成器251、2 52，第10位元〜第12位元對應於放大 器24 1〜243。暫存器263之各位元的設定上，係利用使 用者之鍵輸入操作或電源打開時之起始設定等，系統控制 器4 00會經由IIC匯流排對RFIC 200傳送控制命令，再 由傳送命令解碼器262執行命令代碼之解碼。 動作控制電路264係由輸入上述暫存器263之各位元 的信號、及由系統控制器400提供之導通/斷開控制信號 ΟΝ/OFF之AND閘極Gl、G2、G3......所構成。又，構成 上，想要控制動作之各電路上，和電源電壓端子之間設有 電源開關SW1、SW2、SW3……，這些開關SW1、SW2、 SW3……係對應於上述AND閘極Gl、G2、G3……，利用 AND閘極Gl、G2、G3……之輸出來設定導通狀態或斷開 狀態。 具體而言，執行RFIC 200之動作時，系統控制器 400提供之導通/斷開控制信號ΟΝ/OFF爲高電平。利用此 -15- (12) (12)200412726 方式，暫存器263之各位元的信號會經由AND閘極G1、 G2、G3……提供給電源開關SW1、SW2、SW3……，對應 於暫存器263爲"1”之位元的電路之電源開關會處於導通 狀態，又，對應於暫存器263爲”1”之位元的電路之電源 開關會處於斷開狀態。又，當導通/斷開控制信號ON/OFF 被切換成低電平時，對應暫存器263之各位元的全部電路 都會停止動作，未對應暫存器263之各位元的電路（例如 ，基準振盪電路260之反向器及移位暫存器261等之控制 電路）則會繼續動作。 此實施例之RFIC 200，在接收到Band-Ill之信號時 ，以停止第4圖中附有網目之電路的動作且使其他電路執 行動作之控制命令，會由系統控制器400傳送至RFIC 200且被撖取至移位暫存器261，再由命令解碼器262設 定暫存器263之各位元。利用此方式，天線100接收到之 Band-Ill信號會在低雜訊放大器（LNA)212被放大，而在 第2混合器2 3 2被轉換成第1中間頻率之信號，然後在放 大器24 1、242被放大。此例中，因第3混合器23 3設定 爲不會成爲非動作，轉換成第1中間頻率之信號的信號， 不會在第3混合器23 3轉換成第2中間頻率之信號，而直 接以第1中間頻率之信號在放大器243放大後輸出。 又，依據構成系統之基頻解碼器的種類，有時會要求 輸入第2中間頻率之信號，此時，第3混合器23 3會執行 動作，在放大器24 1、242被放大之收訊信號，會被第3 混合器23 3轉換成第2中間頻率之信號，然後在放大器 -16- (13) (13)200412726 243放大並輸出。 接收L-band之信號時，系統控制器400會提供以只 停止低雜訊放大器（LNA)212之動作爲目的之控制命令， 設定暫存器2 6 3之各位元。利用此方式，天線1 〇 〇接收之 L-band信號，會在低雜訊放大器（LNA)211被放大，並 由第1混合器231轉換成Band-Ill頻率之信號，且由第 2混合器2 3 2轉換成第1中間頻率之信號後，由放大器 241、242實施放大，由第3混合器233轉換成第2中間 頻率之信號，再由放大器24 3放大並輸出。 使用者選取任一之頻帶，且從主服務通道部MSC含 有之服務當中選取例如第2服務S2時，因爲系統控制器 400會依據在基頻解碼器3 00執行解調之信號，從控制資 訊通道部FIC內含有之各服務的CU値而在收訊期間只執 行希望之服務S2的RFIC 200內之電路動作，且在收訊期 間不會執行其他服務的RFIC 200內之電路動作，故會產 依第6圖（B)所示時序變化之導通/斷開控制信號ON/OFF 並輸出。 如此，可利用此導通/斷開控制信號ΟΝ/OFF控制構 成RFIC 200內之動作控制電路264的AND閘極Gl、G2 、G3……，非選擇服務在收訊期間會切斷暫存器263之 各位元的信號，斷開電源開關SW1、SW2、SW3……，切 斷對控制對象之全部電路的電源而停止這些電路之動作。 其次，配合選擇服務之收訊時序將導通/斷開控制信號 ΟΝ/OFF變換成高電平，對應暫存器263之各位元的信號 -17- (14) (14)200412726 決定AND閘極G1、G2、G3……之輸出，並將其提供給 電源開關 SW1、SW2、SW3......，而使對應爲Π1Μ之位元 的電路之電源開關切換至導通狀態，故電路會復動作狀態 ，放大選擇服務之信號，實施頻率轉換，並傳送給基頻解 碼器3 00實施解調。 而且，此實施例中，即使爲非選擇服務，收訊期間內 ，基準之振盪器260仍會動作而輸出振盪信號，故在選擇 服務之開始接收的前一刻使電路執行動作，亦可正確地接 收信號。又，此實施例中，非選擇服務在收訊期間，會停 止VC 0 221、22 2及合成器251、252之動作，然而，因 爲PLL電路需要若干時間才能使迴路安定，故其構成上 ，亦可不停止VCO 221、222及合成器251、252之動作 ，而只停止低雜訊放大器（LNA)21 1、212、混合器23 1〜 233、及放大器241〜243之動作。 第5圖係採用本發明之RF 1C 200的其他實施例。此 實施例之RFIC，係以平行匯流排P-BUS取代如IIC匯流 排之串列匯流排來連結RF 1C 200及系統控制器400之方 式構成數位聲頻廣播收訊系統。此實施例之RFIC，設有 撖取系統控制器4 0 0提供之命令代碼的命令暫存器2 6 5， 此暫存器之一部份則設有以指定RFIC 200內之各電路的 動作/非動作爲目的之位元B 1〜Bn、及導通/斷開控制位 元B0 〇 此導通/斷開控制位元B 0設定爲"1 "時，只會允許位 元B 1〜Β η當中對應爲’，1Π之位元的電路執行動作。導通/ -18- (15) (15)200412726 斷開控制位元B 0設定爲π 〇 "時，則控制對象之電路全部處 於非動作狀態。控制位元ΒΟ爲”0”時，位元Β1〜Βη爲無 效，設定爲"1 M或"〇 "皆可。 因此，例如使用者選擇第2服務S2時，若如第6圖 (C)所示，系統控制器400在第1服務S1開始前將”〇”設 定於暫存器265之位元B0，而在第2服務S2開始前將 "1 π設定於位元B0，在第3服務S3開始前將"〇"設定於位 元Β0，並在最後服務Sn結束前將”1"設定於位元Β0，則 可以只接收並解調期望之服務S2。200412726 (1) 发明 Description of the invention [Technical field to which the invention belongs] The present invention relates to a digital audio broadcasting receiver and an effective technology for reducing the power consumption of the receiver, for example, and to use it with an amplified receiver. Signal amplifier circuits, and semiconductor integrated circuits for receiving signal processing of frequency-converting mixers are related to effective technologies. [Prior technology] At present, radio broadcasting is mainly based on AM sound broadcasting of AM modulation mode and FM sound broadcasting of FM modulation mode. However, in recent years, digital audio broadcasting using digital signals to transmit sound information has continued to promote practicality. . One radio wave of digital audio broadcasting can transmit not only sound information, but also multiple service information such as news and traffic information. In addition, in order to obtain desired information from a signal containing a plurality of information, control information is also carried on the same radio wave and transmitted. The receiver that receives the digital audio broadcast signal will select the desired service from the plurality of services included in the received signal and perform the reproduction (decoding) from the plurality of services included in the received signal according to the control information contained in the received signal. However, in the case of a mobile device configured to drive a digital audio broadcasting receiver with a battery, each component is required to reduce power consumption as much as possible. In order to meet this requirement, the receiver should not perform signal processing for services other than the desired service, and stop the operation of the amplifier circuit and frequency conversion circuit constituting the receiver during this period to reduce power consumption. Traditional digital audio broadcasting receivers have been invented. -5- (2) (2) 200412726 is to achieve low power consumption of receivers, and based on the location information of some data contained in the receiver signal To cut off the power supply to the RF regulator (see Japanese Patent Application Laid-Open No. 200 1-69023). However, in the aforementioned publication, the method of cutting off the power supply to the RF regulator is not specifically specified. In addition, in the constitution of the invention disclosed in Japanese Patent Application Laid-Open No. 1 1 -3 3 1 002, a timing signal is obtained from a specific circuit block constituting a receiver, and a period other than a period of data reception can be selected to cause RF amplification. The specific circuit blocks such as the frequency conversion section, the IF amplification section, the AD conversion section, the quadrature demodulation section, and the FFT differential demodulation section are in an inoperative state. However, regardless of any of the foregoing inventions, it is not described for a system that can simultaneously receive L-band and Band-Ill frequency band signals, how to perform motion control of each circuit block when any one of the frequency band signals is selected. Therefore, a system capable of receiving signals in two frequency bands cannot sufficiently achieve low power consumption. In addition, there is a circuit such as an oscillator capable of generating an oscillation signal in the frequency conversion section. When the circuit is switched from off to on, it takes some time for the oscillator output to reach stability, so the startup sequence must be early, so even if any of the above is used, According to an invention, as a result, the total stop time is short, and it is not possible to sufficiently achieve low power consumption. On the other hand, in order to achieve miniaturization by reducing the number of component points of a digital audio broadcasting receiver, the inventors have implemented a semiconductor integrated circuit other than an RF amplifier, a frequency converter, and an IF amplifier. The control circuit also uses a semiconductor integrated circuit controller, which is a semiconductor integrated circuit that amplifies the received signal and performs frequency conversion. 6- (3) (3) 200412726 circuit (hereinafter referred to as RFIC) ), Such as lie bus (referred to as I2C bus) to connect in series, and review the RF 1C receiver controlled by the controller. The system that connects the controller and the RFIC with an IIC bus, and uses the IIC bus to transmit a command code from the controller to the RFIC to control the operation of the RFIC. However, the transmission frame of the digital audio broadcasting has a structure as shown in FIG. 2 (A), and this frame is then transmitted in the manner shown in FIG. 2 (B). For a system with this IIC bus, if the service S2 is selected from the plurality of services included in the main service channel (MSC) with such a structure, the first control information channel FIC will detect the expected service S2 when it is selected. Position, and then as shown in Figure 7, from the control system to send commands to the RFIC respectively, such as before the unused service S1 will send the disconnection command CMD off, before selecting the service S2 will send the on-state command CMDon, and, the next unused The disconnection command CMD off is transmitted before serving S3, so the power consumption of the RFIC can be reduced. However, when the IIC bus is used to connect the controller and the RFIC receiving system, the code that specifies the circuit to stop the operation using the disconnect command CMD of is also transmitted. The length of the command code provided by the controller to the RF IC will reach 1 〇〇bits of length. In addition, in order to make the RFIC execute an operation during the selected service for each frame of the plural boxes that are continuously transmitted, and to temporarily stop the operation of the RFIC during the non-selected service, the command must be transmitted according to the situation. Therefore, it can be seen that when using the IIC bus, it takes a long time to transmit and process the command, so the effect of fully achieving low power consumption cannot be obtained. (4) (4) 200412726 [Summary of the invention] The purpose of this invention is to provide a control technology. The digital audio broadcasting receiver is composed of a circuit composed of a plurality of semiconductor integrated circuits, and uses IIC buses and the like. When the bus is connected to achieve miniaturization, it is possible to easily and instantaneously stop the operation of the semiconductor integrated circuit with the function of amplifying the received signal and performing frequency conversion during periods other than the reception period of the selected service. Using this method, Reduce power consumption of digital audio broadcasting receivers more effectively. Another object of the present invention is to provide a control technology that can select the frequency band to enable the circuits inside the semiconductor integrated circuit to perform actions or non-actions, thereby reducing the total power consumption. Furthermore, the aforementioned semiconductor integrated circuit can amplify the received signal and execute the frequency The digital audio broadcasting receiver capable of converting and receiving complex frequency band signals including L-band and Band-Ill is composed of the aforementioned semiconductor integrated circuit. Another object of the present invention is to provide a control technology that can selectively cause certain circuits within a semiconductor integrated circuit to perform actions or non-actions during reception, thereby reducing the total power consumption. The integrated circuit constitutes a digital audio broadcasting receiver and can amplify the received signal and perform frequency conversion. The foregoing and other objects and novel features of this invention can be understood from the description of this specification and the drawings of the appendix. Among the inventions shown in this patent application, the representative ones are as follows. In other words, the semiconductor integrated circuit that can amplify the receiving signal constituting a digital audio broadcasting receiver-8-(5) (5) 200412726 and performs frequency conversion is provided with an internal circuit having and controlling motion It is a register with a bit ratio of 1: 1, and a register that can correspond to the register, and a signal for the purpose of controlling the operation of the internal circuit corresponding to the on / off control signal from the system controller. Motion control circuit. With the above-mentioned means, as long as the bus designated by the bus to be set in advance to the register, after that, only the on / off control signal from the system controller can stop the desired circuit operation. In terms of the internal circuit that can stop the execution of the corresponding service, the amplifier circuit that can amplify the received signal and the mixer that can perform the frequency conversion of the received signal are the most effective circuits. In addition, if the operation stop target circuit includes an oscillating circuit that generates a specific frequency signal, the effect of reducing power consumption can be further obtained. In addition, the mixer will mix the reception signal and the specific frequency signal described above to set the above using a system controller. The bus for the purpose of the register in the semiconductor integrated circuit may be any one of a serial bus or a parallel bus. When using a parallel bus, the on / off control bit is set in the aforementioned register, that is, no on / off control signal is required. The setting of this on / off control bit can also set the bit corresponding to 1: 1 to the internal circuit at the same time, or it can be constituted separately. In addition, the semiconductor integrated circuit of the present invention is a digital audio broadcasting receiver capable of receiving complex frequency signals including L-band and Band-Ill. The receiver can amplify the received signal and perform frequency conversion. The frequency band enables the internal circuit to perform operation or non-operation, further reducing the total power consumption of -9- (6) (6) 200412726. [Embodiment] Hereinafter, a preferred embodiment of the present invention will be described with reference to the drawings. Fig. 1 is a configuration example of a digital audio broadcasting receiver to which the present invention is applied. In the first figure, 100 is an antenna for receiving broadcast waves transmitted from a broadcasting station, and 110 is a phase splitter (selection resonance section) that can automatically separate signals of the first frequency band (Lb and) and signals of the second frequency band (Band_III). , 121 is a wave filter through which the frequency signal of the first frequency band can pass, 122 is a filter through which the frequency signal of the second frequency band can pass, 200 is amplifying the signal passing through the filters 121 and 122 and performing frequency conversion (downconverter) RFIC, 130 is an AD converter that converts the analog output of RFIC 200 into a digital signal, 3 00 is a baseband decoder that demodulates and decodes the AD converted signal by digital processing, and 400 is a system that controls the entire system The controller, 5 00 is a man-machine interface composed of an operator (user), a key input operation section 5 10 for inputting instructions to the system controller, and a display section 520 for confirming the operation status. The RFIC 200 includes: low noise amplifier (LNA) 21 1, 212 that amplifies the received signals passing through the filters 121 and 122; signals that are amplified by one low noise amplifier (LNA) 21 1; and 1 Oscillation signal generated by the oscillator 221 0 1 The first mixer 23 1 which mixes and converts it into a signal with a Band-Ill frequency; 1 will use the frequency-converted received signal or use the other low noise amplifier (LNA) 2 12 The amplified received signal and the oscillating signal 0 2 generated by the second oscillator 222 are mixed and converted into a -10- (7) (7) 200412726 second intermediate frequency signal of the second mixer 232; the amplified passed frequency Fixed gain amplifier 241 and variable gain amplifier 242 of the converted signal; a third mixer 2 that mixes the amplified signal and the oscillating signal 0 3 from the RF synthesizer 25 1 and converts it into a signal of the second intermediate frequency 3 3; and an amplifier 2 4 3 that amplifies the frequency-converted signal. In addition, the RFIC 200 has a comparison between a reference oscillation signal 4 ref provided by a crystal oscillator plus a reference oscillator 260 and an oscillation signal fed back by the first oscillator 22 1 to generate a control voltage that allows frequency uniformity, and This is supplied to the RF synthesizer 251 of the first oscillator 22 1; and the reference oscillation signal 0 ref and the oscillation signal fed back by the second oscillator 222 are compared to generate a control voltage capable of matching frequencies, and The IF synthesizer 252 is supplied to the second oscillator 222. The synthesizers 25 1 and 252 are composed of a frequency division circuit or a phase comparison circuit, a charge pump, and a loop filter. The PLL circuits are respectively formed by feeding back the oscillation signals of the oscillators 221 and 222. As the oscillators 221 and 222, for example, a voltage controlled oscillator (VCO) that oscillates at a frequency corresponding to the control voltage is used. In addition, the RFIC 200 includes: a shift register 261 for capturing the command codes provided by the system controller 400; a command decoder 262 for decoding the captured commands and generating internal control signals; and storing the corresponding command codes. A control register 263 such as a control code; and an operation control circuit 264 corresponding to the setting of the register 263 and the on / off control signal ON / OFF from the system controller 400 to control the operation of the internal circuit. The baseband decoder 3 00 has: a vertical demodulation circuit 3 1 0 for vertically demodulating the signal converted by the AD converter 130-(8) (8) 200412726 and generating I and Q signals; FFT demodulation circuit 3 20 for performing fast Fourier transform processing on demodulated I and Q signals; non-interleaving circuit 3 3 0 for performing FFT interleaving processing on signals subjected to FFT conversion; implementation of IE by using the most decoding method Viterbi decoding circuit 3 40; and a low bit rate compression decoding circuit 3 50 that performs stretch on compressed data using a low bit rate encoding process such as the MPEG audio specification. The data decoded by the FFT demodulation circuit 320 and the Viterbi decoding circuit 340 will be provided to the system controller 400, and the control information contained in the control information channel section will be extracted, and inputted by the key input operation section 5 1 0 according to the control information Instructions to perform selection control of user-specified services. When the service designated by the user is a music service, the data (bit stream) decoded in the Viterbi decoding circuit 3 40 will be provided to the low bit rate compression decoding circuit 35 0, and the extension and output will be performed. It is not marked in the first figure. The music data stretched in the low-bit-rate compression decoding circuit 35 will be converted into an analog signal by the DA converter, and amplified by the amplifier and provided to the speaker as a reproduced sound output. In addition, among the received data that the baseband decoder 3 00 receives demodulation and decoding processing, data other than music data will be decoded by the data decoder not marked on the picture and displayed on the display 5 2 0 or the picture Unlabeled image data display monitor. Fig. 2 (A) shows a configuration example of a transmission frame used for digital audio broadcasting. As shown in FIG. 2 (A), the transmission frame is composed of a non-signal portion NULL in front of the representative frame, a synchronization channel portion SYNC for the purpose of frame synchronization, and a control information channel portion containing necessary information for service selection and decoding. FIC, -12-200412726 0) and the main service channel department MSC with specific service content. The main service channel department MS C can contain up to 64 services. The number of services contained in the main service channel MSC is not fixed. If any of these services contains a large amount of data, the number of services that can be transmitted in one frame will be less. -In the European Digital Audio Broadcasting Standard, there are certain requirements for the four transmission modes shown in Table 1 for the transmission speed and the frame configuration. Figure 2 (A) is the number of symbols and time of each channel of the frame of mode 2 among the 4 transmission modes. As shown in Table 1, the number of symbols per frame ® of Pattern 1, 2, and 4 is "76", and the number of symbols per frame of Pattern 3 is "1 5 3". In addition, modes 1, 2, and 4 are the number of symbols of the control information channel section FIC and the main service channel section MSC in each box are "3" and "72", and the number of symbols of the FIC and MSC of mode 3 are " 8 "and" 144 ". In the control information channel section FIC, the location of the service content contained in the main service channel section MSC is represented by a 64-bit CU (Capacitor Unit) 値. Table 1 Transmission mode 1 frame period number of symbols per 1 frame FIC number of symbols MSC number of null periods SYNC period FIC period 1CU period mode 1 96ms 76 3 72 to 1297 // s 1.25ms 3.74ms 25.96 // s Mode 2 24ms 76 3 72 -324 β s 312 / zs 935 // s 25.96 // s Mode 3 24ms 153 8 144 to 168 // s 156 // s 1.25ms 25.96 // s Mode 4 48ms 76 3 72 -648 β s 623 // s 1.87ms 25.96 // s -13- (10) (10) 200412726 As can be seen from Table 1, according to the different transmission modes, the NULL period of the signal period and the time length of each synchronization channel part SYNC are different. On the other hand, each transmission mode is the same for each transmission mode. Therefore, the transmission mode can be known from the NULL period of the received signal and the period of the synchronization channel section SYNC, and the CU in the control information channel section FIC can know the location of the service that the user wants to select the To control the way content is served. In addition, since the control information channel section FIC also contains information representing the transmission mode, the transmission mode can be determined from the information. For example, when the service desired by the user is the second service S2 in the transmission box shown in FIG. 2, since the control information channel section FIC is 72 symbols and 8 64CU, the CU 値 per symbol is "12". The service before the desired service S2 is only S1 of 140 units. Therefore, the control information channel section FIC contains the CU on behalf of service S1 stored in the MSC 値 from "0" to "139", and the desired service S2 is stored in the MSC CU 値 is ^ 40 "to" 3 3 5 ". From these information, the number of FIC symbols is" 3 ", and CU 値 per 1 symbol is" 12 ". It can be seen that the desired service exists in the 16th Symbols to the 32nd symbol. Therefore, the controller 400 can execute the operation control (command transmission) of the RFIC 200 in accordance with the reception timing of the desired service. In addition, if differential modulation is used for the modulation of the transmission data, the circuit inside the RFIC 200 must be driven from the previous symbol corresponding to the first symbol of the service that the user wants. Fig. 3 shows the operation control circuit 264 of the RFIC 200 which can stop the operation of the internal circuit according to the control command from the controller 400, and the circuit that stops the operation according to the control signal. Specific embodiment. In addition, the same circuit as the circuit shown in Fig. 1 will be denoted by the same reference numerals, and repeated explanation will be omitted. In this embodiment, the register 263 has bits corresponding to the circuits to be controlled in a 1: 1 relationship. Specifically, the first and second bits of the register 263 correspond to the low noise amplifier (LNA) 21 1, 212, and the third to fifth bits correspond to the mixers 231 to 23 3, The 6th and 7th bits correspond to the oscillators 22 1, 222, the 8th and 9th bits correspond to the synthesizers 251-252, and the 10th to 12th bits correspond to the amplifier 24 1 ~ 243. Regarding the setting of each element of the register 263, the user's key input operation or the initial setting when the power is turned on, etc., the system controller 4 00 will send a control command to the RFIC 200 via the IIC bus, and then send the command The decoder 262 performs decoding of the command code. The motion control circuit 264 is composed of signals input to the above-mentioned registers 263 and AND gates G1, G2, G3 of the ON / OFF control signal ON / OFF provided by the system controller 400 ... Made up. In addition, power supply switches SW1, SW2, SW3, etc. are provided between each circuit that is intended to control the operation and the power supply voltage terminal. These switches SW1, SW2, SW3, ... correspond to the AND gates G1, G2, G3, ..., use the outputs of the AND gates G1, G2, G3, ... to set the on state or off state. Specifically, when the operation of the RFIC 200 is performed, the ON / OFF control signal ON / OFF provided by the system controller 400 is at a high level. Using this -15- (12) (12) 200412726 method, the signals of the bits of the register 263 will be provided to the power switches SW1, SW2, SW3, etc. via the AND gates G1, G2, G3 ..., corresponding to the temporary The power switch of the circuit whose register 263 is "1" will be in the on state, and the power switch of the circuit corresponding to the register whose "263" is "1" will be in the off state. Also, when When the ON / OFF control signal ON / OFF is switched to a low level, all circuits corresponding to the bits of the register 263 will stop operating. Circuits that do not correspond to the bits of the register 263 (for example, the reference oscillation circuit 260) The control circuit of the inverter and the shift register 261, etc.) will continue to operate. When the RFIC 200 of this embodiment receives the signal of Band-Ill, it stops the circuit with the mesh in Figure 4 And the control command that causes other circuits to perform actions will be transmitted by the system controller 400 to the RFIC 200 and captured to the shift register 261, and then the command decoder 262 will set the elements of the register 263. In this way , The Band-Ill signal received by antenna 100 will be low noise The large mixer (LNA) 212 is amplified, and the second mixer 2 3 2 is converted into a signal of the first intermediate frequency, and then amplified by the amplifiers 24 1, 242. In this example, the third mixer 23 3 is set In order not to become non-operation, the signal converted into the signal of the first intermediate frequency will not be converted into the signal of the second intermediate frequency by the third mixer 23 3, and the signal of the first intermediate frequency will be directly amplified by the amplifier 243. In addition, depending on the type of the fundamental frequency decoder that constitutes the system, it may be required to input a signal of the second intermediate frequency, and at this time, the third mixer 23 3 will perform an operation and the amplifier 24 1 and 242 are amplified and received. The signal is converted by the third mixer 23 3 into a second intermediate frequency signal, and then amplified and output by the amplifier-16- (13) (13) 200412726 243. When receiving the L-band signal, the system controller 400 It will provide a control command for the purpose of stopping only the operation of the low noise amplifier (LNA) 212, and set the bits of the register 2 63. In this way, the L-band signal received by the antenna 1000 will be low. The noise amplifier (LNA) 211 is amplified by the first mixer 23 1 is converted into a signal of Band-Ill frequency, and is converted by the second mixer 2 3 2 into a signal of the first intermediate frequency, amplified by amplifiers 241, 242, and converted by the third mixer 233 into the second intermediate frequency. The signal is amplified by the amplifier 24 3 and output. When the user selects any frequency band and selects the second service S2 from the services included in the main service channel section MSC, because the system controller 400 will 3 00 Perform demodulated signals from the CU of each service included in the control information channel section FIC and perform only the circuit operations in the RFIC 200 of the desired service S2 during the receiving period, and no other operations will be performed during the receiving period The circuit in the service RFIC 200 operates, so the ON / OFF control signal ON / OFF that changes according to the timing shown in Figure 6 (B) is generated and output. In this way, the ON / OFF control signal ON / OFF can be used to control the AND gates G1, G2, G3, ... of the operation control circuit 264 in the RFIC 200. The non-selected service will cut off the register 263 during the reception The signal of each element turns off the power switches SW1, SW2, SW3, etc., cuts off the power supply to all circuits of the control target, and stops the operations of these circuits. Secondly, the ON / OFF control signal ON / OFF is converted to a high level in accordance with the receiving timing of the selection service, and the signal corresponding to each bit of the register 263 is -17- (14) (14) 200412726 determines the AND gate G1 , G2, G3, ..., and supply it to the power switches SW1, SW2, SW3 ..., so that the power switch of the circuit corresponding to the bit of Π1M is switched to the on state, so the circuit will resume In the operating state, the service selection signal is amplified, frequency conversion is performed, and it is transmitted to the baseband decoder 300 for demodulation. Moreover, in this embodiment, even if it is a non-selected service, the reference oscillator 260 will still operate and output an oscillating signal during the reception period, so that the circuit executes the action immediately before the start of reception of the selected service, which can also correctly receive signal. Also, in this embodiment, the non-selected service will stop the operations of VC 0 221, 22 2 and the synthesizers 251, 252 during the reception period. However, because the PLL circuit requires some time to stabilize the loop, its structure is It is also possible to stop the operations of the low noise amplifiers (LNA) 21 1, 212, the mixers 23 1 to 233, and the amplifiers 241 to 243 without stopping the operations of the VCOs 221 and 222 and the synthesizers 251 and 252. Fig. 5 shows another embodiment using the RF 1C 200 of the present invention. The RFIC of this embodiment uses a parallel bus P-BUS instead of a serial bus such as an IIC bus to connect the RF 1C 200 and the system controller 400 to form a digital audio broadcasting receiving system. The RFIC of this embodiment is provided with a command register 2 6 5 which fetches the command code provided by the system controller 4 0 0, and a part of this register is provided with the action of specifying the circuits in the RFIC 200 Bits B 1 to Bn for the purpose of non-operation and on / off control bit B 0 〇 When this on / off control bit B 0 is set to " 1 ", only bit B 1 ~ The circuit corresponding to the bit of '1' in Βη performs an action. When ON / -18- (15) (15) 200412726 OFF control bit B 0 is set to π ", all the circuits of the control target are in a non-operation state. When the control bit B0 is "0", the bits B1 to Bη are invalid and can be set to "1M" or "0". Therefore, for example, when the user selects the second service S2, as shown in FIG. 6 (C), the system controller 400 sets "0" to the bit B0 of the register 265 before the first service S1 starts, and Before the second service S2 is started, "1 π is set to bit B0. Before the third service S3 is started," 0 "is set to bit B0, and" 1 "is set to" 1 "before the end of the last service Sn. Bit B0 can receive and demodulate only the desired service S2.
又，使用IIC匯流排之第3圖所示系統時，亦可爲如 下之構成，暫存器263設有相當於第5圖所示暫存器265 之位元B 0的位元，以此位元之信號取代系統控制器4 0 0 提供之導通/斷開控制信號ΟΝ/OFF，並將其提供給AND 閘極 G1、G2、G3......來執行控制。此時，可變動若干串 列介面，例如，以串列資料之前頭位元爲"0 ”（或” 1 ”亦可） 、或前頭開始之數位元爲特定形態時立即設定或重設暫存 器263之位元B0來構成電路，而可不必等待例如100位 元之控制命令全部傳送結束，即可停止RFIC 200內之部 份電路的動作。 本專利申請所公開之發明當中具代表性者可獲得之效 果，簡單説明如下。 亦即，依據本發明，利用由複數半導體積體電路所構 成之電路來構成數位聲頻廣播用收訊機，並以IIC匯流排 等之匯流排連結來實施控制時，在選擇服務之收訊期間以 -19- (16) (16)200412726 外之期間，可容易且短時間即停止放大收訊信號且實施頻 率轉換之半導體積體電路之內部電路的動作，利用此方式 ，可有效降低數位聲頻廣播用收訊機之消耗電力。 又，可對應選擇頻帶，使構成可接收含L-band及 Band-Ill在內之複數頻率信號的數位聲頻廣播用收訊機而 可放大收訊信號並進行頻率轉換之半導體積體電路的內部 電路執行動作或非動作，利用此方式，可降低總計消耗電 力。又，對應期望之服務的收訊期間，選擇性地執行可放 大收訊信號且實施頻率轉換之半導體積體電路內部的特定 電路之動作或非動作，而具有降低總計消耗電力之效果。 以上，係利用實施例具體說明本發明者之發明，然而 ，本發明並未受限於上述實施例，只要不背離其要旨之範 圍內，當然可實施各種變化。例如，前述實施例中，使用 者希望之服務的位置計算係由系統控制器400執行，然而 ，亦可在基頻解碼器3 00設置具有該機能之電路。又，此 時，構成上，RFIC內部之電路動作的導通/斷開控制信號 ΟΝ/OFF ’可以不利用系統控制器400輸出而利用基頻解 碼器3 0 0輸出。 又，實施例中，設有以指定RFIC 200內之各電路的 動作/非動作爲目的之暫存器263，並由系統控制器400傳 送命令來執行此暫存器263之設定，然而，欲執行動作之 電路在收訊頻帶決定時即可大致固定，故其構成上，亦可 設g儲存著和設定於暫存器263之內容相同之內容（形態） 的ROM來取代暫存器263，將此ROM之內容輸入由 -20- (17) (17)200412726 AND閘極G1〜Gn所構成之動作控制電路264，由系統控 制器400對RF 1C 200以指示使ROM內之指定形態之選擇 信號、及ROM之輸出通過或阻隔爲目的之導通/斷開控制 信號 ON/OFF 〇 又，實施例之RFIC，由和混合器23 1共用之RF合成 器251將以混合器23 3混合之振盪信號提供給混合器233 ，然而，亦可另行設置和混合器23 3對應之振盪器。實施 例之RFIC中，由RF合成器251將以混合器23 3混合之 振盪信號提供給混合器23 3之理由，係因爲以混合器233 混合之振盪信號的頻率爲以混合器23 1混合之振盪信號的 頻率之整數分之1，利用分頻即可獲得。 又，實施例中，係針對應用於放大收訊信號且實施頻 率轉換之RFIC時進行說明，然而，亦可應用於RFIC及 基頻解碼器爲一體化之半導體積體電路。 産業上之利用可能性 以上之説明，主要是針對以應用於以本發明者之發明 爲背景之利用分野一數位聲頻廣播用收訊機’然而，本發 明並未受其限制，可應用於以1框含有複數資料方式傳送 數位信號之所有收訊機。 【圖式簡單說明】 第1圖係應用本發明之數位聲頻廣播用收訊機的構成 例方塊圖。 -21 - (18) (18)200412726 第2圖（A)係數位聲頻廣播用傳輸框之構成例圖，（B) 係連續傳送框時的形態圖。 第3圖係RFIC之動作控制電路及利用該控制信號停 止動作之電路的具體實施例方塊圖。 第4圖係實施例之RFIC在接收Band-III信號時被停 止動作之電路及執行動作之電路的方塊圖。 第5圖係應用本發明之RFIC的其他實施例方塊圖。 第6圖係以停止內部電路之動作爲目的而由系統控制 器提供給實施例之RFIC的導通/斷開控制信號之時序圖。 第7圖係本發明之前，以針對停止內部電路之動作爲 目的而實施檢討時，系統控制器對RFIC供給之導通/斷開 命令的時序圖。 [元件符號之說明] 1 〇 〇 :天線 1 1 〇 :分相器When the system shown in FIG. 3 of the IIC bus is used, the following configuration is also possible. The register 263 is provided with a bit equivalent to the bit B 0 of the register 265 shown in FIG. 5. The bit signal replaces the on / off control signal ON / OFF provided by the system controller 4 0 0 and supplies it to the AND gates G1, G2, G3, etc. to perform control. At this time, several serial interfaces can be changed. For example, the first bit before the serial data is "" 0" (or "1" is also acceptable), or the first bit before the first bit is a specific pattern. Set or reset temporarily. The bit B0 of the register 263 constitutes a circuit, and it is possible to stop the operation of some circuits in the RFIC 200 without waiting for the completion of transmission of a 100-bit control command, for example. The invention disclosed in this patent application is representative The effect obtained by the user is briefly explained as follows. That is, according to the present invention, a digital audio broadcasting receiver is constructed by using a circuit composed of a plurality of semiconductor integrated circuits, and implemented by a bus connection such as an IIC bus. During control, during the period of receiving the selected service, except for -19- (16) (16) 200412726, it is easy to stop the operation of the internal circuit of the semiconductor integrated circuit that amplifies the received signal and performs frequency conversion in a short time. In this way, the power consumption of digital audio broadcasting receivers can be effectively reduced. In addition, corresponding frequency bands can be selected so that the structure can receive complex frequency including L-band and Band-Ill. The internal circuit of the semiconductor integrated circuit that can amplify the received signal and perform frequency conversion by using a receiver for digital audio broadcasting of a signal performs an action or non-action. This method can reduce the total power consumption. In addition, corresponding to the desired service During the receiving period, the action or non-action of a specific circuit inside the semiconductor integrated circuit that can amplify the received signal and perform frequency conversion is selectively performed, thereby having the effect of reducing the total power consumption. The foregoing is a detailed description of the embodiment using the embodiment. The invention of the inventor, however, the present invention is not limited to the above-mentioned embodiment, and various changes can of course be implemented as long as it does not deviate from the gist thereof. For example, in the foregoing embodiment, the location calculation of the service that the user desires is made by The system controller 400 executes, however, it is also possible to set a circuit having this function in the baseband decoder 300. Also, at this time, the on / off control signal ON / OFF of the circuit operation in the RFIC may not be configured. Output from the system controller 400 and output from the baseband decoder 300. Further, in the embodiment, a designated RFIC 200 is provided. The register 263 for the purpose of the operation / non-operation of each circuit in the circuit is executed by the system controller 400 to execute the setting of the register 263. However, the circuit to perform the operation may be determined when the receiving frequency band is determined. It is roughly fixed, so in its structure, a ROM that stores the same content (form) as the content set in the temporary register 263 can also be set instead of the temporary register 263, and the content of this ROM is input from -20- (17 ) (17) 200412726 The operation control circuit 264 composed of AND gates G1 ~ Gn is used by the system controller 400 to RF 1C 200 to instruct the selection signal of the specified form in ROM and the output of ROM to pass or block. ON / OFF control signal ON / OFF 〇 In addition, in the RFIC of the embodiment, the RF synthesizer 251 shared with the mixer 23 1 provides the oscillation signal mixed with the mixer 23 3 to the mixer 233, however, it may be separately An oscillator corresponding to the mixer 23 3 is set. In the RFIC of the embodiment, the reason that the RF synthesizer 251 provides the oscillation signal mixed with the mixer 23 3 to the mixer 23 3 is because the frequency of the oscillation signal mixed with the mixer 233 is the frequency mixed with the mixer 23 1 The integer of one part of the frequency of the oscillation signal can be obtained by frequency division. In the embodiment, the RFIC is applied to amplify the received signal and perform frequency conversion. However, it can also be applied to a semiconductor integrated circuit in which the RFIC and the baseband decoder are integrated. Industrial Applicability The above description is mainly directed to the use of the field-digital audio broadcasting receiver with the background of the inventor's invention. However, the present invention is not limited to this and can be applied to Box 1 contains all receivers that transmit digital signals in the form of plural data. [Brief Description of the Drawings] Fig. 1 is a block diagram showing an example of the configuration of a digital audio broadcasting receiver to which the present invention is applied. -21-(18) (18) 200412726 Fig. 2 (A) Structure example of coefficient-bit audio broadcasting transmission frame, (B) is a morphology diagram of continuous transmission frame. Fig. 3 is a block diagram of a specific embodiment of the operation control circuit of the RFIC and a circuit for stopping the operation by using the control signal. Fig. 4 is a block diagram of a circuit in which an RFIC of the embodiment is stopped when receiving a Band-III signal, and a circuit that executes the operation. FIG. 5 is a block diagram of another embodiment of the RFIC to which the present invention is applied. Fig. 6 is a timing chart of the ON / OFF control signal provided to the RFIC of the embodiment by the system controller for the purpose of stopping the operation of the internal circuit. Fig. 7 is a timing chart of the ON / OFF command supplied to the RFIC by the system controller when the review was performed for the purpose of stopping the operation of the internal circuit before the present invention. [Explanation of component symbols] 1 〇 〇: antenna 1 1 〇: phase splitter
1 2 1、1 2 2 :濾波器 130 : AD轉換器 200 ： RFIC 2 1 1、2 1 2 :低雜訊放大器 221、222:振盪器 23卜232、233:混合器 241 、 242 > 243 :放大器 25 1、252 :合成器 -22- (19) (19)200412726 260 :基準振盪器 261 :移位暫存器 2 6 2 :命令解碼器 263 、 265 :暫存器 263 :控制暫存器 264 :動作控制電路 3 00 :基頻解碼器 3 1 0 :垂直解調電路 320: FFT解調電路 3 3 0 :非交插電路 3 40 :維特比解碼電路 3 5 0 :低位元率壓縮解碼電路 400 :系統控制器 5 0 0 :人機介面 5 1 0 :鍵輸入操作部 5 20 :顯示器 -23-1 2 1, 1 2 2: Filter 130: AD converter 200: RFIC 2 1 1, 2 1 2: Low noise amplifier 221, 222: Oscillator 23, 232, 233: Mixer 241, 242 > 243 : Amplifier 25 1, 252: Synthesizer-22- (19) (19) 200412726 260: Reference oscillator 261: Shift register 2 6 2: Command decoder 263, 265: Register 263: Control register 264: motion control circuit 3 00: baseband decoder 3 1 0: vertical demodulation circuit 320: FFT demodulation circuit 3 3 0: non-interleaved circuit 3 40: Viterbi decoding circuit 3 5 0: low bit rate compression Decoding circuit 400: System controller 5 0 0: Human machine interface 5 1 0: Key input operation unit 5 20: Display-23-