TW200411949A - Optoelectronic integrated circuit device and manufacturing method thereof - Google Patents

Abstract

The present invention discloses an optoelectronic integrated circuit device with high lattice matching and manufacturing method thereof. The device has a silicon dioxide layer to dispose the diodes and transistors on the substrate selectively, which is mainly to form a silicon dioxide layer on the substrate, and the said silicon dioxide layer is selectively etched, so as to define the predetermined region of diodes and the predetermined region of FET. Next, grow diodes, diode passivation layer and transistor. The said passivation layer can isolate the diode and transistor.

Description

200411949

[Technical field to which the invention belongs] The present invention relates to an optoelectronic integrated circuit (0EIC) element and a method for manufacturing the same, and particularly to an effective diode and transistor isolation and Optoelectronic integrated circuit (0EIC) element with high lattice match and manufacturing method thereof. [Previous technology] Optoelectronic integrated circuit (0EIC) is a single-chip integrated optical element that includes electronic circuit parts and optical circuit part elements on a substrate, and is a key device for the rapid and massive development of optical transmission systems. . In the structure of optoelectronic integrated circuit (OEIC) devices, gallium nitride (GaN) that emits short-wavelength blue light is generally used as the light-emitting layer, and is formed on a gallium arsenide (GaAs) substrate. In order to achieve the interconnection of electronic signals and optical signals in the light-emitting layer. In the current optical element technology, the mismatch of the lattice constants of the epitaxial layers has been a bottleneck that causes the luminous efficiency and service life of the optoelectronic integrated circuit elements to be difficult to improve. Taking gallium nitride (GaN) as an example, gallium nitride (GaN) is a very important wide bandgap semiconductor material, which can be used as a photovoltaic integrated circuit element for green light, blue light to ultraviolet light. However, the growth of buik GaN has been difficult, so most of GaN is currently growing with sapphire.

GaP, InP, gallium arsenide (GaAs) or silicon carbide (SiC). In terms of lattice constant, gallium nitride (GaN) is

0769-9103TlVF (nl); VTERA.91 -011. ^; Phoel ip he.ptd page 5 200411949 V. Description of the invention (2) 3.180A, while the gallium arsenide (GaAs) is 5.653 A, the difference between the two Near 1.473 A. With such large lattice constants, the formation of gallium vaporized (GaN) on a GaAs substrate can cause serious lattice defects. Ο On the other hand, using GaAs as a substrate When a gallium nitride (GaN) light-emitting layer is formed thereon, due to the high crystallinity of gallium nitride (GaN), a high deposition temperature is required (more than 10) when it is formed by MOCVD. 0 0, depending on the deposition process). At this time, the gallium tritide (GaAs) substrate will produce an image of arsenic el iminat ion due to high temperature (at about 300, Kun will generate gasification). While removing the surface), causing surface dimples. These depressions are generated between the Shi Shenhua (G a As s) substrate and the nitrided (G a N) light emitting layer. Therefore, it is difficult to control the process temperature for forming high crystallinity gallium nitride (GaN) on the substrate using GaAs as the substrate, so as to avoid the phenomenon of depression at the interface. However, in order to solve the above problems, a photovoltaic integrated circuit element having a buffer layer is proposed. A gallium nitride (GaN) is formed between the substrate and GaN as a buffer layer, and a buffer layer having a lattice constant close to the substrate can provide a nucleation position to facilitate GaN nucleation and growth to form the same crystal. Structure to improve the crystallinity of GaN. Although GaN is used as the buffer layer, the phenomenon of interface depression caused by arsenic el imination on the surface of the gallium arsenide (GaAs) substrate is partially solved, but the relationship between the gallium arsenide (GaAs) substrate and the GaN buffer layer The lattice constants still differ by about 13.8%, and the lattice mismatches are still quite large. So in gallium arsenide (GaAs)

0769-9103TW (nl); \ TERA-91-01MW; Phoelip he.ptd page 6 200411949

At the interface between the substrate and GaN, ^ ^, there will be line defects (defects) of quite two densities, reducing the luminous efficiency and shortening the service life. In US Patent No. 6,355,945, a photovoltaic integrated circuit element having zinc oxide as a buffer layer is also disclosed. Zinc oxide (ZnO) is used as a buffer layer to form a gallium arsenide (GaAs) substrate and GaN. between. Please refer to FIG. 1, which shows a cross-sectional structure view of a conventional photovoltaic integrated circuit element having a zinc oxide (Zn〇) buffer layer. Production of a light-emitting diode element epitaxially on a gallium arsenide (GaAs) substrate 11 丨 1 () (optical integrated circuit circuit element optical circuit part), and a metal semiconductor field effect transistor

(metal-semiconductor field effect transistor, MESFET) 160 (electronic circuit part of the optoelectronic integrated circuit element). The 'No. 1 2 0' in the light-emitting monopolar element 110 shows a buffer layer composed of zinc oxide (ZnO). Its main function is to reduce the gap between the substrate 100 and the subsequent epitaxial layer (n-GaN) 130. Lattice mismatch and prevent gallium nitride (GaN) from being formed directly on the gallium halide (GaAs) substrate, resulting in the appearance of arsenic elimination.

This method completely solves the phenomenon of interface depression caused by arsenic elimination on the surface of the gallium arsenide (GaAs) substrate, and uses zinc oxide (ZnO) to match the crystal lattice with gallium nitride (GaN). However, it uses gallium arsenide (GaAs) as the substrate, and the lattice constants of the oxides (ZnO) and gallium arsenide (GaAs) are 3.25 A and 5.653, respectively. The lattice matching gap is still quite large, so The problem of relatively high-density line defects still exists, and the density of their dislocations is also quite high. Once these differential lines extend into the first type of restraint layer, the characteristics of the components will be seriously damaged.

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Make the phase effect of each light-emitting element of this crystal, or provide a cathodic body electric cat day [the light of the crystal lattice between the circuit elements of the invention within this invention has perfect matching properties (G a A s ) To greatly reduce the efficiency and reduce the use of stupid crystal layers, the lattice is too close in the conventional photoelectricity, or the two connecting wires touch the two by mistake. In order to solve the diode and circuit components effectively, the exemption The purpose of the crystal lattice between the layers] is to mention its manufacturing method, and the mismatch (lattice crystal photoelectricity of the photovoltaic body is clear. The second purpose is that the electrical circuit components are substrates to avoid Kun costs. In addition to the above-mentioned transistor, the body is not short of the above-mentioned characteristics. Because of the urgent need for the connection in the component, the isolated and well-known one is provided with a high lattice to reduce the diode mismatch. Circuit components. Provide a silicon and its manufacturing method based on gallium (GaAs). Based on this, the photovoltaic integrated circuit has a better improvement effect. Because of a pole body and an electric wire, an electric field is easily generated. The main purpose of the invention is to solve the problem of light interference of the plane lattice matching, and the second pole is better. The problem of reducing line defects in the epitaxial layers of the matched optoelectronic integrated device is to provide a high lattice of the substrate. The problem caused by replacing the gallium arsenide plate with silicon and the object of the present invention is to effectively isolate the diode. The component and the transistor component are ensured to be connected only by a connecting wire without causing any interference with the component, or the connection wire mishaps happen. In order to achieve the above-mentioned object, the photoelectric integrated circuit element of the present invention with high lattice matching is mainly directed to the optical circuit part (diode) of the photovoltaic integrated circuit element. The diode includes a substrate and has First lattice constant

200411949 V. Description of the invention (5): A first multilayer buffer layer is provided on the surface of the substrate, wherein the lattice constant of the first multilayer buffer layer exhibits a gradient change, which is determined by the bottom of the first multilayer buffer layer. The above-mentioned first lattice constant gradually changes to a second lattice constant on the surface of the first multilayer buffer layer; a second multilayer buffer layer is disposed on the surface of the first multilayer buffer layer, wherein The lattice constant of the second multilayer buffer layer exhibits a gradient change, and the second lattice constant on the bottom of the second multilayer buffer layer gradually changes to one of the third on the surface of the second multilayer buffer layer. A lattice constant; a first type restraint layer provided on the surface of the second multilayer buffer layer and having a third lattice constant; and an active layer provided on the surface of the first type restraint layer; a second type restraint A layer is disposed on the surface of the active layer; a first type electrode is disposed on the active layer and a second type electrode is disposed on the second type tie layer.

The present invention includes a first multi-circuit element as a substrate, and the first substrate ’s first approximation to the “lattice lattice constant”, the lattice constant and the first characteristic layer are buffered optically, and the multi-layer and multi-layer slow constants are closer to each other between the layer and the second The crystal layer of the buffer layer of the circuit part is incremented or transferred to the second layer. A feature of the present invention is that a multilayer buffer layer and a lattice with a current gradient constant and a lattice constant are two layers. A type of restraint is used to reduce the constant lattice constant of the light-emitting lattice near the first multilayer. The buffer layer lattice is often used between the first layer%. One more buffer layer and one less multilayer buffer layer (< punch layer) are set at The number of the first-type binding layer of the photodiode diode shows a gradient change, and the number of crystals of the first multilayer buffer layer that is close to the lattice constant of the substrate is slightly close to that of the second multilayer buffer layer. Two multi-layer buffer layers are provided at the first and second multi-layer buffer layers of the second multi-layer buffer layer.

200411949 Description of the 5 'invention (6) The lattice constant is increased or decreased again to approach the first-, so that the second layer of the slower lattice constant near the first-type binding layer is slightly similar to the lattice constant of the first-type binding layer . Based on the second aspect of the present invention, the second aspect of the present invention is to form boron phosphide (BP) as a first buffer thereon, a silicon substrate, a (GaAs) substrate, and a second substrate thereon. As a buffer, gallium arsenide forms a first type of binding layer (gallium nitride (GaN)), which is connected to the upper layer. The chemical layer and the second type of restraint are based on the purpose of the present invention. The present invention is a #selective arrangement of a diode and a transistor on the substrate. Engraved above: Oxygen: Shiji fixed area and field effect transistor predetermined area. Continuing in the "area: sequential growth of a diode, a protective layer of a diode and a transistor, wherein the layer can be used to isolate the diode and the transistor as an insulation. A" "According to the purpose of the present invention-and two ' The substrate is, for example, carbonized sand (3C Si), the first multilayer buffer layer is, for example, Bχ (^ (ΐχ) ρ, the upper two multilayer buffer layers are, for example, InwGawN, and the second type binding sound is, for example, gallium nitride (GaN) -based compounds. In this way, the first lattice constant & is approximately 4.32 A, the second lattice constant is approximately 4.538 A, and the upper third lattice constant is approximately 4.51 A.) ^ According to In the present invention, the substrate is, for example, silicon (Si), the first multi-layer buffer layer is, for example, BxGa ^ p, the second multi-layer buffer layer is, for example, IrVzGazN, and the first type tie layer is, for example, gallium nitride. (GaN) -based compound. Thus, the first lattice constant is approximately 5.43A, and the second

0769-9103TW (nl); VrERA-91.011-TlV; Ph〇eiip he < ptd page 10 200411949

V. Description of the invention (7) '~ --I crystal, the constant is approximately 4.538 people, and the third lattice constant is 4.51 A. According to the present invention, the substrate is, for example, gallium phosphide (GaP), which is the least The f buffer layer is, for example, the second multilayer buffer layer, such as ^ awN, and the first type tie layer is, for example, a gallium nitride (GaN) system. This is not true. The first lattice constant is approximately 5.45α, The second lattice constant is approximately 4.538 A and the third lattice constant is approximately 4.51 A. According to the present invention, the buffer layer may be composed of more than one material. The substrate is, for example, gallium arsenide. (GaAs), the first multilayer buffer layer is, for example, a stacked layer of GaAs (Buy) Py and Ma (Bux) ρ, the third multilayer, the buffer layer is, for example, InwGawN, and the first type tie layer is, for example, It is a gallium nitride (GaN) -based compound. As such, the first lattice constant is approximately 5.65 A, the second lattice constant is approximately 4. 5 3 8 A, and the third lattice constant is approximately 4.51 A. The fraction of the GaAs (iy) Py in contact with the BxGa㈣p has a similar lattice constant, that is, the surface of the GaAs (h) and the bottom of the GaAs (h) have a fourth crystal. The constant is approximately 5. · aa. According to the present invention, the above-mentioned substrate is silicon, the above-mentioned utilizing at least one multilayer buffer layer may be one layer, and is composed of one material, such as boron phosphide (Bp) (IGamP, χ-1), and the first-type binding layer is, for example, It is a gallium nitride φ (GaN) -based compound. The method for manufacturing a photovoltaic integrated circuit element according to the present invention includes at least the following steps:

200411949 V. Description of the invention (8) (1) Provide a substrate on which a dioxide layer is formed; (2) Selectively etch the above silicon dioxide layer to define a predetermined area of the light emitting diode and a field effect power A predetermined region of the crystal; (3) sequentially forming at least one buffer layer, a first-type binding layer, an active layer, and a second-type binding layer on the predetermined region of the light-emitting diode to form the photovoltaic element The light-emitting diode part; (4) forming a protective layer, conformably attached to the above light-emitting diode part and part of the above-mentioned dioxide layer; (5) forming an ion-valued area in a field-effect transistor Predetermined area, engraved / stopped layer, remove the above-mentioned ionic value distribution area of the stone oxide layer; the above-mentioned secondary ion implantation · Vkl sub-Λ distribution area; the above-mentioned ion implantation area, and in the layer, then form- On the gate oxide layer; listen to the gate oxidation (7) to the above-mentioned protective layer for the selection of the above-mentioned protective layer, the active layer is the protective layer on the ㈣stop layer; 11 is etched, leaving the silicon dioxide (8) formed above to form a flute-boundary 丨 丨 the first electrode of the type described above: ㈠ (9) forming a circuit connection on the above-mentioned and second type binding layers, and the circuit is based on the above-mentioned protective layer / number; the type electrode and the above source electrode, and on top of the present invention; the first electrode Body separated. The following is a detailed description of the preferred implementation ^, the features and advantages can be more obvious and easy to understand, and in conjunction with the attached drawings, detailed description is as follows [Embodiment]

200411949 V. Description of the invention (9) In the following, please refer to Fig. 2, Fig. 3 and Fig. 4 of the photovoltaic integrated circuit 70 sectional views' to explain the present invention in detail. First, please refer to FIG. 2. The photovoltaic integrated circuit element of the present invention includes at least: a substrate 200, a first multilayer buffer layer 220 disposed on the surface of the substrate 200, and a first multilayer buffer layer 220 disposed on the surface of the first multilayer buffer layer 220. A second multilayer buffer layer 222, a first type tie layer 230 provided on the surface of the second multilayer buffer layer 222, and an active layer 250 provided on the surface of the first type tie layer 230,

A second-type binding layer 232 is disposed on the surface of the active layer 250; a first-type electrode 242 is disposed on the second-type binding layer and a second-type electrode 24o is disposed on the active layer. The photovoltaic integrated circuit element also includes a field effect transistor (FET) 260 having a source 270, an electrode 272, and a gate 280 on the substrate 200 as part of its electronic circuit. The line 2 90 is connected to a part 31 of the optical circuit (light emitting diode). The field effect transistor system and the light emitting diode are formed on the same substrate and have a space. Among them, the first multilayer buffer layer 220 can be formed by adjusting a single composition according to different composition ratios. The first multilayer buffer layer 320 of the photovoltaic integrated circuit element of the present invention may also be composed of more than one type, and each composition is adjusted according to different composition ratios to form a first multilayer buffer layer 3 20 (consisting of 321 and 323) of various compositions. As shown in Figure 3. The first multilayer buffer layer 420 of the photovoltaic integrated circuit element of the present invention may also be composed of a single composition, as shown in FIG. In the following, the characteristics of each layer of the optical circuit (light-emitting diode) of the element are described using the photovoltaic integrated circuit element (FIG. 2) with the first multilayer buffer layer 220 of the single composition in the embodiment of the present invention as an example.

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The substrate 200 has a first lattice constant (C1). The lattice constant of the first multi-layer 22 () exhibits a grading change, and the first lattice constant (C1) at the bottom of the first multi-layer ^^ 2 is gradually changed to the first multi-layer = The surface of the layer 220 has a second lattice constant (C2). In other words, the lattice constant of the first multilayer buffer layer 200 near the substrate 200 is slightly similar to the lattice constant of the substrate 200, and the lattice constant is further increased or decreased to approach the lattice of the second buffer layer 222. The constants are such that the lattice constant of the first multilayer buffer layer 220 near the second buffer layer 222 is slightly similar to the lattice constant of the second buffer layer 222. In short, the lattice constant of the first multilayer buffer layer 22 is gradually changed from the first lattice constant (ci) to the second lattice constant (C2). The gradient change of the lattice constant of the first multilayer buffer layer 220 can be achieved by, for example, adjusting the composition ratio of the multiple buffer layers.

In addition, the lattice constant of the second multilayer buffer layer 2 2 2 shows a gradient change, and the second lattice constant (C2) at the bottom of the second multilayer buffer layer 222 gradually changes to the surface of the second multilayer buffer layer 222. Has one of the third lattice constants (C3). In other words, the lattice constant of the second multi-layer buffer layer 222 near the first multi-layer buffer layer 22 is slightly similar to that of the first multi-layer buffer layer 22, and the lattice constant is further increased or decreased to Approaching the lattice constant of the first type binding layer 230 makes the lattice constant of the second multilayer buffer layer 222 close to the first type binding layer 230 and the lattice constant of the first type binding layer 23 slightly closer. In short, the lattice constant of the second multilayer buffer layer 222 is gradually changed from the second lattice constant (C2) to the third lattice constant (C3). The gradient of the lattice constant of the second multilayer buffer layer 222 can be achieved by adjusting the composition ratio of the multiple buffer layers, for example. Furthermore, the first type of binding layer 2 2 2 has a

200411949 V. Description of the invention (11) Tri-lattice constant (C3) 〇 The following figures are used in conjunction with Figures 2 and 3 to illustrate examples of material combinations applicable to the layers of the present invention.

Example 1: As shown in FIG. 2, the substrate 200 may be silicon (si), the first multilayer buffer layer 220 may be BxGa (1-χ) ρ, and the second multilayer buffer layer 222 may be IiiyGa ^ N In addition, the first type tie layer 230 may be a gallium nitride (GaN) -based compound. As such, the first lattice constant (C1) is generally 5.43A, the second lattice constant (C2) is approximately 4.538 A, and the third lattice constant (C3) is approximately 4.51. That is to say, 'the substrate 200 has a lattice constant (ci) 5.431A, and the lattice constant of the first multilayer buffer layer 220 stacked on the substrate 200 is (C1) 5.431 Λ (with the lattice constant of the substrate 200) (Matching) gradually changes into a surface layer with (C2) 4.538A. Next, the crystal constant of the second multilayer buffer layer 222 stacked above the first multilayer buffer layer 220 is (C2) 4.538 A (the lattice constant of the first multilayer buffer layer 2 2 0 surface layer). (Matching) gradually changes into a surface layer with (C3) 4.51A. Finally, the lattice constant of the first type tie layer 230 stacked above the second multilayer buffer layer 222 is (C3) 4.51 A (which matches the crystal constant of the surface layer of the second multilayer buffer layer 222). Among them, the X of BxGa (ix) p is between 0. 022 and 1, and the y of InyGa and yN is between 0 and 0.059. Example 2: As shown in FIG. 2, the substrate 200 may be silicon carbide (3C-Si), the first multilayer buffer layer 220 may be BxGa + nP, and the second multilayer buffer layer 222 may be IriyGa ^ yN. The first-type tie layer 230 may be a gallium nitride (GaN) -based compound. In this way, the first lattice constant (C1) and the second lattice constant are 4.538A, and the third lattice constant (c3) is approximately 4.51A. That is, the substrate 200 has a lattice constant (ci) of 4.32, and is stacked on the substrate 200.

200411949 V. Description of the invention The lattice constants (C1) and (C2) of the first multilayer buffer layer 220 of (12) are maintained at 4.538A. Next, the lattice constant of the second multilayer buffer layer 222 stacked above the first multilayer buffer layer 220 is gradually gradient from the bottom layer with (C2) 4.538A (matching the lattice constant of the surface layer of the first multilayer buffer layer 220). The surface layer is changed to (C3) 4.51 A. Finally, the lattice constant of the first type binding layer 230 stacked on the second multilayer buffer layer 222 is (C3) 4.51A (the same as that of the second multilayer buffer layer 222 surface layer). Lattice constant match). Among them, the y of inyGai_yN is between 0 ~ 0 · 0 5 9.

Example 3 As shown in FIG. 2, the substrate 200 is, for example, gallium phosphide (GaP), the first multilayer buffer layer 220 is, for example, BxGan_x) P, and the second multilayer buffer layer 222 is, for example, InxGai_xN, and the first type The tie layer 230 is, for example, gallium nitride (GaN)

Department of compounds. As such, the first lattice constant (C1) is approximately 5.45 a, the second lattice constant (C2) is approximately 4.538A, and the third lattice constant (C3) is approximately 4.51A. In other words, the substrate 200 has a lattice constant (C1) 545a. The lattice constant of the first multilayer buffer layer 220 stacked on the substrate 200 is determined by the underlying layer (C1) 5 · 45A (with the lattice of the substrate 200). Constant matching) gradually changes into surface layer with (C2) 4.538A. Next, the lattice constant of the second multilayer buffer layer 222 stacked above the first multilayer buffer layer 220 is (c2) 4 · 538α (matching the lattice constant of the surface layer of the first multilayer buffer layer 22). Gradual change into surface layer with (C3) 4.52 Α. Finally, the lattice constant of the first type tie layer 23o stacked on top of the second multilayer buffer layer 22 / is ((: 3) 4.51 Α (lattice constant with the surface layer of the second multilayer buffer layer 222 Same). Among them, X of BxGau-x) P is about 0 ~ 1. ′, Example 4: As shown in FIG. 3, according to the present invention, the first

200411949 V. Description of Invention (13)

Photoelectric integrated circuit elements of the layer buffer layer 320. The substrate 300 is, for example, gallium arsenide (GaAs), and the first multilayer buffer layer 320 has stacked layers 321 and 323 composed of two different ratios, such as GaAsy) and BxGan_x. The second multilayer buffer layer 322 is, for example, inzGa ^ N, and the first type tie layer 330 is, for example, a gallium nitride (GaN) -based compound. As such, the first lattice constant (c 1) is approximately 5.65 A, the second lattice constant (C2) is approximately 4.538 A, and the third lattice constant (C3) is approximately 4.51A. The portion where GaAsyPw contacts BxGa (1-x) P has a slightly similar lattice constant ', that is, the GaASyP ^ y surface and the bottom of BxGa (1_x) P have a fourth lattice constant (C4) of approximately 5.45 A. That is, the substrate 300 has a lattice constant (ci) of 5.653 A, and the lattice constant of the GaAsy pi-y first multilayer buffer layer 321 stacked on the substrate 300 is determined by the bottom layer with (C1) 5.653A (with the substrate 300). (Lattice constant matching) gradually changes into a surface layer with (C4) 5.45 Α. The lattice constant of the first multilayer buffer layer 323 stacked above the first multilayer buffer layer 321 of GaASyP ^ y is (C4) 5.45 A (the lattice constant of the surface layer of the first multilayer buffer layer 321 of GaASyPh). The same) gradually changes into a surface layer with (C2) 4.5 38 A. Then, the lattice constant of the second multilayer buffer layer 322 stacked on the first multilayer buffer layer 323 is composed of (C2) 4.538A (and BxGa (1_x) P surface crystal of the first multilayer buffer layer 323). Lattice constant matching) Gradual gradient change into surface layer (C3)

4.51 A. Finally, the lattice constant of the first type binding layer 330 stacked on the second multilayer buffer layer 306 is (¢ 3) 4.51 A (matching the lattice constant of the surface layer of the second multilayer buffer layer 322). Among them, the BxGa (h) p is in the range of the laborers ’, and the z of Ir ^ GahN is in the range of 0.059 ~ 0, and the y of GaAs (buy) py is 丄. Example 5: As shown in FIG. 4 ′ Photoelectric integrated circuit element according to the present invention

200411949

The composition is composed of 400 substrates of boron phosphide (BP). The stack is made of gallium nitride (G a N) -based compounds. The first multi-layer buffer layer 420 can also be made of single silicon buffer layer (Si). 42 ° can be laminated, and there are 430 cases of the first type of binding layer: The above-mentioned photovoltaic body of the present invention _ includes an embodiment that uses a diode to protect the nu ?, which can further include a circuit portion (light emitting diode) i electric ;; 2 electric integrated circuit elements, the optical electrical connection of the optical circuit part: two = :: part (field effect transistor) 'and its; Man: separated from its light emitting diode 1 to avoid short circuit of the element. The embodiment is as follows. A substrate 500 is provided. This substrate may be a Shi Xi substrate. Next, 'L' forms a silicon dioxide layer 502 with two zirconiums, as shown in FIG. 5a. Select a region for the etch stop layer 502 for the dioxide dioxide layer 502. 5 61 Ambipolar · Fast Diode Predetermined Area 511 and Field Effect Transistor Predetermined = Then, a rolled silicon layer 502 is etched to define a light emitting diode. == A first buffer layer 420 is formed on the light-emitting diode predetermined region 511 and the partialization region 3 as shown in FIG. 5b. The first buffer sound 4 丄 is a stacked layer composed of phosphorus: dagger boron (BP). A first type binding layer 53, an active layer—and a second type 532 layer are sequentially formed on the boron phosphide (BP) buffer: 420 to form the light-emitting diode of this photovoltaic integrated circuit element. Part = 10 'as shown in Figure 5c. A 3 SiO 2 layer is formed on the above-mentioned light-emitting diode portion 51O as a protective layer 504 'and is compliantly attached to the light-emitting diode 51G. Then, ion implantation is performed on the hair substrate of the field effect transistor predetermined region 561 to form an ion value distribution region 562. Again

200411949 V. Description of the invention (15) ---------- Broken substrate 5 0 0 is a narrative legend like a 'xj stop layer for silicon dioxide layers 502a and 5-2b to be removed Etching to expose the ion implanted areas 562a and 562b, as shown in FIG. 5d, the ion implanted areas 562a and 562b are again implanted with ion implant (1011 implantat10n), and the ion implanted areas 5 62a and A source electrode 570 and a drain electrode 572 are formed on 562b, respectively. A gate oxide layer 582 is formed on the silicon substrate 500, and a gate electrode 580 is formed thereon, as shown in FIG. 5e. Subsequently, the second-type restraint layer 532 and the active layer 550 are used as etching stop layers to etch the protective layer 504 on the second-type restraint layer 532 and the active layer 550. Then, a second type electrode 540 is formed on the first type tie layer 532, and a first type electrode 542 is formed on the active layer 550 'as shown in FIG. 5f. Finally, a line 59 connecting the first type electrode 542 on the active layer 55 and the field effect transistor source 57 is formed. The line 59 is separated from the light-emitting diode 510 by a protective layer, as shown in FIG. 5g. Show. Example 7 · Using the light-emitting diode structure described in Example 1 above and the photovoltaic device circuit element manufacturing method described in Example 6 above, an effective diode and transistor with high lattice matching are obtained. The structure of the photovoltaic integrated circuit element is shown in FIG. 6. The following describes a preferred embodiment of forming one of the BxGa (Bu X) P first multilayer buffer layers 22 and 321. First, the substrate 2000 can be cleaned with an appropriate chemical solution, and then the substrate 2000 is heated to an appropriate temperature in a 4 atmosphere, such as 900 ~ 1180 ° C, preferably 1 030. (: Using halide vapor phase epitaxy, using H2 as carrier gas, boron chloride (BC13), trimethyl gallium (TMG), and vaporized phosphorus ( PC13) or boron gas (BC13), trimethyl gallium (tr imethy 1 gal 1 ium; TMG) and phosphine (PH3) as precursors

0769-9103TWF (nl); VTERA-91-011-TW; Phoelip he.ptd page 19 200411949 V. Description of the invention (16). The epitaxy of the high-temperature boron phosphide layer was performed at a temperature of about 1 000 GC, and the reaction was performed for about 60 minutes, and the thickness was about 456 Onm. By changing the content ratio of each precursor to form multilayer stacking layers BxGa (i χ) ρ with different composition ratios, the lattice constant is changed in a gradient. The BxGa (lx) p first multi-layer buffer layers 220 and 321 formed by this method are 咼 temperature 163 (1_ ^ buffer layer. However, the present invention can also be applied to the south temperature 108 (1_3 ^? Buffer layer 220). A low-temperature boron phosphide (BP) buffer layer is provided between the 321 and the substrate 200, and the low-temperature boron phosphide (81 ° buffer layer is formed at a temperature of about 300 GC. Furthermore, the second multilayer buffer layer 222, 322 can be constructed by inyGai_yN

to make. For example, using the MOVCVD method, for example, trimethyl aluminum (TMA1), trimethy indium (TMIn), trimethyl gallium (TMG), and NH3 are used as precursors. The content ratio of each precursor is changed to form a multi-layer stacking layer InyGawN with different composition ratios.

One of the preferred embodiments for forming the gallium nitride-based first type tie layers 230 and 330 is described below. The precursor for forming a gallium nitride (GaN) -based compound may include monomethyl hydrazine (MMH) and trimethyl gallium (TMG). The second multilayer buffer layer is formed by MOCVD method 2 2 2 A gallium nitride-based compound is formed on the surface of 3, 2 2 as the first type of tie layers 2 3 0, 3 3 0. First, supply one H2 and one N2 gas, and start supplying MMH at a temperature of about 350 ~ 500 ° C, for example. After a period of time, for example: after 3 minutes, the first TMG supply is started, the time is about 20 minutes. Then, the TMG supply is stopped, and after a period of time, for example: 5 minutes, the temperature of the reaction chamber is raised to about 800 ° C. Keep ΜΜίί

0769-9103TWF (nl); VTHRA-91-011-TW; Phoelip he.ptd

200411949 V. Description of Invention (17)-Application. Then, the second & TM (J supply, time is about 60 minutes.) Is maintained at the same temperature (about 800. 0). During the period, the MMH supply is maintained. Finally, the supply of MMH and TMG is stopped at the same temperature (about 800). 〇 Hold it up and down for a period of time, for example: 30 minutes. Then reduce the temperature to room temperature to complete the GaN epitaxy. G a N stupid crystals are continuously supplied with || 2 and N 2 gas. In addition, the active layers 250, 350, and 450 It can also be composed of gallium nitride-based compounds, for example: InyGabuy N. For example, MOVCVD can be used, such as trimethy aluminum (TMA1), trimethy indium (TMIn), and trimethyl. Gallium

gal 1 ium; TMG) and NHS are formed as precursors. The better one can change the content ratio of each precursor to form a multilayer stack with different composition ratios. If y is about 0, its lattice constant is about 4.51A ', so that the underlying active layer and the first-type binding layers 230 and 330 have the same lattice constant (C3). The photovoltaic integrated circuit element of the present invention further includes a ...

One of the surfaces of 250, 350, and 450 is a second-type binding layer 232, 332, and 432, a first-type electrode 242, 342, and 442 disposed on the active layers 250, 350, and 450, and a second-type binding layer 232 , 332, and 432 are one of the second-type electrodes 240, 340, and 440, and a field-effect transistor with a source 270, 370, and 470, an electrode 2 72, 372, and 472, and a gate 280, 380, and 480 (field effect transistor, FET) 26 0, 360, and 460 are used as the electronic circuit part on the substrates 200, 300, and 400. A line 29, 390, and 4 90 and an optical circuit (light emitting diode) 21, Sections 31 and 41. The field effect transistor system and the light emitting diode are formed on the same substrate

0769-9103TW (nl); VrERA-91-01M ^; Ph〇elip he.ptd page 21 200411949

And has an interval. The second type tie layers 232 and 332 may be gallium nitride-based compounds. The second-type tethering layers 232, 332, and 432 and the substrates 200, 300, and 400 may be doped into a p-type conductive type, for example, with a town (Mg), or into an n-type conductive type, for example, with sulfur (s). If the second-type binding layers 232, 332, and 432 are p-type conductive types, the second-type electrodes 240, 340, and 440 are p-type conductive types, and the substrates 200, 300, and 400 are n-type conductive types. , The first type electrodes 242, 342, and 442 are n-type conductive types; conversely, if the second type binding layers 232, 332, and 432 are n-type conductive types, the second type electrodes "ο, 34, and 440 Then it is an η-type conductive type, and the substrates 2000 and 300 are ^ -type conductive types, and the first type electrodes 2 42, 342, and 442 are η-type conductive types. Photoelectric integrated circuit elements according to the present invention The advantage of the present invention is that the lattice constant gradient caused by the change of the composition ratio can reduce lattice mismatch, make the epitaxial layer have a perfect crystal structure, and can improve the luminous efficiency and service life of the device. It can be used with the substrate (such as Shixi substrate) to replace the original GaAs substrate for epitaxy, not only does the photons emitted by the LED not be absorbed by the GaAs material, but because The si substrate has several times better heat dissipation ability than the gallium arsenide (GaAs) substrate, because The led is applied under the operation of a high current of several hundred milliamperes to several amperes, and its output power will not be affected by the poor heat dissipation of the substrate. The luminous efficiency. θ8 Although the present invention is disclosed above in a preferred embodiment, it is not useful. To limit the scope of the present invention, anyone skilled in the art can do various modifications and retouching without departing from the spirit and scope of the present invention.

〇769.9103TW (nl); \ rrERA.91-011.TW; Ph〇elip he.ptd

200411949 V. Description of invention (19) The scope of protection shall be determined by the scope of the attached patent application. 0769-9103TWF (nl); VTERA-91-011-TW; Phoelip he.ptd page 23 200411949 Fig. 1 shows a photovoltaic device circuit element having a buffer layer according to a conventional technique. Fig. 2 is a sectional view showing a photovoltaic integrated circuit element according to a preferred embodiment of the photovoltaic integrated circuit element according to the present invention. Fig. 3 is a sectional view showing a photovoltaic integrated circuit element according to another preferred embodiment of the photovoltaic integrated circuit element according to the present invention. Fig. 4 is a sectional view showing a photovoltaic integrated circuit element according to another preferred embodiment of the photovoltaic integrated circuit element according to the present invention. Figures 5a to 5g are flowcharts showing the manufacturing process of a photovoltaic integrated circuit element according to another preferred embodiment of the photovoltaic integrated circuit element of the present invention. Fig. 6 is a sectional view showing a photovoltaic integrated circuit element according to another preferred embodiment of the photovoltaic integrated circuit element according to the present invention. [Symbol description] 100 ~ Kunhua recording substrate; 110, 210, 310, 410, 510, 610 ~ Light emitting diode; 120 ~ Gallium zinc (ZnO) buffer layer; 130 ~ n-type gallium nitride ( GaN) tethering layer; 132 140 142 160 170 172 180 P-type gallium nitride (GaN) tethering layer; 240, 340, 440, 540, 640 ~ second type electrode • 242, 342, 442, 542, 642 ~ The first type electrode 260, 360, 460, 560, 660 ~ field effect transistor 270, 370, 470, 570, 670 ~ source; 272, 372, 472, 572, 672 ~ drain; 280, 380, 480, 580, 680 ~ closed pole;

0769-9103TWF (nl); VTERA-91-011-TW; Phoelip he.ptd page 24 200411949 Schematic description of 190 ^ 290 590, 690 ~ circuit; ^ 390 ^ 490 200, 300, 600 ~ substrate; 220, 320, 620 ~ first multi-layer buffer layer; 222, 322, 622 ~ second multi-layer buffer layer 230, 33 0, 43 0, 530, 630 ~ first type binding layer 232, 332, 432, 532, 632 ~ The second type binding layer 250, 350, 450, 550, 650 ~ active layer; 321 ~ lower layer of the first multilayer buffer layer; 323 ~ upper layer of the first multilayer buffer layer; 400,500 ~ Shixi substrate; 420, 520 ~ boron phosphide (BP) buffer layer; 5 0 2, 6 0 2 ~ silicon dioxide (S i 02) layer; 502a, 502b ~ silicon dioxide (Si 02) layer to be removed; 504, 604 ~ Protective layer; 5 11 ~ predetermined region of light-emitting diode; 561 ~ predetermined field effect transistor; 562 ~ ion value distribution area; 562a ~ source value distribution area; 562b ~ drain value distribution area; 5 8 2 6 8 2 to the gate oxide layer; C 1 to a first lattice constant C 2 to a second lattice constant C 3 to a third lattice constant; and C 4 to a fourth lattice constant.

0769-9103TWF (nl); VTERA-91 -011 -TW; Phoel ip he.ptd page 25

Claims (1)

200411949 The first multilayer buffer layer and the second multilayer are formed at the bottom of the substrate, the first multilayer, the first multilayer buffer layer, and the buffer layer. The body part and part, and the substrate, have the first lattice constant, and the above-mentioned field-effect transistor part has the above-mentioned surface of the substrate, among which the above-mentioned gradient changes the lattice constant 6. Application for patent scope 1 · An optical circuit element optical circuit The electronic circuit part of the element includes at least: a integrated circuit element, a field-effect transistor buffer layer of a part of the light-emitting diode, and a buffer layer provided on the lattice constant exhibiting the above-mentioned first surface. The surface of the multi-layer buffer layer at the bottom of the crystal layer of the multi-layer buffer layer is the photovoltaic cell and the photovoltaic cell circuit, and the light emitting diode is gradually changed from the first to the second lattice constant; The surface lattice constant of a multi-layer buffer layer exhibits a gradient change, from which the above-mentioned second lattice constant gradually has one of the third lattice constant-the first A binding layer is provided on the surface of the second multilayer buffer layer and has a third lattice constant; an active layer is provided on the surface of the first type binding layer; a first type electrode is provided on the surface of the active layer portion; A second-type binding layer is disposed on the surface of the active layer; a second-type electrode is disposed on a portion of the surface of the second-type binding layer; and a line connects the field effect transistor and the first-type electrode. 2. Photoelectric integrated circuit components as described in item 1 of the scope of patent application, 0769-9103TWF (nl); VTERA-91 -011 -TW; Phoel ip he.ptd page 26 200411949 The light-emitting protective layer, wherein the photovoltaic integrated circuit element may further include a protective layer formed between the diode and the field effect transistor, and the circuit is separated from the light-emitting diode. ^ The photovoltaic substrate device described in item 1 of the scope of the patent application said substrate includes silicon (Si); said first multilayer buffer layer includes IGa + yP; said second multilayer buffer layer InwGa and Z_WN; and above The first type of tie layer includes a gallium nitride (GaN) -based compound. 4. The photovoltaic substrate of the first item of the scope of patent application, the above substrate includes silicon carbide (3C-Si); The layer includes BxGa (1_x) P; the second multilayer buffer layer includes InyGa and yN; and the first type tie layer includes a gallium nitride (GaN) -based compound. Circuit element, 1 said substrate includes gallium phosphide (GaP); ', said first multilayer buffer layer includes BxGa (1_x) P; said second multilayer buffer layer includes InyGai_yN; and said first type tie layer includes nitride A gallium (GaN) -based compound. 6. The optoelectronic integrated circuit element according to item 1 of the patent application scope, wherein the above-mentioned substrate includes gallium arsenide (GaAs); the above-mentioned first multilayer buffer layer includes GaAs (1_y) Py; Two multilayer buffer layers include InyGa and yN; and X The first type tie layer includes a gallium nitride (GaN) -based compound 0769-9103TW (nl); VrERA-91-011.TW; Phoelip he.ptd 200411949 6. Scope of Patent Application L A photovoltaic integrated circuit element, including a field-effect transistor portion of an electronic circuit portion of a light-emitting diode portion of an optical circuit portion of a circuit element, and a portion including at least: Integrated circuit and the above-mentioned light-emitting diode is a substrate, the substrate is a silicon substrate formed on the substrate; and the field effect transistor portion has a first buffer layer composed of phosphorus boride, and the substrate surface has a A second lattice constant; 'the buffer layer is disposed on a first type binding layer composed of a gallium nitride (GaN) -based compound and is disposed on the surface of the second multilayer buffer layer, and has a third lattice constant; An active layer is provided on the surface of the first type binding layer; a first type electrode is provided on the surface of the active layer portion; a first type binding layer is provided on the surface of the active layer; a second type electrode is provided Connect the field-effect transistor and the first-type electrode to the second-type binding layer part table and a line. 8 · If the optoelectronic integrated circuit element according to item 7 of the patent application scope, it may further include a second multilayer buffer layer disposed between the first multilayer buffer layer and the active layer, wherein the second multilayer The number of lattice a of the buffer layer exhibits a gradient change. From the bottom of the second multilayer buffer layer, the second lattice constant gradually changes to the surface of the second multilayer buffer layer and there is a third crystal. Lattice constant. θ ^ 9 · The optoelectronic integrated circuit element according to item 7 of the scope of patent application, wherein the optoelectronic integrated circuit element may further include a protective layer formed on the above 200411949 6. Scope of patent application Between the light-emitting diode and the field-effect transistor, and the circuit is separated from the light-emitting diode by the protective layer. A method of manufacturing a photovoltaic integrated circuit element, to the φ sequence of steps:-Including a substrate provided below, forming a silicon dioxide layer on the substrate; optionally engraving the above silicon dioxide layer to define the starting point The predetermined region of the photodiode and the predetermined region of the field effect transistor, and at least one buffer layer, a first-type binding layer, an active layer, and a second-type binding layer are sequentially formed in the predetermined region of the light-emitting diode. The light-emitting diode part of the photovoltaic integrated circuit element; forming a protective layer, conformably attached to the above-mentioned silicon dioxide layer of the light-emitting diode component part; The predetermined area of the transistor, and the silicon substrate as the stop layer for the rest of the time, remove the SiO2 layer in the above-mentioned ion-value distribution area; form an ion-implanted area in the above-mentioned ion-implanted area, and A source electrode, a drain electrode, and a gate oxide sound are formed on the ion implantation area, and then a gate electrode is formed on the gate oxide layer; 9, +, at The second type binding layer and the active layer are etched Stop level up; select The etching is left 'formed on the above-mentioned silicon dioxide layer, and a type-circuit system is formed on the second-type confinement layer: the first-type electrode and the above-mentioned secrets', and the line includes a compliance layer and a light-emitting diode. Body separated.