TW200411911A - Flash memory structure and the operation method thereof - Google Patents

Abstract

A flash memory structure which is consisted of a P-type substrate, a deep N-type well set in the P-type substrate, a P-type well set in the deep N-type well, a pair of gate structure set on the substrate, a select gate set between the pair of gate structure, and N-type source/drain regions set in the P-type well at the side of the pair of gate structure. Each two gate structures closed to each other use a common select gate, so the integration of device can be increased.

Description

200411911 V. Description of the invention (1) Technology of the invention The invention relates to a memory element, and more particularly to a flash memory structure and a method for operating the same. In the prior art, flash memory components have become a personal computer and electronic device because they can store, read, and erase data multiple times, and the stored data will not disappear even after the power is turned off. A widely used non-volatile memory element. A typical flash memory device is a floating gate made of doped polysilicon.

Floating Gate and Control Gate. In addition, the control gate is directly arranged on the floating gate, the floating gate and the control gate are separated by a dielectric layer, and the floating gate and the substrate are separated by a tunnel oxide (also (The so-called stacked gate flash memory).

When writing data to the flash memory, the control gate and source / drain regions are biased so that electrons are injected into the floating gate. When reading the data in the flash memory, a working voltage is applied to the control gate. At this time, the charged state of the floating gate will affect the opening / closing of its lower channel (C ha η ne 1), and this The opening / closing of the channel is the basis for judging the data value "0" or "1". When flash memory is erasing data, 'the relative potential of the substrate, the drain (source) region, or the control gate is increased, and the tunneling effect is used to pass electrons from the floating gate through the tunneling oxide layer. (Tunneling Oxide) and drain into the base or drain (source)

Substrate Erase or Drain (Source) Side Erase), bite is passed through the dielectric layer and discharged into the control gate.

9918twf.ptd Page 6 200411911 V. Description of the invention (2) However, when erasing the data in the flash memory, because the amount of electrons ejected from the floating gate is not easy to control, it is easy to discharge the floating gate Too many electrons with a positive charge is called over-erase. When this over-erase phenomenon is too serious, even the channel below the floating gate will continue to be in a conducting state when the control gate is not applied with a working voltage, and the data will be misjudged. Therefore, in order to solve the problem of excessive erasing of components, many flash memories will adopt the design of a split gate (Sp 1 it Ga te). Its structure is characterized in that in addition to the control gate and the floating gate, it also has a Gate and floating gate side wall, one of the gates above the base selects the gate (or erase gate). This selection gate (erase gate) and control gate, floating gate and the base W Separated by a gate dielectric layer. In this way, when the over-erase phenomenon is too serious, and the channel below the floating gate is continuously opened without the control voltage applied to the gate, the channel below the selected gate (erasing the gate) can remain closed. The state makes the drain / source region impossible to conduct and prevents misjudgment of data. Because the split gate structure requires a larger split gate area and a larger memory cell size, its memory cell size is larger than that of a stacked gate flash memory, resulting in the so-called inability to increase component accumulation. Problem. Therefore, the industry currently proposes a dual flash memory cell structure that allows two memory cells to share a selection gate (erase gate), thereby reducing the size of the memory. FIG. 1 is a cross-sectional view showing a conventional dual flash memory cell structure. Please refer to FIG. 1. This flash memory has two memory cells 1 0 1 a and 1 0 1 b on a base 100. The memory cells 1 0 1 a and 1 0 1 b each include a gate structure 10 2 a and 10 2 b. The two gate structures 10 02 a and 102 b sequentially have

9918twf.ptd Page 7 200411911

Tunneling oxide layers 104a, 104b, floating gates 106a, 106b, gate dielectric layers 108a, 108b, control gates 110a, 110b and cap layers 112a, 1 1 2b. Spacers 1 1 4 a and 1 1 4 b are provided on the side walls of the gate structures 10 2 a and 10 2 b. On the opposite sides of the two gate structures 10a and 10b, respectively, source / drain regions 116a and 116b are formed. On the surface of the structure 1 02a and 1 02b, there are selection gates 1 1 8. This selection interval 彳 丨 8 extends from the source / drain region 1 1 6 a to another source / drain region 1 1 (丨 h · I »When programming the memory cell 1 0 1 a of the twin flashes, the memory cell 1 0 1 b is used as a channel transistor. That is, the control gate 丨 丨A bias voltage of 10 volts is applied to 〇a; a bias voltage of 10 volts is applied to control gate 1 1 〇b to open the channel below the recording cell 1 0 1 b; a bias voltage of 2 volts is applied to gate 丨 丨 8 A voltage of 2 volts is applied to the source / non-electrode region 116a, and the source / drain region 116b is 0 volts. In this way, when programming, the electron system goes from the source / drain region l > 16b to the source The pole / drain region 1 i6a moves and is accelerated by a high-channel electric field at the source / drain region to generate hot electrons. Its kinetic energy is sufficient to overcome the energy barrier of the tunneling oxide layer 104a, plus control A high positive bias is applied to the gate noa, so that hot electrons are injected into the floating gate 10 6a from the source / drain region 6a, and the programmed memory cells are the same. , For memory cells 1 〇 丨When stylization is performed, the δ self-recovery cell 10a is used as a channel transistor. That is, a bias voltage of 10 volts is applied to the control gate 110b, and a bias voltage of 10 volts f is applied to the control gate 110a. The channel below the memory cell 10la is open; select the gate 丨 ^^, the bias voltage of the source / drain region 1 16a is 0 volts, and a bias of 2 volts is applied to the source / drain. Thus, during programming, the electron system moves from the source / animated region 116a to the source / animated region U6b, and at the source / animated region U6b,

Page 8 200411911 V. Description of the invention (4) The hot end of the 1 1 6 b end of the drain region is accelerated by the high-channel electric field, and its kinetic energy is sufficient to overcome the energy barrier of the tunneling oxide layer 1 0 4 b, plus A high positive bias is applied to the control gate 1 1 0 b, so that hot electrons are injected into the floating gate 10 6 b from the source / drain region 1 6 b end. In the programming method of the dual flash memory cell, after the memory cell 1 0 1 a is programmed, and then the memory cell 1 0 1 b is programmed, the memory cell 1 0 1 b is subject to the programmed function. The effect of the programmed memory cell 1 0 1 a reduces the programmed current, so the programmed speed of the memory cell 1 0 1 b is lower than the programmed speed of the memory cell 1 0 1 a. As a result, the asymmetry of the stylization of the memory cell will be caused, resulting in a slow operation of the memory cell. SUMMARY OF THE INVENTION In view of this, an object of the present invention is to provide a structure of a flash memory and a method for operating the same, which can improve the accumulation degree of the memory elements. Another object of the present invention is to provide a structure of a flash memory and a method for operating the same, without the asymmetry of the memory cell programming, which can reduce the current of the memory cell and improve the operation speed of the memory element. Another object of the present invention is to provide a structure of a flash memory and a method for operating the same, which can avoid excessive erasure of memory cells. The invention provides a structure of a flash memory element. The structure of the flash memory element is composed of a first conductive type substrate, a second conductive type first well region, a first conductive type second well region, and a pair of gate electrodes. A structure, a selection gate, and a pair of first conductivity type source / drain regions. Among them, the second conductive type first well region is disposed in the first conductive type substrate; the first conductive ^ type second well region is disposed in the second conductive type first well region; a pair of gate structures is disposed in the first

9918twf.ptd Page 9 200411911 One pair of structured pole gates on one side is set to set the pole source in the other subdivision. The bottom type is based on the electric milk type and the first and fifth structured pole gate pairs-on the set Set the gate to select the layered oxygen tunneling gate to float. In the structure of the junction area, two pairs of first-pole electric gates in the junction area are conducted on the first-the second on the second control, the bottom and the wall of the base type of the bottom gap between the electric base-conducted one-on-one and the first on the first floor. The first electric device and the dielectric pole gate are set, and the floating pole is set, and the gap setting system is set in the middle. The tunnel electrode wall in the Chenghua oxygen structure is placed through the gate and the gate wall is placed. The upper pole of the gap is placed first. The floating gate is placed in the layer and the dielectric gate is controlled by the second pole of the gap. The floating part, the top pole and the sluice are controlled by the side control hr. In between and between the yuan. The bottom flash of the base body and the side of the electric flash guide fast brake, the first one is located at the top of the floating and the second is located at the pole, the two are next to each other. It can be added to add exercises to this element because of the body's memory. Yiji Jizha selects fast M types one by one to provide a total of outside 丨 another Mingfa (constitutes of the composition of the memory as deep operations. The model is included in the package, including the element of the package. Remembering the base of the model, the element of the model means the old one. The pattern of the model of the zone of the flash is located on the depth of the pattern of the setting zone. Recalling the ancient memory of the ancients and the ancients, the first and second poles include the gate and the gate, and the month and the gate are controlled by the second pole and the second pole and the regional pole & draw selection / > '' Hidden sum f in the cell area of the control two and // elementary metadiodes of the first source and the second cell of the flash memory and the short note area into a polar form of the first piece of the first and the bottom of the basic package Bao Yueyi Jigukou set the cell and set the second set and the cell division Remembrance of the memory in the middle area of the well-type process / in the poles of the sluice gate original: one / legal system control this one and the first, the opposite, the type of the cell II introductory side profile

flLHfwr-ΜΊΜ

9918twf.ptd Page 10 200411911 V. Description of the invention (6) Add the first positive voltage, apply the first negative voltage to the P-type well area as the ground, the first source / non-pole ... the second source is the second choice. In the case of the memory cell, the second positive voltage is applied to the closed pole of y., I5U | the closed pole: a -1 control voltage is applied to the second .m. The second control gate voltage is applied to the-^ voltage to the second source voltage. The positive electrode / drain region is connected to the ρ-type and grounded to read the second positive electrode. The fifth positive voltage is applied to the second electrode, and the second electrode is erased by using the f-ν penetrating effect. The whole, / face — // 5 / polar area is floating, with flash memory elements of Bu, +, Xi & & pages. The above-mentioned operation of the second memory of the flash memory element is more complicated. When privateizing a HW β and a hidden cell, the first control gate is applied to the second control gate. The first negative voltage is applied to the well region, so that the selection gate is connected to the drain region and the second source / drain region are floating to program the second memory cell by using the FN tunneling effect. . ^ In the flash memory device of the present invention, an isolated P-type well area is provided in a deep N-type well area. Therefore, in a stylized operation, due to the control gate and the P-type well area where P is free from Voltage, and the F-N tunneling effect is used to make the electrons pass from the substrate (isolated P-well region) through the tunneling layer to the floating gate. Therefore, the first memory cell is transformed into the second memory cell. When performing a stylized operation, the second ashamed cell is not affected by: the stylized first cell has been affected by the memory, and the problem of asymmetric stylization of the memory cell can be avoided. In addition, the stylized operation of the channel flashing shame component of the present invention is adopted.

9918twf.ptd Page 11 200411911 V. Explanation of the invention (7)-Using F-N tunneling effect, its lightning, ^ ^,,., P ^ ^. The efficiency of the injection of the wrongdoers is relatively high, so the coding can be reduced. A recalls the cell current, and has the same operating speed as the "At ancient" sun inch crime & Because the stylized and erased movements use FN tunneling 4 盆, the two, ☆ ,, James, and dentition effects, and its small current / xiao consumption can effectively reduce the work of the entire memory device. ^ — Force Rate deduction, same leaves can also be applied to parallel stylization / erasing of large-size pages. In order to make the above-mentioned objectives, features, and advantages of the present invention more obvious and easier, “I. Heavy”, a preferred embodiment is given below, in conjunction with the accompanying drawings, as follows: `` The second embodiment is a drawing A top view of the flash memory of the present invention is shown. Please refer to FIG. 2 'The flash memory of the present invention is composed of a substrate 200, a component isolation / structure 2 0, an active area 2 0 4, a control gate 2 06 (word line), and a floating gate. 208, the N-type source / drain region 21 0, the P-type well region 31 2 and the selection gate 21 4. Constituted by. Among them, an insulating layer (gap wall) 2 1 6 and an insulating layer (gap wall) 2 1 8 are provided between the selection gate 2 14 and the control gate 2 06 and the floating gate 2 0 8. A deep N-type well area (not shown) is provided in the base 200, and a p-type well area 212 is provided on the deep · N-type well area. The element isolation structure 2 0 2 is disposed in the substrate 2 0 to define the active region 204 so that the P-type well region 212 is located in the active region 204 only. The control gate 206 is disposed on the substrate 200 and is perpendicular to the active region. 204. The floating gate 208 is disposed under the substrate 200 of the control gate 206 (word line) across the active region 204. In the same active area 204, every two memory cells 220 are used as a group, and a selection gate 21 4 is provided between two adjacent memory cells. The N-type source / drain region 210 is disposed in the p-type well region 212 on both sides of each memory cell group 2 20. Select the gate 2 1 4 in the same active area 2 0 4 to select the gate line (not shown).

4-

9918twf.ptd Page 12 200411911

5. Description of the invention (8) are connected together, and the N-type source / drain regions 210 in the same active region 204 are electrically coupled together by bit lines (not shown). Next, the manufacturing method of the flash memory of Ben Sheming will be described. Figures 3 A to 3 Η, and Figures 4 A to 4 D are shown in Figure 3 along a_a, line, B-B. 'Line manufacturing process cross-section. First, please refer to FIG. 3A and FIG. 4A to provide a p-type substrate 300. This P-type substrate 300 has formed an element isolation structure 302, and the element isolation structure 302 is arranged in a stripe shape. To define the active area. The formation method of the element isolation structure 3 〇 2 is, for example, a regional oxidation method (Loca 1 Oxidat ion, LOCOS :) or a shallow trench isolation method (Shallow Trench Isolation, STI), in which the solitary degree of the element isolation structure 3 2 should be able to isolate subsequent Formed p-type well area 306. Next, a deep N-type well region 304 is formed in the P-type substrate 300, and a P-type well region 306 is formed within the deep N-type well region 304, wherein the depth of the P-type well region 306 does not exceed the depth of the isolation structure 30 2 . After that, an oxide layer 308 is formed on the surface of the p-type substrate 300 as a tunneling oxide layer. The method for forming the oxide layer 308 is, for example, a thermal oxidation method. Next, referring to FIG. 3B and FIG. 4B, a conductive layer (not shown) is formed on the oxide layer 308. The material is, for example, doped polycrystalline stone. The method for forming the conductive layer is, for example, using After the chemical vapor deposition method forms an undoped polycrystalline silicon layer, an ion implantation step is performed to form it. The thickness of the conductor layer is, for example, about 200 angstroms, and the dopant implanted into the conductor layer is, for example, Kun ion, in order to form a circular shape that is favorable for erasing in the subsequent thermal oxidation process, and then pattern the conductor layer It exposes part of the surface of the element isolation structure 302 to form a conductive layer 31 as shown in the figure.

99l8twf.ptd Page 13 200411911 V. Description of the Invention

Alas, please refer to Figure 3C and Figure 30. After sequentially forming a dielectric layer 312, y, 8 on a p-type substrate 300, and a conductor layer (not shown), the conductor layer is patterned by using to define it as a control gate. The material of the dielectric layer 312 is, for example, oxidized. &Quot; Gasified stone layer > The method for forming the dielectric layer 31 2 is, for example, a low-pressure chemical vapor deposition method. Of course, the material of the dielectric layer 3 1 2 may be a silicon oxide layer, a silicon oxide layer, or the like. The material of the conductor layer 3 1 4 is, for example, doped polycrystalline silicon, and the formation method of the conductor 314 is, for example, formed by in-situ doping ions using chemical vapor deposition. After the mask is removed, a termination layer 3 1 6 is formed on the side wall and the top of the conductor layer 3 丨 4. The material of the insulating layer 3 1 6 is, for example, silicon oxide, and a method for forming the insulating reed is, for example, a thermal oxidation method. Next, referring to FIG. 3D and FIG. 4D, the dielectric layer 312 and the conductor layer 31 are defined by using the conductor layer 314 and the insulation layer 316 as the screen, so that they are respectively shaped as an electrical layer 31 2a and a conductor layer 31a. Among them, the conductive layer 31〇a is used as a floating electrode. That is, the conductor layer (control gate) 31-4 shown in the figure, the dielectric layer gate 312a, the conductor layer (floating gate) 310a, and the oxide layer 308 (tunneling oxide layer constitute a gate structure. Then, a patterned masking layer 3 1 8 is formed on the entire substrate 300, and the patterned masking layer 3 丨 8 exposes a region where the source / injection region 320 is to be formed. Then, an ion implantation step is performed to The patterned cover layer 318 is a mask, and a dopant is implanted into the p-type well region in the substrate 300 on one side of the gate structure to form a source / drain region 32. Among them, two gate junctions are formed. 6 is a gate structure group. In the gate structure group, the gate structure can be used to form a selection gate, and the source / drain region 32 is formed in the gate structure =

9918twf.ptd Page 14 200411911 V. Description of the Invention (ίο) In both sides of the base. Since the structure of line B-b in Figure 2 is the same in subsequent processes, the following describes only the process of line A-A and line section in Figure 2. Please refer to FIG. 3E after removing the patterned mask layer 3 丨 8. Then, a selective gate oxide layer 3 2 1 is formed on the substrate 3 0 0 between the gate structures, and the conductive layer 310 a (floating The gate electrode) has an insulating layer (gap wall) 32 2 on its side wall. The material of the gate oxide layer 3 2 1 and the insulating layer (gap wall) 3 2 2 is selected, for example, silicon oxide, and the method of forming the gate oxide layer 3 2 1 and the insulation layer (gap wall) 3 2 2 is, for example, thermal oxidation law. Among them, the thickness of the selected gate oxide layer 3 2 i is, for example, about 250 Angstroms. Next, another patterned mask layer 3 24 is formed on the substrate 300. The patterned mask layer 324 covers the source / drain region 32 and exposes a region where a selection gate is to be formed. Then, a conductive layer 326 is formed on the substrate 300. The material of the conductive layer 32 6 is, for example, doped polycrystalline silicon, and the method of forming the conductive layer 3 2 6 is, for example, formed by in-situ doped ions using chemical vapor deposition. Next, referring to FIG. 3F, 'removing part of the conductor layer 326 and the patterned mask layer 32 6 until the surface of the insulating layer 316 is exposed', the shape between the gate structures is selected = gate 328. After that, the patterned mask layer is removed. The subsequent completion of the flash § self-memory process is well known to those skilled in the art, and will not be repeated here. FIG. 5 is a cross-sectional view showing a structure of a flash memory according to the present invention. 4 According to FIG. 5, the flash memory of the present invention is composed of p-type substrate 0 = type well area 502, isolated P-type well area 504, gate structure ⑽, and pole area 50 8. Pole 510. The interrogation structure 506 is composed of an oxide layer 512, a floating gate 514, an open-gate dielectric layer 516,

Page 15 200411911 V. Description of the invention (11) The gate electrode 518 and the partition walls 52 0 and 522 are used. The deep N-well region 502 is located in the P-type substrate 500. The isolated p-type well area 5 (). 丨 is located in the special N-type well area 502. The gate station structure 506 is located on a p-type substrate 2000, and has two adjacent gate structures 506 A—a gate structure group 5 24. The N-type source electrode and the pole region are located in the gate structure 纟 u · Γ) 2 4 and the two p-type well regions 504. Selective suppression The gate 5 1 0 is located between the two junction structures 506 of the gate junction. ‘T select gate 5 1 0 and base into 5 () () Ai Wen only selects the inter-polarization layer 5 2 6. The partition wall 5 2 0 is located at the top and side walls of the control gate 5 1 8. The partition wall 5 2 2 is located on the 5 U side wall of the floating gate. According to the present invention, one selection gate 5 10 is shared by two adjacent gate structures 506 (memory cells), so that the accumulation degree of components can be increased. FIG. 6 is a circuit diagram of the flash memory of the present invention. In Figure 5, there are shown a plurality of memory cells Qnl to ^^! ^, Selection transistors Tnl to Tn4_, isolated p-type well regions 1 ^ 0 to 13, bit lines / source lines blo / s 〇 To bit line / source line BL 2 / S 2. Control gate line c G 〇 To control gate line cg 3 and select gate line (word line) SGO (WLO) to SGI (WL1). A plurality of memories are formed by using each two memory cells and a selection transistor as a group to form a plurality of groups. The selection transistor is arranged between the two memory cells. The above complex number == memory cell groups are arranged side by side in a row / column array, and two adjacent memory cell groups share a source / drain region. The source / drain region of each memory month in each memory cell group in each column is coupled to a corresponding bit line / source line. ^ Each ^ The control electrode of each memory cell is corresponding to— Electric pole force of the P-shaped well area for controlling each memory cell in a row of 7 poles

200411911

Ask the polar lines (character lines). For example, in the same column, memory cells such as 1, select transistor Tnl, memory cell Qn2 as a group, memory cells such as 3, select transistor Tn2, memory cell Qn 4, as a group, memory cell qn 5. Select the transistor Tn3 and memory cell Qn6 as a group, and select the memory cell Qn7, select the transistor Tn4 and memory cell Qn8 as a group. Memory cells such as 1, Qn5 side source / drain is coupled to bit line / source line BL0 / S0, memory cells Qn2, Qn3, Qn6, Qn7 side source / no pole are lightly connected to bit line / The source line BL1 / S1, and the source / drain on the memory cell side such as 4, Qn8 are coupled to the bit line / source line BL2 / S2. The control gate line CG0 is connected to the control gates of the memory cells Qni and Qn5, the control gate line CG1 is connected to the control gates of the memory cells Qn2 and Qn6, and the control gate line CG2 is connected to the control gates of the memory cells Qn3 and Qn7. The polar line CG3 connects the memory cell Qn4,

Control gate of Qn8. Select the gate line (word line) SG0 (WL〇) to connect the gates of the transistors Tnl and Tn2, and select the gate line (word line) SG1 (WU) to connect the gates of the transistors Tn3 and Tn4. Memory cells such as 1, Qn2, Qn3 and Qn4 are electrically coupled together in an isolated P-type well area PW0, and memory cells such as 5 /, Qn6, Qn7, and Qn8 are electrically coupled together in an isolated P-type well area PW1 .

The memory cell array of the present invention uses a selection transistor (selection gate) for every two memory cells, so the size of the memory cell can be reduced, and by this design, the memory cell array of the present invention also has the same practice The known NAND-type memory cell array has the advantage of smaller size, and can increase the degree of accumulation. Next, please refer to FIG. 7A and FIG. 7B to understand the operation mode of the flash memory element in the preferred embodiment of the present invention, which includes programming (Program, FIG. 7A), and data reading (Read ), And erase

9918twf.ptd Page 17 200411911 V. Description of the invention (13) (Erase, Figure 7B) and other operation modes, and the memory cells Qn 1, Qn2 shown in Figure 6 are taken as an example. When the memory cell Q η 1 is programmed, a positive bias voltage ν CG ρ is applied to the control gate 6 6 a (CG 0), which is, for example, about 10 volts to 12 volts, and is at P A negative bias voltage -VPWp is applied to the well region 60 4 (PW0), which is, for example, about -6 volts to about -8 volts, the source / drain region 612 (BL0 / S0), and the source / non-polar region 614 (BL1 / S1) is floating, and the gate 61o (SGO) is selected as 0 volts. In this way, when programming, in this way, a large electric field can be established between the floating gate 606a and the substrate 600, and the channel F-N tunneling effect (Channel FN Tunneling) can be used to pass electrons through The tunneling oxide layer 616 enters the floating gate 606a. Similarly, when the memory cell Qn2 is programmed, a positive bias voltage v CG ρ is applied to the control gate 6 0 6 b (C G1), which is, for example, about 10 volts to 12 volts, and is in the ρ type. A negative bias voltage -VPWp 'is applied to the well area 604 (pw0), which is, for example, about -6 volts to -8 volts. The source / drain region 612 (BL0 / S0) and the source / drain region 6i4 ( BL1 / Sl) is floating, and the gate 610 (SG0) is selected to be 0 volts. In this way, when programming, in this way, a large electric field can be established between the foreign gate 6 06b and the substrate 6 0, and the electrons can pass through the tunneling oxide layer 616 to float using the FN tunneling effect. The gate 606b is as shown in FIG. 7A. When performing the above-mentioned programming operation, the memory cells such as 5, Qn6 are not programmed. This is because the isolated P-well area (PW1) is 0v, so remember

Qn5, Qn6 will not produce F-N tunneling effect, of course, it will not be programmed =

Qn5, Qn6 ° In addition, the control gate lines CG2, connected to memory cells Qn3, Qn7

200411911 V. Description of the invention (14) The voltage of the control gate line CG3 of the memory cells Qn4 and Qn8 is 0 volts, so the memory cells Qn3, Qn4, Qn7 and Qn8 will not produce the F-N tunneling effect. When the reading operation of the memory cell Qn 1 is performed, the reading bias voltage of the memory cell QrU can be set as follows: The bias voltage of the source / drain region 61 2 (BL0 / s〇) is ..., which is, for example, 1 volt. To about 1.5 volts, the bias voltage of the selected gate 61 ° (% 0 (several)) is Vcc, which is, for example, about 3.3 volts, and the bias voltage of the control gate 608a (cG0) is Vcc. It is, for example, about 3.3 volts, and the bias voltage of the control gate 608b (CG1) is VCGR ', which is, for example, about 10 volts, the source / drain region 614 (BL1 / S1), and the isolated p The well area 604 (PW0) is grounded. When performing the reading operation of the memory cell Qn2, the reading bias of the memory cell Qn2 can be set as follows: The bias voltage of the source / drain region 614 (BL1 / S1) is Vd, which is, for example, 1 volt to 1 About 5 volts, the bias voltage of the selection gate 61 ° (SG0 (WL〇)) is Vcc, which is, for example, about 3.3 volts, and the bias voltage of the control gate 608b (CG1) is Vcc, which is, for example, 3 · About 3 volts, the bias voltage of the control gate 608a (CG〇) is VCGR, which is, for example, about 10 volts, and the source / drain region 612 and the isolated P-type well region 604 (PW0) are grounded. . Since the channel of the memory cell with the electron stored in the floating gate is closed and the current is small, and the channel of the memory cell with the floating gate is open and the current is large, it is possible to pass the memory cell = switch / channel current To determine whether the number stored in this memory cell is "1" or "0". When the memory cells Qn 1, Qn2 are erased, 0 volts are applied to the control gate 608a (CG0) and the control gate 608b (CG0); a positive bias voltage is applied to the pole 610 (SG0) to (3) It is, for example, about 10 volts to about A, source / drain region 612 (BL0 / s〇), source / drain region 4

9918twf.ptd Page 19 200411911 V. Description of the invention (15) 614 (BL1 / S1) and the isolated P-type well area (PW1) are floating. In this way, a large electric field can be established between the floating gate 6 6 a, the floating gate 6 6 b, and the selective gate 6 1 0, and the electrons can be removed from the floating gate by using the F-N tunneling effect. The interrogation pole 6 0 6a and the floating gate 6 06b are pulled out to the selection gate, as shown in FIG. 7β. ° During the above-mentioned erasing operation, since the selection transistor Tnl between the memory cells Qnl and Qn2 and the selection transistor Tn2 between the memory cells Qn3 and Qn4 share a selection gate line (word line) SG〇 (WL 〇), so when memory cells Qnl, Qn2 are erased, memory cells Qn3, Qn4 on the same page will also be erased. And the choice between the memory cell Qn5, Qn6, the transistor Tn3 and the memory cell, such as? The selection gate line (character = S ^, (WL1) shared by the selection transistor Tn4 between Qn8 and Qn8 is not applied with voltage, so the memory cells such as 5, Qn6, and ㈣ are not erased. FN-tunneling effect (Channel FN TunneHng) to remove the data in the hidden cells. That is, the flash memory of the present invention performs a erase operation with a page nose, thinking about this, starting from 1U The shell surface is early. Therefore, the flash gate of the present invention is used to control the gate line two plus ::, is a bias voltage of about 10 volts to 12 volts, and the entire page is $ 2 & The tunneling effect erases the data in Yiyou's cell. In the separated P-type well area, the flash § Jiyi, and the file, the isolated P-type well area is set up in the deep N-type well area. During the ionization operation, by controlling the gate electrode and the substrate (isolated ^^. When the voltage is used, the electrons are used in the FN tunneling effect, so in the t-well region) through the tunneling oxide layer and enter the floating After the gate hidden cell Qnl &

9918twf.ptd Page 20 200411911 V. Description of the invention (16) When performing the stylized operation, the memory cell Qn 2 will not be affected by the programmed memory cell Qn2 'and the problem of asymmetric programming of the memory cell can be avoided. Moreover, the present invention can also apply a positive bias voltage vcGp to the control gate 606a (CG0) and the control gate 606b (CG1) at the same time, and apply it to the P-type well area 6 04 (PW0). Negative bias-vpwp, the source / drain region 612 (BL0 / s〇) and the source / drain region 614 (BL1 / S1) are floating, and the gate 61o (SG0) is selected as 0 volts' At the same time, stylized memory cells, Qn2. Use f — n to be empty. The stylized operation of the channel flash memory element of the present invention is the 7 effect of the time. Its electron injection efficiency is high, so it can reduce the coding current and increase the cell current. Operating speed. Since Cheng Mao and his actions all use the F-N tunneling effect, the power consumption of the entire memory element is low, and n, two, and small hairs can effectively reduce the parallel programming / erasing of the page. Question 4 can also be applied to large size to limit: in a preferred embodiment, such as ...-not in the field and range, when it can be used for various kinds without departing from the fine money of the present invention ... see the attached application; The set = the invention "200411911 Brief description of the diagram-Figure 1 is a cross-sectional view of a conventional flash memory, and Figure 2 is a top view of the flash memory of the present invention; ' Figures 3A and 3F show the manufacturing process along the line A-A 'in Figure 2 & process cross-section; ° Figures 4A and 4D are smaller along the line B-B' in Figure 2 Manufacture of the line "Cross-section view; ° Figure 5 shows the structural cross-section of the flash memory of Mu Niming. Figure 6 continues the simplified circuit diagram of the revised flash memory ship; Figure 7 Figure A is a schematic diagram of the stylized operation of the quick memory of the present invention; and Figure 7B is a schematic diagram of the erase operation mode of the flash memory of the present invention. > 20 0 ~ 30 0 \ 50 0: substrate 10 la, 102b: memory cells 102a, 102b, 5 06: gate structure 104a, 104b, 308, 512 ·· tunneling oxygen Layers 106a, 1 06b, 2 08, 514 ·· Floating gates 108a, 108b, 516: Gate dielectric layers 110a, 110b, 206, 518 · Control gates 112a, 112b: Top cap layers 114a, 114b, 216, 218, 316, 322, 520, 522: spacers 116a, 116b, 210, 320, 508: source / drain regions

Page 22 200411911 Brief description of the drawing 1 1 8, 2 1 4, 3 2 8, 5 1 0: Select gate 2 0 2, 3 0 2: Isolation structure 2 0 4: Active area 21 2, 306 > 50 4.PW0, PW1: P-type well area 2 2 0, 5 2 4: Memory cell group 3 0 4, 50 2: Deep N-type well area 310, 310a, 314, 3 26: Conductor layer 31 2, 31 2a: Dielectric layers 318, 324: patterned mask layers 321, 526: selective gate oxide layer

Qn 1, Qn2, Qn3, Qn4, Qn5, Qn6, Qn7, Qn8 ·························· 0 ······································· BIT / SOURCE SGO (WLO), SG1 (WL1) : Select gate lines Tnl, Tn2, Tπ3, Tn4: Select transistors GCO, GC1, GC2, GC3: Control gate lines

9918twf.ptd Page 23

Claims (1)

200411911 VI. Application Patent Scope 1 · A structure of a flash memory device, the structure of the flash memory device includes a first conductive type substrate; a second conductive type first well area, the second conductive type first A well region is disposed in the substrate; a first conductivity type second well region is disposed in the second conductivity type first well region; a pair of gate structures, the pair of gates A pole structure is disposed on the first conductive type substrate; a selection gate is disposed between the pair of gate structures; and a pair of first conductivity type source / drain regions, the pair of first The conductive source / drain regions are respectively disposed in the first conductive second well regions on both sides of the pair of gate structures. 2. The structure of the flash memory device according to item 1 of the scope of patent application, wherein the first conductive type substrate includes a P-type substrate. 3. The structure of the flash memory device according to item 1 of the scope of the patent application, wherein the second conductive type first well region includes an N-type well region. 4 · The structure of the flash memory device according to item 1 of the scope of the patent application, wherein the first conductive type second well region includes a p-type well region. 5. The structure of the flash memory device as described in item 1 of the scope of the patent application, wherein the pair of first conductivity type source / drain regions is doped with N-type ions. 6. The structure of the flash memory device as described in item 1 of the scope of patent application, wherein each pair of gate structures includes at least: 9918twf.ptd Page 24 200411911 VI. Application scope A floating gate electrode, the floating closed electrode is disposed on the first conductive type substrate; a tunneling oxide layer, the f tunnel rolling layer is disposed on the floating electrode A gate is placed between the gate and the first conductive substrate; a control gate is provided on the floating gate; a gate gate layer is placed on the control gate; And: the question of the floating gate: a first gap, the first gap is provided on the side wall and the top of the control gate; and a second gap, the second gap is provided on the floating gate The side wall of the pole. 7. The flash memory element structure described in item 6 of the patent application scope, further comprising a selective gate oxide layer disposed between the selective gate and the first conductive type substrate. 8. The structure of the flash memory device according to item 6 of the scope of patent application, wherein the material of the first spacer comprises silicon oxide. 9. The structure of the flash memory device according to item 6 of the patent application scope, wherein the material of the second spacer comprises silicon oxide. 1 0. A method for operating a flash memory device, suitable for operating a flash memory device, the flash memory device including a P-type substrate; an N-type well area disposed in the P-type substrate; A P-type well area is disposed in the N-type well area; a first memory cell and a second memory cell are disposed on the P-type substrate, and the first memory cell includes a first control gate and the first memory cell. The two memory cells include a second control gate; a selection gate is disposed on the first memory 9918twf.ptd Page 25 200411911 6. The scope of the patent application and the second memory cell; a first source / drain region and a second source / drain region are respectively disposed on the first memory cell and the In the p-type well region on one side of the second memory cell, the first source / drain region and the second source / drain region are of an N-type conductive type; and the method includes: stylizing the When the first memory cell of the flash memory element, a first positive voltage is applied to the first control gate, and a first negative voltage is applied to the P-type well area, so that the selection gate is grounded, and the first The source / drain region and the second source / drain region are floating to program the first memory cell using the F-N tunneling effect; while reading the first memory of the flash memory element A second positive voltage is applied to the selected gate, a second positive voltage is applied to the first control gate, a third positive voltage is applied to the second control gate, and the second source Applying a fourth positive voltage to the electrode / drain region, floating the first source / drain region and the P-type well region to read the data of the first memory cell; And when erasing the first memory cell of the flash memory element, applying a fifth positive voltage to the selection gate, so that the first control gate and the second control gate are 0 volts, the first The source / drain region and the second source / drain region are floating, so as to erase the flash memory device by using the FN tunneling effect. 1 1. The method for operating a flash memory device as described in item 10 of the scope of patent application, wherein the method further includes: when programming the second memory cell of the flash memory device, Two control gates apply the first positive voltage and the first negative voltage to the P-type well region to ground the selection gate, the first source / drain region and the second source / drain region Is floating to stylize the first using the FN tunneling effect 9918twf.ptd Page 26 200411911 VI. Scope of Patent Application Two memory cells. 12. The method for operating a flash memory device as described in item 10 of the scope of patent application, wherein the method further comprises: when erasing the first memory cell of the flash memory device, simultaneously erasing the first memory cell Second memory cell. 13. The method for operating a flash memory device as described in item 10 of the scope of patent application, wherein the first positive voltage is about 10 volts to about 12 volts. 1 4. The method for operating a flash memory device as described in item 10 of the scope of patent application, wherein the first negative voltage is about -6 volts to -8 volts. 15. The method of operating a flash memory element as described in item 10 of the scope of patent application, wherein the second positive voltage is about 3.3 volts. 16. The method for operating a flash memory device as described in item 10 of the scope of patent application, wherein the third positive voltage is about 10 volts. 1 7. The method for operating a flash memory device as described in item 10 of the scope of the patent application, wherein the fourth positive voltage is about 1 volt to about 1.5 volts. 1 8. The method for operating a flash memory device as described in item 10 of the scope of patent application, wherein the fifth positive voltage is about 10 volts to 12 volts. 9918iwf.ptd Page 27