TW200411746A - Method for producing amorphous silicon layer with reduced surface defects - Google Patents

Abstract

A method for producing an amorphous silicon layer with reduced surface defects comprises: mounting a substrate in a chemical vapor deposition (CVD) device; introducing a SiH4 gas with a low flowrate into the CVD device for depositing a first amorphous silicon layer on the substrate, in which the flowrate of the SiH4 gas is about 60~100sccm; and introducing a SiH4 gas with a high flowrate into the CVD device for depositing a second amorphous silicon layer on the first amorphous silicon layer, in which the high flowrate of the SiH4 gas is about 110~160sccm.

Description

200411746 V. Description of the invention (i) [Technical field to which the invention belongs] The present invention relates to a gate electrode process of a semiconductor device, and more particularly to a method using a two-stage (dua 1 steps) process. Manufacturing method to reduce the defects of the amorphous electrode (amorphous si 1 icon) gate electrode. [Prior art] Conventionally, a chemical vapor deposition method (chemica 1 va ρ οr deposition, CVD) is commonly used to deposit a polycrystalline silicon layer (polys) at a temperature range between about 500 to 650 ° C. i 1 icon) or amorphous si 1 icon to be used as a gate electrode of a complementary metal-oxide semiconductor transistor (CMOS transistor). When applied to occasions where the line width (critical dimension) is 0.25 micrometers, a low flow rate (approximately 60 to 100 sccm) of Shi Xiyan is used; j: the CVD condition of the finished gas, because of its The performance of the deposited amorphous silicon layer is better than the condition of using a high-flow (approximately 110 to 60 sccm) sintered gas. However, the surface of the amorphous stone layer deposited under the conditions of low-flow siloxane gas has many bump defects, and the number of the bump defects is larger than that under the conditions of high-flow siloxane gas. occasion'. That is, if the above-mentioned low-flow process conditions are applied to a CD system of -22 μm field people, these protrusion defects will affect the subsequent etching process and be transferred to the substrate σ interlayer oxide layer) to generate pits (Pits). So when applying:

These defects (protrusions and% = / N ^) will be severe in a process equal to 0.22 micron.

';; ®〇3-8504TWF (N1); TSMC2002-0504; Jacky.ptd 200411746 V. Description of the invention (2) " ----- It seriously affects the non-deposition of CVD conditions using low-flow silicon-methane gas. The performance of the crystalline silicon layer affects the reliability of the device (reliabiHty). In the following, the disadvantages of the prior art will be explained using FIG. Please Mai according to the first figure, firstly, a gate oxide layer 12 is grown on the surface of the silicon substrate; and then, the above-mentioned Shixi substrate 1 with the gate oxide layer 12 formed thereon is moved to, for example, a low voltage. 10W pressure vapor deposition (LPCVD) device. Next, inert gas such as silicon methane (SiIU gas and nitrogen (ν2)) with a low flow rate (60 to 10 sccm) is introduced into the above-mentioned chemical vapor deposition apparatus. Furthermore, the above-mentioned chemical vapor deposition is set at the reaction temperature The adjustment is about 500 to 600, and the reaction pressure is adjusted to about 0.07 to 0.09 torr for chemical vapor deposition, and an amorphous layer is formed on the silicon substrate to form the gate oxide layer 12 described above. Silicon layer 丨 4. However, many bumps 16 are formed on the surface of the amorphous silicon layer 14, and these bumps 16 will affect the subsequent engraving process and transfer to the gate oxide layer 12 to generate pits 18 , Which seriously affects the yield performance of the device. That is, after patterning the amorphous silicon layer 14, it can be found that the surface of the gate oxide layer 12 has recesses 1 8 caused by the influence of the protrusions 6 Here, the process of patterning the amorphous silicon layer 4 is not shown. In addition, in US Patent No. 5,648,293, it is disclosed that the amorphous silicon is improved by a high frequency discontinuous discharge method. Layer quality and deposition rate However, this method must be purchased an expensive control device ,, and the discharging process may be months &. Harm to other elements on the substrate addition "in U.S. Patent No. 601781 9, there is disclosed a method of forming

fr 5 & 03-8504TWF (Nl); TSMC2002-0504; Jacky.ptd 200411746 watts, description of the invention (3) 4 crystalline layers / rijr Θ >## 声 @ # + 非 说 告 层This patent is based on the use of triple denierization to eliminate the rough surface of the polycrystalline silicon layer. SUMMARY OF THE INVENTION The present invention aims to provide a method for manufacturing an amorphous stone layer with reduced surface defects, so as to improve the performance of components, which can be applied to higher-level processes. ^ ^ 目的 1 Another purpose is to provide a method for manufacturing a gate electrode, which can adjust the performance of the gate electrode by utilizing ί Ϊ two-step deposition. 0 @ ^ ^ For the purpose described, the present invention provides an amorphous phase difluoride with reduced surface defects :: A: including the following steps: placing the substrate in a chemical gas phase: introducing a low-flow siloxane ⑻tie) gas in the chemical rolling phase " L product is placed in the middle 'to deposit a first Shiba, Liudan n — Qingle non-Japanese stone Xixi layer on the substrate, of which the low dry Wai is probably 60 ~ 100sccm; and a gas sintering gas in the chemical vapor phase M ^ φ,, ^ ^ μ 予 孔 齐 / 儿 衣衣, used to deposit a second amorphous silicon layer on the first amorphous On the silicon layer, the range of beans φ, 、, 曰, 11 η, 1 π π, and 回流 reflow ® is in the range of 11U ~ IbOsccm 〇According to the above purpose, the present invention adopts the address ^ A ^ 5 and also provides a kind of reduced surface A method for manufacturing a defective amorphous silicon layer is used in a gate process. The manufacturing method includes the following steps: First, a substrate of a V-body is provided, and a gate emulsion layer is formed thereon; The substrate was placed in a chemical vapor deposition I. Then, a low flow rate of Shi Xiyan mSlH4) gas was introduced into the chemical In the vapor deposition device, it is used to deposit a first amorphous silicon layer on the gate oxide layer, and the range of the low and medium flow is about 6HGGS. Then, the high-flow Mengjia gas is introduced.

200411746 V. Description of the invention (4) The body is used in a chemical vapor deposition device for depositing a second amorphous silicon layer on the first amorphous stone layer, and the range of high flow is probably 丨 04 6 Sccm The first amorphous stone layer and the second amorphous stone layer form an amorphous stone gate layer. Then, the amorphous stone gate layer is patterned. Then, a furnace annealing process is performed. Then, an ion implantation process is performed to implant the dopants into the first amorphous stone layer and the second amorphous stone layer. And, a rapid thermal annealing (RTA) procedure is performed, so that the doped first amorphous silicon layer has a first piece of resistance value, and the doped second amorphous silicon layer has a second piece. Resistance value, where the resistance value of the second piece is greater than the resistance value of the first piece. According to the method of the present invention described above, the overall performance of the gate layer (for example, resistance characteristics) can be adjusted by controlling the deposition day-to-day ratio of the low-flow silicon methane gas and the high-flow silicon halide gas. The invention is described in more detail below with reference to the drawings and preferred embodiments. Embodiment: The following is a cross-sectional view of the process shown in FIG. 2 to describe a preferred embodiment of the present invention. Referring to FIG. 2, a semiconductor substrate 20 is provided, such as a Shi Xi substrate (s i s u b s t r a t e). Then, for example, a thermal oxidation process or a deposition process is used to grow a gate oxide layer 30 on the substrate 20 in a high temperature oxidation furnace (about 900 ° C.) in which oxygen is present. Then, referring to FIG. 2, the substrate 20 having the gate oxide layer 30 formed thereon is moved to a low-pressure chemical vapor deposition (LPCVD) device, such as a low pressure chemical vapor deposition (LPCVD) device. Then, first

> §503-8504TWF (N1); TSMC2002-0504; Jacky.ptd Page 7 200411746 V. Description of the invention (5)-Introduce low-flow (about 60 ~ 100sccm) silicon methane (SiH4) gas and use it as &Amp; Inert gas such as nitrogen pressure & equilibrium gas is in the above chemical vapor deposition apparatus. In addition, the reaction temperature of the chemical vapor deposition device is adjusted to be between about 500 ° C and 600 ° C, and the reaction pressure is adjusted to be about 0 · b0 · 〇1 t〇rr to perform chemical gas deposition, A first amorphous silicon layer 40 is formed on the substrate 20 to form the gate oxide layer 30. Among them, the process conditions of the chemical vapor deposition device in this step are preferably controlled to 5 4 〇 ～ 56 6 〇, 〇8 ～ 〇. 09 torr ° Secondly, please still according to Figure 2 and then import High flow rate (approximately 1 ^ 10 ~ 16 ^ CCm) of silicon methane (siHj gas and nitrogen (I) net non-reactive gas used as equilibrium pressure in the above chemical vapor deposition device. And, The reaction temperature of the device is adjusted to about 500 ~ β ^, and the reaction pressure is adjusted to about 0.001 torr for chemical vapor deposition, and the first amorphous silicon layer 40 is formed. A second amorphous silicon layer 50. Among them, the process conditions of the chemical vapor deposition device in this step are preferably controlled at 540 ~ 5 60 ° C, 0 · 〇8 ~ 〇 · 09 torr. Thus, The first non-imprinted stone layer 40 and the second amorphous silicon layer 50 form a stacked amorphous silicon gate layer 60. It should be particularly noted that the second amorphous silicon layer 5 〇 It is possible to suppress a bump def ects growth mechanism on the first amorphous silicon layer 40, so the present invention The step of depositing (dua; [steps deposit ion). The number of raised defects formed amorphous silicon gate layer surface is less than 6〇 In this conventional method, the inventors provide a comparison of the number of defects in the surface of the protrusion "table

Page 8 200411746 V. Description of the invention (6) One "is used to compare the surface condition of the amorphous silicon layer deposited by the present invention with the conventional one. The test method is the number of raised defects measured in five positions on three wafers (unit: (/ 25 μm square)). Table 1 The method of the present invention (minimum flow rate of 144.8sccm, low flow rate of 9Qsccm, and high CVD methane gas CVD strip). Known method (only CVD device using low flow rate of 90 sccm silicon methane gas) Position 1 Position 2 Position 3 Position 4 Position 5 Position 1 Position 2 Position 3 Position 4 Position 5 1st 28 21 20 19 14 1st 50 48 50 48 39 2nd 30 21 20 .19 14 2nd 48 44 43 46 42 3 pieces 25 16 16 17 23 3 pieces 44 44 42 35 値 20.2 値 値 44.4 ------- That is, the pre-crystal layer can be seen from Table 1 above, according to the method of the present invention (low flow rate and then high) Flow two-stage deposition) can effectively reduce non-surface protrusion defects. After that, a patterning of the amorphous broken gate layer 60 is performed, and the clothes (such as a quilt) are etched to obtain a desired gate shape / pattern.厶 一, ′ 々 彳 曼, j, and a furnace annealing (f u r n a c e a η n e a 1 i n g) program, retreat, person 〃 < example of human condition

Lion-8504TW_; TSMC2〇㈣5〇4; Jacky._ Page 9 200411746 V. Description of the invention (7) If it is about 8 0 ~ 90 0 ° C, 20 ~ 40 minutes. To simplify the description here, the above patterning process (ie, the gate patterning process) is not shown. Furthermore, in order to reduce the resistance of the amorphous silicon layer 40, 50 (ie, the amorphous silicon gate layer 60) to be suitable for the application of the gate electrode, an ion implantation procedure (i mp 1 an ti ng, here taking n-type dopants as an example), implant an ion-implanted N-type dopant at a concentration of about 5 · 5 E1 5 at 〇m / c m2 (for example, filling and crushing miscellaneous ions) into the brother An amorphous stone layer 40 and a second amorphous stone layer 50 are included. Next, a rapid thermal annealing (RTA) procedure is performed. The rapid thermal annealing conditions are, for example, about 1000 to 1100 C and 20 to 40 seconds, so that the doped first amorphous stone layer is formed. 40 has a first sheet resistance, and the doped second amorphous silicon layer 50 has a second sheet resistance, wherein the second sheet resistance is greater than the first sheet resistance. It should be particularly explained here that according to the above-mentioned process of the present invention, it is possible to control the deposition time ratio of the low-flow siloxane gas to the high-flow siloxane gas (that is, to control the first amorphous silicon layer 4). 0 and the thickness of the second amorphous silicon layer 50), and adjust the electrical properties (eg, resistance characteristics) of the entire gate layer. In other words, the present invention can also appropriately adjust the performance of components according to the customer's needs (trade-of f). An example is given here, but the scope of the present invention is not limited. After the above N-type doped ion implantation procedure and annealing procedure, the first sheet of the first amorphous silicon layer 40 deposited by introducing a low flow rate of 90 sccm of the silicane gas at the beginning has a resistance value of approximately 1 8 0 Q / □; and the second amorphous stone layer 50 of the second amorphous stone layer deposited by the introduction of a high flow rate of 1 4 4 · 8 sccm of the stone yoke gas was originally ___ 11 11 u§mm National Logic __ 11 11 _ country _ 丨 ^ m〇3-8504TWF (Nl); TSMC2002-0504; Jacky.ptd Page 10 200411746 V. Description of the invention (8) Therefore, the inventor presumes that the resistance value of the two pieces of the invention is substantially 172 Ω, which can be controlled by The deposition time ratio of the low-flow siloxane gas to the high-flow silicon body (tuning l0w / high deposition to stop holes rat 1 0), and adjust the electrical properties of the gate layer (for example, resistance characteristics) . The inventors also found that if the P-type doped ion implantation procedure is used, the initial sheet resistance of the low-flow and high-flow siloxane gas deposited is almost 154 Ω / mouth. 、] Non-Japanese silicon layer In addition, it should be specifically explained here that although the above is based on the one-cycle low-flow and high-flow siloxane gas deposition example, in practice, the user can use more To achieve the purpose of reducing surface defects, the process of "re-depositing ^^^" is performed. For example, as shown in FIG. 3, the process of the present invention is repeated two times, so the first amorphous silicon layer 4 is formed. The second non-silicon layer: the silicon layer 50, the first amorphous silicon layer 40, and the second amorphous silicon layer 5 are composed of: an amorphous silicon gate layer 7 of the stack. [Features and Effects of the Case ] The process of Ming Zhi is characterized by: placing a substrate in a chemical vapor deposition chamber. First, a low-flow Si Xi 4 (SiΗ 4) gas is introduced into the sclerosis phase to deposit a first layer. An amorphous silicon layer is rubbed on the substrate, the range of the low flow rate is about 60 ~ 100 sccm. After that, a flow of siloxane gas is introduced into the chemical vapor deposition device on the first non-reading ... high flow: Range: 1 1 0 to 16 0 sccm. Therefore, the advantages of the present invention are at least: (1) · According to the present invention, it can be effective Absence amorphous silicon layer to reduce the surface

? ^^ b503-8504TWF (Nl); TSMC2002-0504; Jackyptd '---' Page 11 200411746 V. Description of the invention (9) Depression, thus reducing defects in the substrate (or gate oxide layer), so it can improve Product reliability and reduced leakage current. (2) According to the present invention, when an N-type doped ion implantation procedure is used, the overall gate layer can be adjusted by controlling the deposition time ratio of the low-flow siloxane gas to the high-flow silanol gas. Electricity. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make changes and retouches without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application.

'^ 4 1) 503-8504TWF (N1); TSMC2002-0504; Jacky.ptd Page 12 200411746 Brief description of the diagram The first diagram is formed according to a conventional process (CVD conditions using a low flow rate of silane gas) A schematic cross-sectional view of an amorphous silicon layer is used to illustrate the conventional disadvantages. Figure 2 is a schematic cross-sectional view of an amorphous silicon layer formed according to the process of the present invention. Figure 3 is a schematic cross-sectional view of an amorphous silicon layer formed according to the process of the present invention. Explanation of symbols 10, 20 ~ substrate; 1 2, 3 0 ~ gate oxide layer; 1 4 ~ amorphous silicon layer; 16 ~ protrusion defect; 18 ~ recessed hole defect; 40 ~ first amorphous silicon layer; 50 to a second amorphous silicon layer; 60, 70 to an amorphous stone gate layer.

^-^ (g03-8504TWF (Nl); TSMC2002-0504; Jacky.ptd page 13

Claims (1)

200411746 "Scope of patent application 1. A method for manufacturing an amorphous stone layer with reduced surface defects, comprising the following steps: placing a substrate in a chemical vapor deposition device; introducing a low-flow siloxane (S i H4) gas is used to deposit a first amorphous stone layer on the substrate in the chemical vapor deposition device, wherein the low flow rate range is about 60 to 10 Osccm; and a high flow rate of silicon methane gas is introduced. In the chemical vapor deposition device, a second amorphous silicon layer is deposited on the first amorphous silicon layer, wherein the range of the high flow rate is about 110 to 160 sccm. The method for manufacturing an amorphous silicon layer with reduced surface defects, wherein the deposition temperature in the chemical vapor deposition device is controlled to be within the range of 500 to 600 ° C. The method for manufacturing an amorphous silicon layer with reduced surface defects as described in the above item, wherein the pressure in the chemical vapor deposition device is controlled to be within a range of 0.1 to 0.1 1 t 〇rr. Reduced surface as described in item 1 A method for manufacturing a recessed amorphous silicon layer, wherein the process conditions in the chemical vapor deposition device are approximately 540 to 560 ° C, 0.08 to 0.09 torr. 5. The method of reducing surface defects as described in item 4 of the scope of patent application The method for manufacturing an amorphous silicon layer further includes the following steps: Introducing an inert gas into the chemical vapor deposition device, and the inert gas is used to balance the pressure in the chemical vapor deposition device. The method for manufacturing an amorphous silicon layer with reduced surface defects according to item 5, wherein the inert gas includes nitrogen. P: ^ 0 $ O3-85O4TWF (N1); TSMC2002-0504; Jacky.ptd Page 14 200411746 VI. Application for patent scope 7 · A method for manufacturing an amorphous stone layer with reduced surface defects, applicable to a gate The process includes the following steps: providing a semiconductor substrate on which a gate oxide layer is formed; placing the substrate in a chemical vapor deposition device; introducing a low flow rate of silicane (SiH4) gas into the substrate; In a chemical vapor deposition device, a first amorphous silicon layer is deposited on the gate oxide layer, wherein the low-flow range is approximately 60 to 100 sccm; and a high-flow siloxane is introduced. A gas is used in the chemical vapor deposition device to deposit a second amorphous silicon layer on the first amorphous silicon layer, wherein the range of the south flow is approximately 1 10 ~ 1 6 0 sccm; The amorphous stone layer and the second amorphous stone layer form an amorphous silicon gate layer. 8 · The method for manufacturing an amorphous stone layer with reduced surface defects as described in item 7 of the scope of the patent application, further comprising the following steps: patterning the far-amorphous broken anode layer; performing furnace annealing (furnace annea 1 ing) A procedure; performing an N-type dopant ion implantation procedure, implanting the N-type dopant into the first amorphous stone layer and the second amorphous stone layer; and performing a rapid thermal annealing ) Program, so that the doped first amorphous silicon layer has a first sheet resistance value, the doped second amorphous silicon layer has a / sheet resistance value, wherein the second sheet resistance value is greater than The first slice electrical limit. 9 · Amorphous to reduce surface defects as described in item 7 of the scope of patent application B4®03-8504TWF (N1); TSMC2002-0504; Jacky.ptd Page 15 200411746 VI. Application for patent scope Manufacturing method of Shixi layer, which also includes controlling the low flow rate of silicon methane gas and the high flow rate The silane gas deposition time ratio adjusts the resistance characteristics of the gate layer. I 0 · The method for manufacturing an amorphous stone layer with reduced surface defects as described in item 7 of the scope of the patent application, wherein the semiconductor substrate is a stone substrate. II · The method for manufacturing an amorphous stone layer with reduced surface defects as described in item 7 of the Shenjing patent scope, wherein the deposition temperature in the chemical vapor deposition device is controlled to be within a range of 500 to 600 ° c. between. 1 2 · The method for manufacturing an amorphous stone layer with reduced surface defects as described in item 7 of the scope of the patent application, wherein the pressure in the chemical vapor deposition device is controlled to be in a range of 0:! ~ 0 · 01 t〇 between rr. 1 3 · The method for manufacturing an amorphous stone layer with reduced surface defects as described in item 7 of the scope of the patent application, wherein the process conditions in the chemical vapor deposition device are approximately 540 to 56〇t :, 0.08 ~ 〇β〇9 torr. 1 4. The method for manufacturing an amorphous stone layer with reduced surface defects as described in item 7 of the scope of the patent application, further includes the following steps: Introducing an inert gas into the chemical vapor deposition device, the inert gas is used for To balance the pressure in the chemical vapor deposition device. 1 5. The method for manufacturing an amorphous silicon layer with reduced surface defects according to item 4 of the scope of the patent application, wherein the inert gas includes nitrogen. 16. The method for manufacturing an amorphous silicon layer with reduced surface defects as described in item 8 of the scope of the patent application, wherein the ion doping concentration of the medium dopant is approximately 5. 5E1 5 atom / cm2. 1 7 · Amorphous with reduced surface defects as described in item 8 of the scope of patent application | ?? i503-8504TWF (Nl); TSMC2002-0504; Jacky.ptd Page 16 200411746