TW200411565A - Processor with demand-driven clock throttling power reduction - Google Patents

Abstract

A synchronous integrated circuit such as a scalar processor or superscalar processor. Circuit components or units are clocked by and synchronized to a common system clock. At least two of the clocked units include multiple register stages, e.g., pipeline stages. A local clock generator in each clocked unit combines the common system clock and stall status from one or more other units to adjust register clock frequency up or down.

Description

200411565 (1) Description of the invention: [Technical field to which the invention belongs] The reduction and control of micro or systemic palm force consumption composed of a plurality of timed components or units. [Previous technology]: The advancement of conductor technology and wafer production has led to a steady increase in the clock frequency of the wafer, the number of transistors on a single wafer, and the size of the crystal itself. The corresponding increase in the supply voltage of the wafer. Normally: Power consumption increases linearly with its switching frequency. Therefore, the electric dust is reduced, and the power consumption of the chip is still increased. For ^ Dianbei 'due to the increase in chip power,' cooling and packaging ', and for low-end systems (for example, handheld ports. 石 μ 去 # 丄 丘 7lance, uniform), the battery life must be: reduce performance to unacceptable Under the premise of this :: As a result, the increase in the power consumption of the microprocessor has become a major obstacle to improving performance in the future. After I attacked Feng 7 scalar processor-fetch and issue / execute-an instruction to operate on scalar data operands. Each of these operands is where Shan Guang is everywhere ... The second line is: = An example of a problem. , '~' Process multiple instructions while maintaining a single Ultrascalar processor can fetch instructions in a specific machine cycle. In addition, 'fetching of each instruction'. Performing multiple pipelines to actuate the advance-step control is usually a permutation / ordering. Ultra scalar noodle company _wer / PowerPC processor, examples of ② include, Pentium 86560 200411565

Pro (P6) processes are series, Puyang's uitraSparc processor and Hewlett Packard Company (HP) PA-RISC processor, and the former Compaq (now merged with HP) Alpha processor family. Vector processors are generally arranged in a pipeline that can perform an operation on an entire number of arrays of a single structural step or instruction. For example, a single instruction can add each item of array A to the corresponding item of array B, and store the result in the corresponding item of array C. Vector instructions are usually supported as an extension of the basic scalar instruction set. Only encoding segments that can be vectorized in larger applications can be executed on the vector engine. The vector engine can be a single, pipeline execution unit, or it can be organized into an array or a single multiple data (SIMD) machine. The single inStructiary has multiple identical execution units, which simultaneously execute the same instruction on different data. Both are vector processors.

Cray Super Electric For example, in general, a stepped timing processor or system has a single MU perceptual master clock, and all units or components that make up the unit. The proportion of the clock may be greater than the specific clock unit of the main clock cycle. Faster or slower. This is usually determined by designing static reservations and presets of such clocks. For example, the Intel Indie 4 processor's integer pipeline clock is twice as fast as the chip's master clock. This doubles the pump or waveform pipeline technology familiar to those skilled in technology. On this day, the clock doubling technology improves the processor's execution speed and speed. performance. However, the speed of the bus is synchronized with the speed of the off-chip memory. Therefore, the large M arithmetic logic core fetching new technology processor has a crystal foreign exchange stream and cache memory, and its operation ... The slave clocks of Congru and Feng are approximately several times the positive clock frequency of the main processor. Generally, the operating frequency of these clocks is in the design system 86560 200411565. This means that the Titan generation processor complex may have multiple clock speeds. The daily power is σ times the pump and the waveform pipeline technology is also used for higher-end Machines' to mitigate performance mismatches between processors and external buses or memory.

Rabaey, Jan Μ and ㈤ Brewing, discussed and edited and published Zigui "Academic Press, 1996 Edition" "Low Power Design Method" illustrates the power reduction method using synchronous clock interrogation. Among them, it can be stopped at a regeneration point. Clock 1 can be buffered for 4 li on the next day | § 〇ocai cioc buffer; lcb) feeds the special day area, component or latch. At the coarse control level, the clock is gated along the functional boundary. At the precise control level, the clock is gated within a separate lock-in benefit. For example, Gerosa et al. Published a paper "2.2 W, 80 MHz ultra-pure; .cu processing s" published in the IEEE journal "Solid Energy Two Modifications μ a + ^ Dankouxin Circuits" (Section 144 ( ) To pages 1454) describe the gated clocks for different execution units of instructions scheduled and executed in each cycle. When Hada processes sequences of instructions of a certain functional category (such as pure integers or pure floating-point instructions), coarse-grained unit-level clock gating is advantageous. When the input workload is such that the processor sees only whole digits, the clock of the floating-point unit is disabled and =. Similarly'H can be stopped for integer units during pure floating point operations. This can save a considerable amount of chip power. Usually, the software uses borrowed sequence instructions or uses hardware to detect the idle period to partially implement coarse idle control. Fine idle control is usually implemented locally by avoiding unnecessary propagation of thermal effects or insignificant data during instruction decoding. One cause and effect of gated information = two: Γ starting point flow to downstream stage or unit is called feed-forward flow. This type of: ... includes a loop, which has a significant backward flow, but the causal predicate "is still considered a feedforward procedure. Therefore, coarse interposition control and refined intermediation 86560 200411565 are self-triggered feedforward. On the other hand, using The downstream pipeline suspends the signal management feed-forward flow to constitute a loop control system. Here, the control information flow is from the “effect” downstream to the “cause” inside the upstream. Coarse-grain and fine-grain pause control systems are mainly used to prevent overwriting of effective pause data in pipeline processors, however, these mechanisms can also be used to save power consumption. For example, Jacobson et al. Proposed a fine-grained pause propagation mechanism to reduce the power of synchronous pipelines in the paper "Synchronous Interlocking Pipelines" at the Jiangqiu ASYNC-2002 conference in April 2002. This mechanism uses "effective "Wu Wu supplements the more traditional fine-grained feed-forward mechanism of clock gating, as described by Gerosa et al. Above, see also (3 (^ buck et al. Η) in terms of power considerations in microprocessor design" (1998 From the rule _ design automatic = pp. 726 to 731W199wq)) MnJac〇b_u's published fine-grain pause gating (feedback) mechanism is not like the invention used to control the rate of information flow (through clock or bus bandwidth) Regulation). The coarse idle control generates at least two problems that must be solved. First, the large transient current drop and gain can cause the inductor (Ldi / dt) noise level to be unacceptable on the wafer supply voltage. The second is' gating The switching program requires extra cycles to maintain correct functioning. For fine-grained phase changes in workload, switching too frequently between gate actuation modes can cause unacceptable performance degradation ^ and 'the latest fine idle control relies on the bureau Interim signals or conditions for pipeline-level clock gating 'for example based on invalid data or irrelevant operator conditions. These latest methods do not generate gated signals based on expectations or expectations. Therefore,' timing requirements are often important because of interrogation signals A suitable period must be provided before the judgment for the operation of the error-free clock interrogation. Gowan, M. 86560 10 200411565 K., Biro, L.L. and Jackson, D.B. in 1998 acm / IEEe Design Automation Conference Paper "Alpha 2 丨 Microprocessor Design Power Test $" (pages 726-731) (June 1998) illustrates how these constraints can greatly complicate design timing analysis Even the clock frequency performance is degraded. Whether the basic control mechanism is feedforward (causal flow) or feedback (causal flow), the latest clock control technology (regardless of coarse or fine) is only for space control. This is because, Application information is used to eliminate redundant clocks in affected areas, regardless of the time activity or history of those areas or other areas of the machine. It depends on Fischer units and stages (such as execution pipelines or .Title column) Activity status and event I are not: to adjust the clock or resource rate of upstream (producer) in non-adjacent areas (such as instruction extraction or scheduling unit), speed, and speed Similarly, the events and events in the upstream producer area or the event are not feed forward to adjust the clock or poor flow rate of the downstream consumer. Moreover, if L is now activated or not activated, the clock is generally closed The signal may or may not have an effect. Therefore, there is a need to improve the connected t that can operate at fine granularity of time and time without causing (extra) degradation in performance and large current / voltage swing to the grass-roots circuit. [Summary of the Invention] This The clear purpose is to reduce performance loss. -The power consumption is not obvious at the same time. The present invention is a synchronous integrator. Circuit components or units are passed by a common clock such as a scalar processor or ultra-scalar. At least, the common system clock is synchronized and synchronized to a stage, such as a pipeline stage. Each eaten / picked time unit includes a plurality of registers. A local clock generator node in the early guard unit 86560 200411565 ΠΓ system clock and the pause state of one or more other units to adjust the temporary storage up or down Clock frequency. [Embodiment] Referring now to the drawings, more specifically, item 1 shows a typical latest technology pipeline, a high-level block diagram of an example of the Piri processing, and a corresponding instruction sequence diagram. The main function data path is divided into two main components or units, which are usually called instruction unit (instrUetiGn unit; 1) T2 and execution unit (⑽⑽⑽unit; E_UNIT) 104. The present invention does not describe the [unit 10 technology] many fine-molecular units and functional logics (such as branch prediction logic) in the unit 104, so 'the explanation of the entire clock control for processing is concise and omitted. The processor 100 in this example is representative of the pipeline scalar design. This design does not include clock gating to prevent redundant timing of the unit, sub-unit or its included auxiliary storage 'resources. " Chip-mounted misstores accessed by a single 7G 1G2 or 1G4-or both include register file (REGFILE) 106, instruction cache memory ^ Gnst and tion cache; ICACHE) 108 And data cache memory (such as cache; DCACHE) 110. REGFILE 106 is generally a shared resource that can be accessed from units 102, 104, so it is considered a separate entity. icache 08 is the first termination stage of the I-Unit pipeline, so it is considered as part of the unit 102. DCACHE 110 is generally accessible separately from E_unit 104 and is therefore considered part of E-unit 104. Two separate local clock buffers 114 each amplify and allocate a common synchronous clock 115 to a corresponding one of the cells 102 and ι04. Each unit 102, 104 includes an input queue 116I, U6E, and a pipe 1181, 118E. As necessary, in the unit 102 and the unit 104, 86560-12-200411565 may have a further level of LCB 2, 114, which is used in the common system, field knife allocation, amplification and control. One . The electronic private instruction is included in the first stage of the I-unit pipeline, IC ACHE 108. Suddenly in a rush.

Two again, under the conditions that may cause ICACHE, ICACHE 108 may suspend a variable number of processor cycles. 4 The suspension implies an adaptation failure to the previous instruction transfer level (ie, the lower level of the instruction memory level). )Impact. In addition, the synchronous clock continuously drives each unit through lcd ι2, ιΐ4, regardless of the pause in the pipeline. Switching capacitor modulation and pattern bit change cause power consumption changes' but the range of change is small. Because of &, from the beginning of the program execution to the .σ beam, the monitoring period consumes approximately the same energy every day (here it is expressed in standard energy units). Therefore, considerable energy can be saved by using power saving techniques, especially the power saving method according to the present invention. During code generation, coarse idle control can be synchronized by a compiler that inserts special instructions included in the instruction set structure, or these instructions can be issued by the operating system, such as when implementing a special interrupt or in a certain context When switching. At the coarsest control level, a special sleep-type instruction or command may be issued. The special sleep command may generate a disable signal to stop the clock of the selected part of the chip for a period of time. This same sleep command can also be used to disable instruction fetching. Similarly, when the disable signal becomes negative, or after the sleep cycle, an implicit wake-up is initiated, or an explicit asynchronous interrupt can be used to achieve wake-up. As is well known to those skilled in the art, various power saving modes (such as nap, light sleep, or sleep) can be provided by a clock distribution tree that is selectively disabled at each level of the LCB level. At the next level of finer granularity, whenever the compiler can 86560 -13-enough to statically predict the calculation phase, start and close the heart of a particular unit. Insert special instructions, open and close 1 inch, such as the clock of a floating point unit. It may include a self-detection mechanism. When a unit is allowed to deactivate its own clock leaf x and idle, it is allowed to measure the part of the processing: In the hardware, you can design logic to detect some or all idle areas. Trigger deactivation of a # ^ ξι! ^ ^ —, 里. Calling students also self-initiated in a similar manner based on new tasks received based on deactivation or sleep orders. Min Zao-Zhong: Example 2: 1: Control 'Dynamic Definition Signals' Periodic Gating of Local Timings ~ Yes, Zuo Tian Zuo: Ultra-scalar machine, the processor executes cycles after instruction decoding, 疋 σ ik Clock, ^ ^ in the early days with η go bed Yayama sword shame & 逞. This method reads that the processing of the first-order mechanism works well within 11, so it can be clear and enough time in advance "g month eight" to make a closed control decision (that is, when the calculus or dispatch). If Yu Yu Issue out of order in a chaotic order, then you can generate these gate control letters even at the time of the transaction. Even in any pipeline data path, you can dynamically detect and selectively prevent redundant timing 'for example' along the logical pipeline. Propagate a data valid flag, and set the data valid flag only when it is generated from the periodic data of f. Then, the logical level data valid flag can be used as a clock actuation money to set the level The output latch is crying. Ll_ ^ Therefore, in these subsequent pipeline stages, there is no need to time the invalid data. These pipeline stages can be referred to as fine-grained, effective bit-based pipeline-level clock gating. Sproch et al., US Patent No. 6,247,1342 B1, "Pipe-Level Gating Method and System in Power-Saving Operation Pipeline Circuits" 86560 200411565 states: a processor whose logic will be implemented at the _th level of the logic One w period Does not count changes in the pipeline received any new operational storage yuan recognized as independent. Detect such unconditional signals as irrelevant: Stop the clock of the first stage, and then continuously deactivate the clock of the subsequent stages. Τ ◦hnishi, M., Yamada, a ”N〇da, Η and ^^, Ding Dm International Workshop on Low Power Electronic Products and Design (Int · > ρ_% L⑽ P〇wer Electronics and Design; ISLpED The article "Methods for Redundant Timing Detection and Power Reduction by Level Design" (pages HI to 136) in the publication) describes other more detailed 4-timing detection mechanisms to prevent timing of various redundant latches. As mentioned above, regardless of the coarse or fine control, these latest technology idle control mechanisms are self-triggering, space or feedforward, that is, the gate control conditions or signals are locally produced according to the condition of the idle or invalid state of the unit, and Avoid unnecessary cycle-by-cycle clock and data propagation when such invalid or idle state bits are present. A unit can be an entire area or a functional unit, or it can be a pipeline-level latch group. On the contrary, in the first specific embodiment, the scalar pipeline processor with a demand-driven clock adjustment and an instruction unit with an execution unit Eecution unit; E_unit can be adjusted to operate. Xianxuan established a producer-consumer relationship between the two units. The producer I unit forwards the existing data actuation instruction to the execution unit for processing at a rate not faster than the execution unit can accept. Each The unit maintains an active state register with at least one bit of information. In this specific embodiment, the PE unit pair is clocked by a common synchronous clock 86560 -15- 200411565. However, the clock of each unit is based on The local unit activity information transmitted between units is locally modified and controlled. The local clock control of each unit can be a function of the activity status information of the local unit and the remote unit f σ early (that is, two early). Figure: Shows a high-level example of a preferred embodiment in which the scalar processing of power control according to the requirements or activities is 120 according to the present invention, the elements of which are the same as those in FIG. The components are the same. In this specific implementation, the processing units 122 to 124 each include activity monitoring and clock control logic I. Kg, the monitoring unit activity level. In a simplified embodiment, a single activity status bit 13 is A pause bit indicates a pause / non-pause condition. When the e_unit 124 senses a temporary ir condition (current or imminent), it determines the pause bit 130. The hailer 位 τ bit 130 is used In order to reduce the clock speed of the unit clock clkj 132 in order to reduce!-Unit 22, and thus reduce (or cut off) the instruction rate to £ _ Unit 124. Depending on the control granularity, & unit activity status or pause bit Wu 130 can adjust its own clock in E_unit 124, such as 1 ^. When unit 124 pauses, CLK_i ^ is raised to its normal clock rate. Similarly, when L unit 122 detects a pause condition ( If an ICAcHE is not missed), after a few cycles, the pipeline 1181 is empty, so there is no poor signal to the unit 124, then the pipeline empty bit 136 is used to lower clk_e 138 to save power. Activity monitoring and clock Control logic 126, 128 This upper / lower joint can be implemented using a variety of different methods, and several examples are provided below. For example, each unit clock can exit one pipeline stage at a time. Similarly, when the brake conditions, "σ 束 日 ^", the The unit clock returns to a pipeline stage again. This control logic allows all unit clocks to exit or return in time without losing valid information 86560 -16- 200411565, without adding interface logic, buffers, and no wasteful pipeline occupation and re-use of energy. Alternatively, the unit clock frequency can be slowed down or gradually reduced to save power and 'if / as required, the clock can then be slowed down to a stop. FIG. 3 shows a first example of an activity monitoring and clock control logic suspension circuit. 'One of the gated control shift registers (GCSR) 150 transfers the system clock 115 to the pipeline. }} 81 individual levels 152. The GCSR 150 is a “litre linear shift register” which is clocked by a 1-bit flip-flop 154. The flip-flop corresponds to each pipeline stage 152. The system clock 115 is AND at each stage, and the AND gate 156 One of the members with gcsr 15〇 selectively passes the system clock 115 as an AND gate output to a corresponding I-pipe stage 152, which together constitute 1 _ (:) ^ 〖158. In this example, E-cell pauses are usually not detected, and the pause bit 13 remains low and is inverted by inverter 160. All i ^ pipelines 1181 by GCSR 150 are in full regulation. Therefore, the AND gate 156 will not The changed system clock 115 is passed as I-CLK 158 to each stage of I-pipe stage 152, each of which is equivalent to system clock 115. As long as the E-unit pause bit 13 remains at 0, one i is shifted to qcSR 150, thereby keeping the I-pipe 1181 in full regulation. In this example, when the E-unit activity monitoring and clock control logic (1 24 and 1 28 in Figure 2 respectively) senses an imminent pause condition, That is, it is determined that the unit pauses at position 130. The pause position 13 is inverted by the inverter 160, and a 10 is presented to GCSR 150, which It is then shifted to GCSR 150 in the next system clock cycle. In the same cycle, the first j • pipe stage (ie, ICACHE 116 from Figure 2) is deactivated, and the data input to I-pipe 181 is suspended while the 0 shifts to and passes GCSR 150. As long as the pause bit 13 is judged, 0865560 -17- 200411565 shifts to GCSR 150 'once every system clock cycle. Each zero then stops from left to right in this example The follow-up pass of the AND AND pole of the wave i 5 6 is the clock. Therefore, the stage of the H-channel clock 158 is closed at some time from left to right. Therefore, it is valid until the pause bit 13G is determined. Continue to I-Official 1181 and enter E-unit. To avoid losing valid information in [pipe U8i ', at least when the available EH buffer (queue U6E) space is equal to! Unit pause bit. Therefore, 'at least S available E-unit buffer (Zai U6E) space is equal to [_ number of valid items in the pipeline, you must determine the unit pause bit ⑽ .: In extreme cases, the latter is directly equal to! _ The length of the pipe 1181. At this point, before the transmission. And D The E-cell queue ii 6E in Nakakata is filled until the number of available (blank) line items equals the number of I_f track levels. E · cell 124 determines the pause bit 13. The blank in the E-cell queue 116E The invalid or invalid items are assumed to be clock-controlled with pre-entered valid bits (to save power), as with traditional fine-grained, level-level clock gating.

Similarly, when Tian Tianzi returned to 0 from 130, that is, when it was detected that the E_unit activity had fallen below the predetermined level, the reverse upward adjustment operation was started. The low value of pause position 130 will resume shifting 1 to GCSR 150, while shifting the valid input material to I-guan 1181. Therefore, the super-continuous follow-up system of the pipeline U8I is actuated step-by-step to keep the surface cycle I-CLK 158, so that the I-channel 1181 resumes normal operation and transfers the data to the fully-adjusted unit 124. Step-by-step gate control ^ cLK 158 off / on prevents large current swings, thereby minimizing the Ldi / dt noise impact of the supply voltage. FIG. 4 shows a second example of a speed reduction circuit 170, which can be used in place of 86560 -18-200411565 f. The suspension circuit of FIG. 3 included in the preferred embodiment of the present invention which is adjusted according to requirements in. The deceleration circuit m is substantially similar to the suspension circuit of FIG. ^, And the common or common components are labeled the same. A lazy selection 1 72 provides an inversion set input and the gate 176 to the flip-flop / bit trigger counter m. When the slow selection bit 172 is high, that is, when judged, the gate 176 selectively passes the system clock 115 to the clock i-bit counter 174. The retarded GCSR 178 is substantially similar to the GCSR 15 of FIG. 3, except that only the final stage output 180 is passed to all AND gates 182. and idle pole a] can be a three-input AND gate, providing the selection function of the AND gate setting in Figure 3. Therefore, the AND gate 182 can combine the final stage output 180 with a corresponding stage output of the system clock 115 and the GCSR (130 in Fig. 3, Xi Yi ☆ 丨 soil &, v 曰) example. The individual output clocks of the and gate 182 correspond to the pipeline stages. In this specific embodiment, the response delay is selected 172, and the clock frequency of the US can be lowered (Q). By judging (determining) the delay selection 172, the dagger unit raises the delay (increase) requirement in the S-star E-unit to the I-single it. In addition, all the characteristics of the I-CLK158 can be maintained—or multiple cycles, as described in Figure 3 above. When the column is almost full, the suspension is triggered __ times, so from GCSR 15 to the corresponding The individual AND idler 182 provides a stop output. As mentioned above, the I-CLK 158 restarts when the length of the E_cell activity queue decreases below a predetermined threshold. Under normal operating conditions, the slow selection 172 is low (to make the i-bit controller output to the GCSR178-a continuous high shift value). Therefore, GCSRm generally includes everything! 'And the system clock 115 passes the unchanged value to stage m. When it is determined to be slow to select 172 to issue the & unit deceleration request signal 86560 19 200411565 (not due to temporary 彳 τ), the AND gate 76 prevents the 1-bit control counter 1M from being triggered. When the slow-selection 174 rises to its inversion group input and the AND gate 176 passes the system clock 115, the 1-bit control counter Π4 is released. Yes! Bit control: Counter 174 starts to trigger the GCSR m transfer. Alternating sequence with 丨:. Once the alternating pattern propagates through the GCSR m, the AND CLK control of the AND pin is activated and deactivated at alternate clock cycles. As a result, this will be treated as a halving of the main system clock frequency provided by I-CLK 158. Fig. 5 is a variation of the specific embodiments of Figs. 3 and 4, wherein the output of individual stages is passed to the corresponding ㈣AND gate. The operation is substantially similar to that of Fig. 4 ', but the final I · pipe clock adjustment may be different. During the adjustment (deceleration) phase, the alternative stage of the pipeline under the 敎 state operation is based on-specific system clock cycle timing ', that is, half of the system clock frequency. Each pipeline level is for demonstration purposes only-significant bit (V). These valid bits usually exist in the structure of the complex pipes and E-pipes in Figure ⑴. According to the traditional feed-forward scheme, the upstream I-Single effective bit system is transmitted downstream to the £ • unit to activate the fine-grained, level-level clock closure control to save additional power. In this example, the effective bits of each pipeline stage provide additional gate control for the AND structure that synchronizes the local stage 'level clock. The implementation of this specific q-channel timing configuration requires a basic circuit (not shown) to prevent valid data from being covered in the pipeline stages during the adjustment (deceleration) mode, such as redundant intermediate placeholders between stages, or possibly duplicate information Master and slave sections of each latch stage stored. Figs. 6 A to B show another example of 11 81 in more detail 1 9 0 and a register stage 192 including an input and a scalar I-pipe corresponding to the sectional view of Fig. 3

Corresponds to the timing diagram. Each pipeline stage 152 is output by. In this example, each of the GCSR 86560-20-200411565 latches is a two-stage latch and a single-bit element that is basically a serial-input / parallel-output register. The two-stage latch 154 includes a first-stage latch m and a second-stage latch 196. The 'stage' latch 194 is the same as the latch of the temporary benefit stage 192. The second-stage latch 196 is actuated from the clock polarity of the first-stage latch 9 4 using a negative clock polarity. Therefore, for example, when the first-stage latches 94 are clocked on the rising clock edge, the second-stage latch urn is clocked on the falling clock edges to ensure that a valid input is provided to the [clock driver 156. As described with reference to FIGS. 3 to 5 and FIG. 6 AsB, the I-clock driver 156 is an AND gate and functions as an AND gate. However, each AND gate 156 may include a clock driver, which may be a two-phase clock driver, if desired. The input block 198 provides suitable clock control logic for selecting a particular type of suspension / latency control logic. Therefore, in the example of FIG. 3, the input block 198 may include a first stage 194 of the first stage latch 154 of the inverter 16o and gCSR 15o. Similarly, for the examples of FIGS. 4 and 5, the input block 130 may include a latch 174 and an AND gate 176. FIG. 7 shows an example of applying the present invention to a pipeline ultrascalar processor 2000. From May 5, the pure processor 200 includes an I-unit 202 and an E-unit 220. The 1_ unit 202 includes an instruction cache memory (ICACHE) 204, a combined IFU / BRU (206) including an instruction fetch unit (IFU) and a branch unit (BRU), a A dispatch unit (DPU) 208, a completion unit (CMU) 210, and a branch history table (BHT) and a branch target address cache (BTAC) ) Of a branch address unit 214. In addition, I-unit 202 includes monitoring and clocking 86560 -21-200411565 control logic 216. The operations of these units 204, 206, 208, 210, and 214 are substantially the same as the widely known counterparts, but as described below, they are timed by monitoring and clock control logic 2 1 6 according to the present invention. Normally, the IFU in ‘IFU / BRU 206 fetches instructions from ICACHE 2 04 per cycle. The fetch bandwidth (fetch-bw), which was processed in the prior art, was fixed to the maximum number of fetch instructions per cycle, and can now be adjusted by the monitoring and control logic 2 1 6 in real time. According to the available free space, IFU places the fetched instructions in the fetch queue (FETCH-Q) of IFU / BRU 206. The instruction in IFU refers to the instruction fetch address register (IFAR) to instruct instruction fetch and provide the next fetch address at the beginning of each cycle. IFU sets each next fetch address of each cycle to one of the following ... (a) The next sequential address of the IFAR value of the previous cycle is increased to be sufficient to satisfy the fetch to fetch in the previous cycle —Q the number of instructions; (b) the target of a branch instruction that is determined or expected to be used in the previous cycle; or (c) the correct fetch address of a branch instruction after determining that it was a previous misprediction. The branch and instruction fetch address prediction hardware 206 includes a branch history table (BHT) and branch target address cache memory (BTAc), and guides the instruction fetch process. According to the decision of the corresponding fixed bandwidth parameter (fetch-bw or disp-bw), each activity fetch (or scheduling) cycle usually fetches (or schedules) a fixed number of instructions. However, when the E-unit 220 indicates that a deceleration / suspension system is necessary, in addition to the above-mentioned clock adjustment, the processor of the preferred embodiment (200 in this example) dynamically adjusts each fetch a bw and / Or the value of disp-bw. The deceleration / suspension (or opposite acceleration / continuation) signal of the E-unit is synchronized. It is a combined function of status signals generated and monitored in the E-unit. These states 86560 -22- 200411565 can include: ⑷ Problem lists are indicated by 229, LSQ 232, fpq 2 and VXQ 246 full or empty; 化) a DCACHE 238 hit or miss event, (C) E_Bus internal bus traffic is congested or non-congested (for example, a single bus can be shared (and arbitrated) to carry completion information to the completed order 24), or (d) due to mispredictions or misconceptions Other forms of executive officers overwhelm or reissue conditions. This example's FXU pipeline can execute processor branch instructions. Alternatively, branch instructions can be executed using a separate parallel BRU pipeline. One or two I-CLKs can be used to adjust and / or compress the ^ unit bus frequency. See the E-Unit to adjust the deceleration / suspension signal of the unit pipeline flow rate without disabling the receiving ICACHE location. Capture half of the data to adjust the clock (such as in the specific access that can be effectively bisected. Therefore, in order to save power in the withdraw mode, half of the items are usually in the private state, the rush state ( Within IFU 206). Generally speaking, depending on the severity of the downstream E-unit deceleration / suspension display, the capture bandwidth can be adjusted to any number of tools in normal mode, including all the way to zero. Similarly, to save power Adjust the scheduling bandwidth (bus bandwidth; disp_bw) to execute less pipeline scheduling instructions to the energy-consuming E-unit as needed or indicated. The E-unit 220 includes a fixed-point execution unit (fixed point execution it 'FXU) 222, a loading {various storage units (i〇a (j store unit; lsu) 224 floating point execution unit (FPU) 226 and vector multimedia extension unit (vector multimedia extension unit unit · 'VMXU) 228. FXU22 2 includes a fixed-point queue 229 and a fixed-point unit execution unit pipeline 230. The LSU 224 includes a load storage queue 232 86560 -23-200411565 and a load storage unit pipeline 23 4. The FXU 222 and the LSU 224 are both The general purpose register 236 communicates. The LSU 224 also communicates with the data cache memory 238. The FPU 226 includes a fixed point queue 240 and a fixed point unit pipe 242, and a fixed point register and a rename buffer 244. LSU 224 It also communicates with the fixed point rename buffer 244. The VMXU 228 includes a vector extension queue 246 and a vector multimedia extension unit pipeline 248. Each unit 229, 230, 232, 234, 236, 238 '240, 242, 246, and 248 Both are essentially the same as the well-known counterparts, but they are timed according to the present invention as described below. Like any typical latest technology ultra-scalar processor, in a specific workload execution phase, FXU 222 and FPU 226 It is likely that the activities are often mutually exclusive. When the Fpu 226 is in use, the preferred embodiment processor 200 may deactivate or slow down the local clock of the FXU 222, and vice versa. In addition, the item Best embodiment allows the processor 2〇〇 LSU224 suspension with FPU226 / slow clock speed of each inner unit such, requires fine adjustment mode clock-driven system has been added to the inter-cell of the coarse grain mode is described. Unlike the above-mentioned preferred scalar processor example, the two units 224, 226 in E_unit 22 have no direct data flow path producer-consumer relationship, that is, there is no direct relationship between LSU 224 and FPU 226. News stream. The communication between these two units 224, 226 is implemented indirectly through data cache / memory and floating point register files 244. Generally speaking, an Fpu pipeline 242 has several levels (for example, 6 to 8 levels in modern gigahertz range processors), and the general LSU execution pipeline 234 is 2 to 4 levels. Therefore, and because the current processor has a large number of scratchpad rename buffers, when DCACHE 23 8 hits 86560 -24- 200411565, LSU pipeline 23 4 tends to run substantially earlier than FPU pipeline 242. On the other hand, in the cluster DC ACHE 23 8 miss stage, the effective LSU path delay can be greatly increased. If a series of quick misses suspends DC ACHE 238, the LSU problem queue 232 fills up, so upstream producers can be suspended. The present invention utilizes this feature by using the activity of upstream resources to drive fine-grained timing clock gating or FPU 226 local clock adjustment. FIG. 8 shows a more detailed example of the LSU 224 and the FPU 226 of the E-unit 200. In this embodiment, the LSU event / active state monitoring logic 250 monitors various LSU queued applications and drives an active state for the LSU 226. In this example, the LSU queue includes a load-store issue queue (LSQ) 232, a pending load queue (PLQ) 252, and a pending storage queue. (Pending store queue PSQ) 254, and DC ACHE 236. Monitor DC ACHE 236, and then log cache memory events. It should be understood that these four units 232, 236, 252, and 254 are selected for demonstration purposes only, and fewer or more queues and events can be monitored. For this example, the LSU event / activity monitoring logic 250 determines an output pause bit 256 that is passed to the FPU 226 in this example. For finer control, a set of pause bits can be used. To control the clock, the pause bit 256 can be transmitted to the I-unit 202 and the IFU or DISPATCH unit 206. For example, at the beginning, the LSU active state monitoring logic output pause bit 256 and the FPU active state monitoring pause output 258 are both determined to make the LSU 224 and FPU 226 in the normal full adjustment operation. If the FPU active state monitoring pause bit 258 is judged and the LSU active state pause bit 256 remains undetermined, for example due to high usage within fpq. The LSU bureau 86560 -25-200411565 clock is slowed down to allow the FPU 226 to catch up with the LSU 224, which is faster than the FPU 226 due to the cache memory hit phase. In contrast, when the LSU active state pause bit 256 is determined and the FPU active state pause bit 258 remains undetermined, the FPU local clock is slowed down. If the suspended bits of the LSU and FPU are both judged / de-judged at the same time, according to other status conditions of E-Unit 220 4! • Unit 202, the local clocks of LSU and FPU are slowed down or turned up the same frequency. Advantageously, in response to activity / inactivity in other processors or system units, the present invention can selectively decelerate, accelerate, or shut down a unit or components within a unit, i.e., the invention has a variable clock control granularity. The local time control of each unit is derived from the activities and resources flowing forward and backward in the direction of the data stream. Unlike all or nothing of the prior art clock gating, the adaptive clock of the preferred embodiment can use feedforward and feedback control to provide a more flexible general clock adjustment mechanism with selectable bandwidth. Information

11. The P, which may be lost when the prior art pipeline unit is closed, can be kept in the unit queue and of a suitable size. The performance degradation caused by such losses owed by the relevant borrowers to 86560 -26- 200411565 was almost reduced to zero. In contrast to the traditional clock gating method, .. ^ ^ ^ ^, the clock rate of the tuning or faster frequency is gradually adjusted, which means to ensure excellent ^ m, more + and) current swing (di / dt) characteristics. Therefore, the clock rate is gradually lower. Therefore, -preferably and concretely, the noise of the pen is minimized, and the power consumption of the system is greatly reduced, and there is no obvious performance loss. The performance loss (average power reduction without sociality) (such as command or call per cycle does not need to be significant: hardware. / It is necessary to strictly adhere to the maximum power consumption and temperature limit. Risi, the present invention can successfully control power consumption, „^ ^ Limit performance loss to a predetermined small time window 'to maintain normal operating conditions and return to normal operation quickly. The dynamic activity levels of individual system components use the early-synchronous clock framework that propagates throughout the chip or system. The clock rate of the component depends on the situation. And it's related to a non-synchronous (or self-timed) unit with local timing: a multi-clock synchronization system with multiple asynchronous clock domains in global asynchronous control: a synchronous system or a processor, The present invention does not require synchronization with the agreement between shaking individual pieces. In addition, the present invention dynamically adjusts the time-to-know rate of various components, and the inductance noise associated with traditional coarse-grain clock gating methods is usually minimized. Although the present invention A number of (exemplary) preferred embodiments have been described, but those skilled in the art will appreciate that the present invention may be used in Modified within the spirit and scope of the scope of patent application. [Brief description of the drawings] From the detailed description of the ten-year specific embodiment of the invention described above, i can refer to the drawings to better understand the above and other objectives, viewpoints and advantages, of which: 2865560 -27- 200411565 Figure 1 shows an example of a typical latest technology pipeline scalar processor and a command timing diagram. Figure 2 shows the preferred pure processor based on the present invention to drive power control with requirements or activities. High level example of a specific embodiment; FIG. 3 shows an example of a suspension circuit for activity monitoring and clock control logic. The cb is shown in FIG. 1 and the intermediate control shift register (GCSR) makes the system clock ^ pipe. Figure 4 shows a second example of a speed reduction circuit that can be used instead of or included in the suspension circuit of Figure 3, which is a preferred embodiment of the invention adjusted according to the requirements i-CLK; Fig. 5 shows a variation of the specific embodiment of Figs. 3 and 4, in which the individual ^^^ is transmitted to the corresponding individual AND gates in a step-out system; Figs. 6A to 3B are shown in more detail to correspond to the faults in Fig. 3 Surface Another example of a scalar ^ pipeline; Fig. 7 shows an example of the present invention applied to a pipeline ultra-scalar processor; Fig. 8 shows a more detailed example of the LSU and FPU of the E-unit of Fig. 7. [Schematic representation Symbol description] 100 pipeline scalar processor 102 instruction unit (I-UNIT) 104 execution unit (E-UNIT) 106 register file (REGFILE) 108 instruction cache memory (ICACHE) 110 data cache memory (dcache ) 112 Local clock buffer (LCB) -28- 200411565 114 115 116E 1161 118E 1181 122 124 126 128 138 150 152 154 156 158 160 170 170 172 174 176 178 180 182 Local clock buffer (LCB) Synchronous clock input ^ [ning Column input 彳 ning column pipeline pipe I-unit E-unit activity monitoring and clock control logic E-unit clock gating control shift register (GCSR) Individual stage flip-flop AND gate I- Clock inverter deceleration circuit slow selection of flip-flop / 1 bit trigger counter AND gate deceleration selection GCSR final stage output AND gate 86560 -29- 192200411565 194 196 198 200 202 204 204 206 208 210 214 216 220 222 224 2 26 228 229 230 232 234 236 238 240 Register level First level latch Second level latch input Block pipeline Ultra-scalar processor I-unit instruction cache (ICACHE) Combined IFU / BRU scheduling Unit (DPU) Complete Unit (CMU) Branch Address Unit Monitoring and Clock Control Logic E-Unit Fixed Point Execution Unit (FXU) Load Storage Unit (LSU) Floating Point Execution Unit (FPU) Vector Multimedia Extension Unit (VMXU) Fixed Point queue fixed point unit execution unit pipeline load storage queue load storage unit pipeline general register data cache memory fixed point queue 86560 -30- 200411565 242 fixed point unit pipeline 244 fixed point register and re- Named buffer 246 Vector extension queue 248 Vector multimedia extension unit pipeline 250 LSU event / activity monitoring logic 252 Shelve loading queue (PLQ) 254 Shelve storage queue (PSQ) 256 LSU activity monitoring logic output pause bit 258 Output 260 FPU activity monitoring pause A array B array C array disp_bw fixed bandwidth parameter fetch_bw fixed bandwidth parameter FPU floating point Row unit FXU a fixed point execution unit load store unit LSU 86560

Claims (1)

200411565 Scope of patent application 1 · A synchronous integrated circuit including a common system clock; and at least two or more clocked units synchronized with the common system clock. Each of these timed units includes: A plurality of register stages; and a state 14 generator, which is connected to a clock and a pause response to adjust the daily frequency of the plurality of registers. 2. I apply for a patent Synchronous integrated circuit with W items, where the local clock = includes-Gated Controlled Shift Register (GCSR) with multiple single-bit counters. Shishen. Month Patent Ganwei Le 2 Synchronized Product Body circuit, the local clock generator further includes a plurality of local clock generators, each of which receives an output of one of the plurality of single-bit counters, aa iA buckle, and combines the output with the system 'To generate a register-level clock. 4. As claimed: the patented synchronous integrated circuit of item 3, wherein the plural stages are stored ..., and the stage of the register pipeline, the GCSR includes the plural single bits for each pipeline stage Counter one. 5. As stated in the patent, the synchronizing integrated circuit of item 4 is a scalar processor. Taixi Qiyueyi includes at least two clocked units in the 4 pure 1 processor including an I- The unit is a ^ knot one ^-early 70 'This unit provides a temporary heart for the E-unit and ° E-Shan Fan provides a pause state for the I-unit. Declaring the synchronous integrated circuit of the fifth item of the patent, the scalar processor goes to 86560 200411565. The step includes: a data cache memory that communicates with the E-unit; a register file that communicates with the unit and The dagger unit communication; ^ unit, including an I-cache memory, a data receiving from the cache memory: M Ning column and a channel to receive data from the queue; and the E-unit It includes a dipper string that receives data from the ^ pipe and an E_pipe that receives data from the Ε- 彳 ning column. 8. 9. 10. If the synchronous integrated circuit of item 6 of the scope of patent application, in each of the L unit and the 5H single fan, each output of the GCSR and the plurality of clock drivers are individually One corresponds to the system clock combination, and each of the multiple Km-drive n gates separately-corresponds to the pipeline stage. The Synchronous Integrated Circuit of Item 7 of the Patent Scope states that a suspended state bit in the middle is a first stage provided to the GCSR. For example, for the synchronous integrated circuit of the seventh scope of the patent application, a pause state bit in the middle: it is provided to a single-bit counter. Unless the 3 pause state bits are determined, when the pause state bit : When judged, the -bit counter performs counting, and an output of the -bit count state is provided to a first stage of the GCSR. The synchronous integrated circuit of item 6 of the January patent scope, wherein the GCSR is: the output is related to each of the plurality of clock drivers ^ a pause state bit system is provided to a single bit count ^ : Hai: The one-bit counter remains set, unless the pause status bit is determined. When the pause status bit is determined, the -bit count 86560 -2-The device implements counting, which is a first level of one-bit counting. A round of output of the device is provided to the GCSR 1 1 · If the beginning of the scope of the application for the patent No. 5 & + circuit, in which the scalar processing cry a ultra-pure ϊ processor, back to the warehouse Xi P — σσ η 口 口… Do this. If the bit is in the paused state, the bit 70 further adjusts the bit-buffer memory to capture the bandwidth. 12: Synchronous integrated circuit with the scope of patent application No. 11 in which the E-unit package is cut by one. Fixed-point order S, which receives instructions from the red list it and communicates with the general-purpose state / rename buffer unit;-load and store the order t which receives the instructions from the unit 1 and _general register / Rename the embroidery and leave a Ώ σ ^ 绫 Chongzao Wu and a data cache memory communication; "Yu Diaozao 'it receives instructions from the K unit and and-floating point temporary storage benefits / rename buffer Unit communication, the load storage unit further-the floating point register / rename buffer unit communication, the load ticket 7L provides a pause status for the 4 point unit, and the floating point unit stores the load The unit provides a pause state; and a home multimedia extension unit that receives instructions from the unit and communicates with a completion unit of the I-unit. • The synchronous integrated circuit as claimed in the scope of the patent application, wherein the L · unit further includes: an Iβ cache memory;-an instruction fetch unit / branch unit (IFU / BRU) which receives the Iβ cache memory And the scheduling unit, which receives the (IFIj / BRU) instructions and provides the received instructions to the E-unit 86560 200411565. For example, please apply the synchronous integrated circuit of item 12 of the patent scope to the combination of the -output system of each stage and the «system clock, and respectively gate the corresponding pipeline stage. 15. ^ The synchronous integrated circuit of item 14 of the scope of patent application, wherein the -pause state bit is provided to the first stage of the GCSR. 16. If the synchronous integrated circuit of item 14 of the scope of patent application, w 纟 R ,; the pause status bit is provided to a single-bit counter, the early-bit 7L count ㈣ remains set, unless the pause status bit When the suspend state bit is judged, the one-bit counter implements the punching number. The output of the Xuan-bit-fan counter is provided to each G first stage. J 17 · If the circuit of the scope of application for item No. 14 in which one of the GCSRs is taken out and the output is in combination with the plurality of mother-in-law's mother-in-laws, the system is 4 mile, and 1 Suspended status bit device, the single-bit leaf number cries ... Early-bit counter value is judged "hold setting, phase separation pause status bit field. When the pause status bit is judged, the digitizer implements counting, 哕 Tan. . ^^ 〇〇. Early Hai-a first stage of the GCSR of the bit counter _GCSR. The pedigree processor is provided to the 18. A scalar processor, including: a common system clock; I-unit clocked by the system clock; and —E „which is timed by the system clock and communicates with the 1_ unit, each of the ... and the E-unit includes: Zao Fan, S6560 -4-200411565 plural registers Stage; and I local clock generator, which receives the common system clock and pause state, the Asian loop should adjust the snap frequency of the plurality of registers, and the I-unit provides a pause for the £ _ unit. Status, and the unit provides a pause status for the I-unit . 19. The scalar processor according to claim 18, wherein the local clock generator includes: a gated control shift register (GCSR) including a plurality of single-bit counters; and a plurality of local clocks The drivers each receive an output from one of the plurality of single-bit counters, and combine the output with the system clock to generate a register-level clock. 20. For a scalar processor in the scope of application for item 19, wherein the plurality of register stages are stages of a register pipeline, and the GCSR includes the single bit counter for each pipeline stage. 21. The scalar processor according to the scope of patent application No. 20, further comprising: a data cache memory, which communicates with the E-unit; a register file, which communicates with the bull unit and the dagger unit And the I-unit includes: a cache memory, an I-queue that receives data from the cache memory, and a pipeline that receives data from the queue; and the dagger unit includes · An E-queue that receives data from the I-pipe, and an E_pipe that receives data from the E-pipeline. 22. According to the scalar processor of the 21st patent application range, wherein each of the ^ unit 86560 200411565 and each of the E-unit and the G cs R and the system clock are combined in the plurality of clock drivers At a corresponding clock driver, each of the plurality of clock drivers gates a corresponding pipeline stage, respectively. 23. 24. If the scalar processor of item 22 of the patent application scope, one of the pause energy bits is provided to a first stage of the GCSR. For example, in the scalar processor with the scope of patent application No. 22, a pause state bit is provided to a single bit counter, and the single bit counter 2 is held. In addition, unless the pause status bit is judged, when the pause status bit is judged, the single-bit counter performs counting, and an output of the single-bit counter is provided to a first stage of the GCSR. 25. If the scalar processor of item 2 and item 2 of the patent application is applied, one of the final outputs of the gcsr is combined with the system date of each of the plurality of clock drivers, and a pause status bit is provided. For a single-bit counter, the 711 counter of the 5H unit remains set unless the paused state bit is judged. 'When the paused state bit is judged, the single-bit count state is a Bech number. An output of the meta-counter is provided to a first stage of the GCSR. 26. An ultrascalar processor, comprising: a common system clock; a unit clocked by a system clock; the unit includes: a cache memory; an instruction fetch unit / branch unit (IFU / BRU), which receives instructions from the I-cache; and ° cycle unit 'which receives instructions from the (IFU / BRU) and forwards them to 86560 200411565 27. 28. 29. The received instructions are used to For execution;-by the system clock. As a result, the E-early element includes a fixed-point unit that receives communications from the dagger using a scratchpad / renaming buffer unit; Aceh-1 a load-storage unit (LSU) mx Danfan's instructions go straight to "general purpose register / rename buffer 'body communication; early ... lean cache phase 1 black early S (FPU), which receives instructions from the r unit and registers" register / Rename the buffer unit to communicate, the loading ⑷ early-advance-step with the floating-point register / rename buffer unit 1 'Money into the health storage unit provides the suspended state for the floating-point unit, 子 early = Then providing a suspended status for the manned storage unit; and ^ a vector multimedia extension unit that receives the instruction and # completes a unit communication in the I-unit; and 'the LSU and each of the FPUs Yes-the local clock generator receives the common system clock and the suspended state, and responds to the suspended state to adjust the clock frequency of the unit register. ~: Ultra-scalar processor with the scope of patent application No. 26, wherein the pause status indicates the activity level of a unit. For example, the ultra-scalar processor in the 27th area of the patent application, wherein the unit is. The E-unit pause status should be used to adjust the capture bandwidth. · A method of controlling the local frequency of a local clock of an integrated circuit chip component 'The method includes: 86560 200411565 monitoring the activity level of a chip component; and adjusting in response to an indication that an activity level of a second component exceeds a critical level A local clock frequency of the first component. 30. The method of claim 29, wherein the local clock is suspended when the activity of the second component rises above the critical level. • If the method of applying for the scope of patent No. 29, wherein when the activity of the second component rises above the critical level, the clock frequency is bisected by 0 3 2 1 顼 — The method of the disciple, wherein when the activity level rises to a second critical level or more, τ is suspended against the clock. 3 3 · If the scope of the patent application is 29, Shi 4 # Tian and Wan Fa, in which when the activity level is below (¾ to below the 5th grade level, the rate is ".". The department clock returns to a normal operating frequency 86560