CN100353288C - Performance control method and device for data processing - Google Patents
Performance control method and device for data processing Download PDFInfo
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- CN100353288C CN100353288C CNB2003801087534A CN200380108753A CN100353288C CN 100353288 C CN100353288 C CN 100353288C CN B2003801087534 A CNB2003801087534 A CN B2003801087534A CN 200380108753 A CN200380108753 A CN 200380108753A CN 100353288 C CN100353288 C CN 100353288C
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- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3237—Power saving characterised by the action undertaken by disabling clock generation or distribution
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
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- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
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- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
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Abstract
Performance control of a processor core 52 is achieved by modulating between a processing mode power supply configuration which the processor core 52 is clocked and a holding mode power supply configuration which the processor core 52 is not clocked. By modulating between these two power supply configuration modes, a target performance level may be achieved and energy consumption whilst in the holding mode can be reduced.
Description
Technical field
The present invention relates to the data handling system field.More particularly, the present invention relates to the control data handling property such as to reduce the field of the energy that consumes by data handling system.
Background technology
Significant consideration is their energy consumption in data handling system.The data handling system that consumes less energy allows longer battery life in mobile device, be easy to colder and operation reliably, and for handling thermal losses etc., require less special designs Consideration.Very wish to reduce the energy consumption of data handling system.
What reduce that the energy consumption of data handling system balances each other with hope is the performance class of wishing to improve them simultaneously, so that handle concentrating of the task of calculating day by day.The processing that this task usually requires in the short time to concentrate is very much operated, and is the long relatively free time that wherein requires low computational effort in described short time back.
In order to solve above-mentioned two factors, the data handling system that known proposition is such, its performance class that can change them provides low-energy-consumption so that provide high calculated performance in some configuration in other configuration.Such as LongRun software of producing by Transmeta or the known system by the SpeedStep system of Intel production, processor can be switched between this different configuration.In order to mate the performance objective of wanting, the so often configuration of high calculated performance configuration has high relatively operating voltage and relative high processor clock frequency.Otherwise low energy consumption configuration has low relatively operating voltage and relative low processor clock frequency.
EP-A-0,632,360 disclose a kind of computer system that can switch according to power selection signal between voltage and frequency rank.The operand power of being wanted can be determined according to the free time iteration.
US-A-5,627,412 disclose a kind of in response to the fluctuating demand of operand power and the power supply that can dynamically switch.
Except that above-mentioned performance and energy management capabilities were provided, another important design characteristics was that the hardware and software design should be reused in more relatively varying environment.If realize writing again computer software such as operating system software for different hardware, perhaps realize revising hardware design significantly for different hardware, this is very disadvantageous so.
Summary of the invention
According to an aspect, the invention provides a kind of equipment that is used for deal with data, described equipment comprises:
Processor can be operated and carry out data processing operation, and described processor can be operated and produce the Properties Control signal, described Properties Control signal indication data processing performance rank that want, described processor; With
The circuit that at least one is other is supported the data processing performance rank of described that want, described processor in response to described Properties Control signal operation; Wherein
When response when being clipped to the variation that change, the Properties Control signal of the second data processing performance rank wanted from the first data processing performance level of wanting, described at least one other circuit can be operated and support data processing at least one intermediate data handling property rank, and described processor during described variation temporarily in described at least one intermediate data handling property level operations.
Present technique provides a kind of system, wherein when the variation of response performance control signal, described other circuit can be operated and support at least one intermediate data handling property rank, and described processor uses it to operating on described at least one intermediate data handling property rank during the described variation.In case higher intermediate performance rank can be used to help better to make progress forward in carrying out the code process paid close attention to, occurent performance change just can be that other increases and raising on performance class with the described higher intermediate performance level that adopts.As selection, between the performance class decrement phase, in case low intermediate performance rank can be used to more promptly reduce energy consumption, this technology just causes described low intermediate performance rank to be used.
Under the situation that performance class improves, can before arriving that augmented performance rank, delete for other requirement of augmented performance level.As an example, when the still relative calculating of service high priority is not concentrated, interruption can trigger attempts to switch to maximum performance class, but in fact only in several processing cycle, just fully carried out interruption code, and fully carried out interruption code before this processing rank rises to maximum very early, this break in service is more promptly enabled in the use of intermediate treatment level.When handling the needing of level, the new data processing performance rank of wanting is set to higher when having eliminated, cancellation switching to maximum performance class.
Although current techniques is applicable to other circuit of control number of different types, it is particularly useful when control clock generator and voltage controller.In this environment, in case higher frequency can with and supply voltage when being enough to support the operation of this raising speed, can switch to this higher clock frequency so as better forward progress pass through the program code paid close attention to, also be like this even this higher clock frequency may be the intermediate frequency of a final goal frequency that approaches to want.
The preferred embodiments of the present invention also provide signal priority, and it can trigger and change to predetermined performance class, and no matter control signal value (for example rank of maximum or reduction).This allows hardware mechanisms to adopt can be so that the mode of rapid response environment be come the direct control feature rank, the battery power signal of described environment such as hardware interrupts, reduction etc.
Observe from another point of view, the invention provides the method for deal with data, described method comprises step:
Carry out data processing operation with processor, described processor can be operated and produce the Properties Control signal, the data processing performance rank of described that want, the described processor of described Properties Control signal indication; And
In response to described Properties Control signal, operate one or more other circuit so that support the data processing performance rank of described that want, described processor; Wherein
When response when being clipped to the variation that change, the Properties Control signal of the second data processing performance rank wanted from the first data processing performance level of wanting, described one or more other circuit can be operated and support data processing at least one intermediate data handling property rank, and described processor during described variation temporarily in described at least one intermediate data handling property level operations.
Description of drawings
To embodiments of the invention be described with reference to the accompanying drawings only with the form of giving an example now, wherein:
Fig. 1 schematically for example understands the part of data handling system, comprises performance controller, clock generator and voltage controller;
Fig. 2 is a process flow diagram of schematically for example understanding operating system computer program operation in the performance class process that setting is wanted;
Fig. 3 schematically for example understands the exemplary map between performance class of wanting and control signal value;
Fig. 4 is a process flow diagram of schematically for example understanding the control voltage controller;
Fig. 5 is a process flow diagram of schematically for example understanding the control clock generator;
Fig. 6 is the figure that schematically for example understands another example of the data handling system of utilizing current techniques;
Fig. 7 is the figure that schematically for example understands at the further example of wanting to shine upon between performance class and the control signal value;
Fig. 8 understands that for example supply voltage is in the modulation that keeps between pattern rank and the tupe rank;
Fig. 9 has schematically illustrated the circuit in conjunction with Fig. 8 technology;
Figure 10 understands for example that schematically the voltage that uses modulation comes the process flow diagram of control performance;
Figure 11 is the figure that schematically illustrates another data handling system of using Fig. 8 technology; With
Figure 12 illustrates the figure that is used for such as each control signal of the embodiment of Fig. 8 to 11.
Embodiment
Fig. 1 for example understands the part of data handling system, comprises performance controller 2, clock generator 4 and voltage controller 6.Typically, circuit in Fig. 1 forms the part of big integrated circuit, and described integrated circuit comprises processor, such as the arm processor of being produced by Britain Camb Advanced Risc Machines Ltd., and other circuit component, also can be used as the part of system design in the chip.For simplicity, from Fig. 1, omitted circuit component except that performance controller 2, clock generator 4 and voltage controller 6.Described performance controller 2 receptivity level request signal/values, this signal/value produces by going up under the control of computer program at programmed instruction of carrying out at processor (not illustrating), and described computer program is such as operational computations machine program.For this purpose, can be written in the data processing performance level request of being wanted in the memory address space on the mailbox memory, also can be written to control register (such as the control register in the configuration coprocessor the CP5 ARM architecture for example), perhaps adopt the alternate manner storage.Performance controller 2 is the bonding properties monitor also, and described performance monitor can be one or more performance counters, its counting real time, clock signal, the work of execution or the process of other performance-monitoring parameter.When performance controller 2 received the data processing performance level request of the variation on the performance class of representing to want, it was used for to clock generator 4 issues to the request of new target clock speed and to the request of voltage controller 6 issues to new target voltage so.Should be understood that, in case when programmed instruction was written to suitable position with its data processing performance rank of wanting, how it just implemented described other control of data processing performance level of wanting to control and give hardware (performance controller 2).Described performance controller 2 is mapped to the data processing performance request of being wanted to clock generator 4 and voltage controller 6 appropriate control signals values (described performance controller 2 comprises mapping circuit).The data processing performance request signal can be Gray's (Gray) coded signal value or simple uniform enconding value.Described mapping can be the thermometer coding control signal value, because so to may being to provide repellence preferably at sample error when sampling between the asynchronous clock zone.In addition, this provides a kind of fail safe situation, and sample error is easy to generate minimum stable synchronization value for use whereby.
The described voltage controller 6 of control signal order that is sent to voltage controller 6 is adopted new voltage output level.Can be by in guiding or be programmed in At All Other Times that configuration parameter registers 8 disposes the voltage output level of being supported in the voltage controller 6.Voltage controller 6 cost finite time amounts rise or drop to new voltage level.In certain embodiments, when voltage controller 6 is changing to its new voltage level, described voltage controller 6 can pass one or more middle ranks, rank often can support to hang up an intermediate performance rank (in other embodiment that describes after a while, can use single operating frequency clock signal and stop clock) of the last performance class that arrives in the middle of described.Voltage controller 6 produces the current operation signal of its current voltage level that can support of expression and these signals is transferred back to performance controller 2, these signals can promptly be used to trigger the use to the suitable and available clock frequency that is associated according to as getting off action herein.
Fig. 2 schematically for example understands the processing operation according to an example of described technology, and it can be carried out by the operating system computer program of carrying out on processor.In step 16, the relevant treatment thread waits, up to determining to need to change performance class.This needs and can be shown by changes in external parameters, such as by user's pressing key, maybe can use such as previously discussed those performance monitoring counters to come in internal trigger by the operational performance that monitors described system.When detecting this performance level change of wanting, handle proceeding to step 18, said software is carried out the unit of write store mapping, and described unit is exclusively used in the request rank of the data processing performance that storage wants.The action of computer program code will detect to the requirement that changes performance class and this and require write storage unit.Not needing provides Control and Feedback to monitor: in fact the performance change of being wanted takes place or how it takes place.Between the action that computer program writes and the underlying hardware mechanism of moving, exist abstract according to request.This makes and uses constant basically computer program to be convenient to carry out in various environment, can or can not provide any performance management mechanism in those environment.
Fig. 3 schematically for example understands the exemplary map between the thermometer coding control signal value of 6 data processing performance request signals of wanting (it is Gray code alternatively) and correspondence.In this case, although there are 33 possible performance classes, but only there are 9 possible control signal value.Correspondingly, between performance class of being wanted and control signal value, there is quantification.This quantification is arranged to make described control signal value corresponding in the performance class scope and can be mapped to the maximum performance class of this control signal value.In the performance signals of wanting be intended to have monotone increasing in the performance class of appointment.Thereby the performance class of being wanted can be the binary fraction that is illustrated in attainable maximum performance class number percent in the system.This be convenient and flexibly, the approach of abstract described performance class request, be used for abstract described performance class request mode and be: described performance class request can be in multiple different hardware environment and is controlled by programmed instruction for multiple different processing order.
Fig. 4 schematically for example understands the control of voltage controller 6 in having the embodiment of a plurality of voltage levels, the active process pattern that described voltage level is moving corresponding to clock wherein.In step 20, described voltage controller is waited for and is received new control signal.When receiving new control signal, handle proceeding to step 22, start the change of the voltage level that is provided at this.This change can be to improve or reduce.Voltage controller 6 has the limited conversion ratio (slew rate) of the output that can change it.Step 24 is monitoring, up to till arriving next supported voltage level during the total variation of generation.When arriving this next rank, setting up procedure 26 and produce new current voltage output signal so is so that offer performance controller 2 and can support described new voltage level to show described voltage controller 6 to returning.This can be the intermediate voltage level that approaches the final goal voltage level, is final goal voltage level itself at described conversion (slew) end perhaps.Described performance controller 2 can move according to the current voltage output signal that feeds back to it, so that control clock generator and possible performance monitoring circuit.Step 28 determines whether to reach final voltage.If also do not reach described final voltage, handle the conversion of getting back to step 24 and voltage output so and continue towards its final goal.In the system that only supports two voltage levels, described system will reach final voltage level not having can wait for simply under the situation of intermediate voltage level.
Should be understood that Fig. 4 supposes that control signal does not change.In fact, described control signal can change before arriving final goal voltage.To by instructing the needs of determined performance class Iterim Change not existed at the operating system internal program, such as interrupt having obtained service or contingency mode signal be changed to invalid.In this environment, interrupt control, and handle and get back to step 20 in Fig. 4 illustrated, start action there based on newly-established control signal value.Should be understood that, by the control that software carried out is the part open loop at least, this is because its performance class of being wanted has only been stipulated in this control on particular point in time, and and do not require the performance that in fact supervision sends, or in fact when send described performance class.
As mentioned, can offer performance controller 2 to emergency signal (signal priority or hardware override signal) so that any software control of heavily loaded performance class and temporarily described performance class is brought up to maximum level.The software control of bypass performance class can be so that switch to maximum performance class more rapidly and directly, such as carrying out described switching in response to specific high priority hardware interrupt under pure hardware controls.More than this " meeting an urgent need " signal can be provided, and for example " low battery is emergent " signal can be forced to performance the rank of known reduction.
Fig. 5 schematically for example understands the control of clock generator 4.In step 30, described clock generator is waited for and is received new control signal.When receiving new control signal, handle and proceed to step 32, determining whether there needs to give any additional phase lock loop circuit 12 to power up so that serve the final new clock frequency that requires.If require this additional phase lock loop circuit 12, handle so and proceed to step 34, start described additional phase lock loop circuit 12 there.As selection, handle proceeding directly to step 36.
In step 36, whether described clock generator determines to approach the new clock signal of the performance class of asking available.This is convenient to adopt the intermediate performance rank that is used to hang up final goal performance class availability.When the clock frequency of this centre of identification, handle so and proceed to step 38.Whether the definite current operation signal value from voltage controller 6 feedbacks of step 38 shows is producing the voltage that can support new clock signal value.But when this voltage time spent, handle proceeding to step 40 so, adopted by the cpu clock generator there and produce new clock signal value with as signal cpuclk, described signal cpuclk is provided for processor core.Then, step 42 oppositely gives performance controller 2 outputs new present clock value, and performance monitoring hardware described herein can be abideed by described new present clock value and be moved so that estimate forward progress by code.Whether step 44 is determined: to the switching of new clock frequency, to the switching that is produced, wanted the specified final clock frequency of data processing performance request by programmed instruction.If do not reach the final goal clock frequency, handle so and get back to step 36, otherwise control stops (in fact getting back to step 30).
As for Fig. 4, Fig. 5 also supposes and does not change by the specified data processing performance rank of wanting of programmed instruction.If the described data processing performance rank of wanting changes, will produce new mapping control signal value so, described control signal value is interrupted in the processing of Fig. 5 illustrated and is made described processing turn back to step 30, so according to new control signal value action.
Clock frequency value in the middle of adopting when changing between initial and final clock frequency value for the particular state of concern circuit, allows the best code that passes through to make progress forward and be achieved.The final goal clock frequency become available before, described circuit is always in initial clock frequency operation, but opposite, but when becoming the time spent in each clock frequency of performance transition period, described circuit rises or descends and passes the clock frequency sequence.Can be adopting new clock frequency to think to control by the logical and (AND) of following signal, described signal comprises: be used to show the current frequency of described frequency ratio more near the signal of target frequency, be used to show to come the signal and being used to of that frequency availability in self-clock source to show that voltage controller can generate the signal of the power signal with the operation that is enough to support this new clock frequency.As selection, in only having two performance level other embodiment of other (maximum/free time), described system can wait for final voltage before switching.
Fig. 6 is the figure that schematically illustrates the data handling system of utilizing current techniques.Has identical Reference numeral with components identical in Fig. 1 illustrated.Fig. 6 for example understands the processor 46 of execution of program instructions in addition, and described programmed instruction can remain in tightly coupled accumulator system 48 or other storer.The different voltage ranges of being paid close attention to make each interface in illustrational circuit provide level shifter (shifter) necessary.
Fig. 7 for example understands another exemplary map between data processing performance request rank of wanting and thermometer coding control signal value.In this case, use 32 thermometer coding control signal values, produce the more possibility of the Properties Control of fineness.Other circuit in response to these 32 control signal value may be merely able to provide the more control of coarseness, therefore in fact quantizes the control signal value of being paid close attention in inside.The thermometer coding control signal value provides special mode easily to make up from the control signal value of homology not, such as control signal value from the different processor on the multicomputer system, can suitably select overall level of performance whereby, it may be only controllable on the basis of chip range.Can determine maximum control signal value with the logical OR (OR) of control signal value, can determine minimum control signal value, and can determine equivalence value with the XOR XOR of control signal value with the logical and (AND) of control signal value.Max function can be used for determining the clock frequency of largest request, and minimum value function can be used to show minimum supported voltage, and equivalent function can be used to determine the coupling between the different elements demand.
Fig. 8 for example understands another Properties Control technology.In this example, the supply voltage to treatment circuit is shown keeping modulating between mode voltage level HM and the tupe voltage level PM (in this example for pulse-length modulation).When in the maintenance pattern, treatment circuit is not supplied to clock and does not make progress code by carrying out forward.When in tupe, treatment circuit is supplied to clock with its complete bit rate clock signal and makes progress code by carrying out forward.The for example clear wherein treatment circuit of the first of Fig. 8 is in tupe and has taken for 50% time, and can think correspondingly that in fact this treatment circuit is just moving with half clock frequency of provided clock frequency.Power configuration-be in this case supply main line (rail) power supply (but can the main consuming body biasing (bodybiasing) or other technology) is such, makes that the energy consumption of described treatment circuit is lowered under the maintenance pattern.Thereby, described treatment circuit consumption less operating energy as shown, reason be described treatment circuit under the maintenance pattern of low energy consumption with enduringly under tupe time loss compare the time that has only consumed half.
At the center section of Fig. 8, used the duty cycle ratio of 33% different modulating, thereby effectively clock frequency is 1/3 of a maximum rate.In the decline of Fig. 8, system's 100% the operating of holding time under tupe as can be seen, thus operate effectively in the clock frequency speed that is completely fixed.
Fig. 9 schematically for example understands data handling system 50, comprises processor core 52, tightly coupled storer 54 and DSP circuit 56, and all these are by bus 58 links.Processor core 52 is arranged by the above-mentioned Properties Control technology of Fig. 8, and switches between tupe and maintenance pattern.Voltage and clock controller 60 receive the target performance level request (may be produced by operating system or other code carried out) of from processor core 52 on processor core 52, and use this to ask to produce pulse width modulating signal PWM (Pulse Widthmodulated sigal), described PWM is selected to provide suitable dutycycle so that the performance class that realizes wanting in fixing clock frequency.Or door 62 carries out or operates this pwm signal and the busy signal that is produced by processor core 52, look-at-me irq with by the real-time clock request signal that real time clock circuit 64 produces.When pwm signal can phase shaft system when placing the maintenance pattern, any one in busy signal, look-at-me irq and the real-time clock request signal can heavily loaded pwm signal and forced system to enter tupe.
Or door 62 output offer clock generator 66 and voltage generator 68.When or door 62 output when showing the requirement tupe, so described clock generator 66 produces its clock signal clk, in case the following ready signal that clock generator circuit 66 has received from voltage generator 68 just offers processor core 52 to described clock signal clk, described ready signal shows that voltage generator 68 successfully changes into tupe configuration to the power configuration of processor core 52, and this is enough to the stable timing of supporting processor circuit 52 now.When can not be safely when tupe switches to the maintenance pattern processor core 52, for example when existence suspended to other circuit (such as tight coupling storer 54 or DSP circuit 56) to the data transmission via bus 58, processor core 52 produced busy signals.Processor core 52 uses and sends active high signal to the other circuit component such as tightly coupled storer 54 and DSP circuit 56, makes that clamp circuit 70 can be these circuit limitations at ground level when processor core 52 being placed the maintenance pattern or cutting off the power supply fully.
Figure 10 schematically for example understands the process flow diagram that can how be realized Properties Control by voltage and clock controller 60.In step 72, show the new performance class of wanting to voltage and clock controller 60 by processor core 52.In step 74, this performance class of wanting is converted to suitable pulse width modulation duty cycle according to searching in mapping table, firmware hardwired logic or the two are average.Should be understood that this example uses width modulation, but other modulating mode also is possible, such as scramble sequence PWM pattern or other pattern.
Figure 11 for example understands the another circuit that uses Fig. 8 technology.This circuit is similar to the circuit of Fig. 6, notices that at least some level shift circuits are replaced by clamp circuit, and uses the power range that switches, rather than the dynamic voltage scaling scope.
Figure 12 for example understands the PWMDVS signal that is produced by voltage and clock controller 60, is used for the performance class that order is wanted.IEC REQ signal indicating continuous signal is sending to intelligent energy controller, so that trigger dormancy or wake actions when entering or leaving the maintenance pattern in system.IEC PANIC signal is the signal priority that is used for heavily loaded PWMDVS signal.The CPUACTIVE signal is to show to stop to provide clock also unsafe busy signal to CPU.
VDDREQ is or door 62 output.VDD CPU is from the signal of voltage generator 68 outputs and shows limited conversion ratio.VREADY is the signal from voltage generator 68, shows that to clock generator can carry out clock switches.Should be noted that not switch to tupe, still can switch to the maintenance pattern very soon up to finishing described conversion.
Claims (6)
1. equipment that is used for deal with data, described equipment comprises:
Processor (46) can be operated and carry out data processing operation, and described processor can be operated and produce the Properties Control signal, the data processing performance grade of the described processor that described Properties Control signal indication is wanted; With
At least one other circuit (4,6) is supported the data processing performance grade of the described described processor of wanting in response to described Properties Control signal operation; Wherein
When response when being clipped to the variation of the Properties Control signal that the second data processing performance rank wanted changes from the first data processing performance level of wanting, described at least one other circuit can be operated at least one intermediate data handling property grade and support data processing, and described processor is temporarily operated (40) in described at least one intermediate data handling property grade during described variation.
2. equipment as claimed in claim 1, wherein said at least one other circuit also comprises voltage controller (6), can operate and come at a plurality of different voltage levels (V[i]) for described processor produces power signal,
Wherein said at least one other circuit comprises clock generator (4), can operate producing the clock signal with optional clock frequency,
Wherein in response to the raising of the data processing performance grade of wanting, clock signal frequency in the middle of described clock generator is brought up to clock signal frequency, at this moment, described voltage controller producing have be enough to support described in the middle of the power signal of voltage level of clock signal frequency.
3. equipment as claimed in claim 1, wherein one or more signal priorities are used for triggering described other circuit and change, and support predetermined data processing performance rank so that be independent of described Properties Control signal.
4. the method for a deal with data, described method comprises the steps:
Carry out data processing operation with processor, described processor can be operated and produce the Properties Control signal, described Properties Control signal indication data processing performance rank that want, described processor; And
In response to described Properties Control signal, operate one or more other circuit so that support the data processing performance rank of described that want, described processor;
Wherein when response when being clipped to the variation that change, the Properties Control signal of the second data processing performance rank wanted from the first data processing performance level of wanting, described one or more other circuit can be operated and support data processing at least one intermediate data handling property rank, and described processor during described variation temporarily in described at least one intermediate data handling property level operations.
5. method as claimed in claim 4,
Wherein said one or more other circuit comprises voltage controller, and can operate at a plurality of different voltage levels is that described processor produces power signal,
Wherein said one or more other circuit comprises clock generator, can operate producing the clock signal with optional clock frequency,
Wherein in response to other raising of data processing performance level of wanting, clock signal frequency in the middle of described clock generator is brought up to clock signal frequency, at this moment, described voltage controller producing have be enough to support described in the middle of the power signal of voltage level of clock signal frequency.
6. method as claimed in claim 4, wherein one or more signal priorities are used for triggering described other circuit and change, and support predetermined data processing performance rank so that be independent of described Properties Control signal.
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB0300712.7 | 2003-01-13 | ||
| GB0300713.5 | 2003-01-13 | ||
| GB0300710A GB2397140A (en) | 2003-01-13 | 2003-01-13 | Data processing performance control |
| GB0300710.1 | 2003-01-13 | ||
| GB0301852.0 | 2003-01-27 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1739081A CN1739081A (en) | 2006-02-22 |
| CN100353288C true CN100353288C (en) | 2007-12-05 |
Family
ID=9951046
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2003801087534A Expired - Lifetime CN100353288C (en) | 2003-01-13 | 2003-11-10 | Performance control method and device for data processing |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN100353288C (en) |
| GB (1) | GB2397140A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112306558A (en) * | 2019-08-01 | 2021-02-02 | 杭州中天微系统有限公司 | Processing unit, processor, processing system, electronic device, and processing method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0632360A1 (en) * | 1993-06-29 | 1995-01-04 | Xerox Corporation | Reducing computer power consumption by dynamic voltage and frequency variation |
| US5627412A (en) * | 1994-11-07 | 1997-05-06 | Norand Corporation | Dynamically switchable power supply |
| CN1306641A (en) * | 1999-03-31 | 2001-08-01 | 皇家菲利浦电子有限公司 | Parallel data processing |
-
2003
- 2003-01-13 GB GB0300710A patent/GB2397140A/en not_active Withdrawn
- 2003-11-10 CN CNB2003801087534A patent/CN100353288C/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0632360A1 (en) * | 1993-06-29 | 1995-01-04 | Xerox Corporation | Reducing computer power consumption by dynamic voltage and frequency variation |
| US5627412A (en) * | 1994-11-07 | 1997-05-06 | Norand Corporation | Dynamically switchable power supply |
| CN1306641A (en) * | 1999-03-31 | 2001-08-01 | 皇家菲利浦电子有限公司 | Parallel data processing |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2397140A (en) | 2004-07-14 |
| CN1739081A (en) | 2006-02-22 |
| GB0300710D0 (en) | 2003-02-12 |
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