TW200410402A - Manufacturing method of flash memory - Google Patents

Abstract

A manufacturing method of flash memory is provided. First, a substrate with a first gate structure and a second gate structure is provided, and the first gate structure and the second gate structure is consisted of a dielectric layer, a first conductive layer and a cap layer respectively. A tunneling oxide layer is formed on the substrate and a first spacer is formed on the sidewall of first conductive layer. A second conductive layer is formed on the source side of the first gate structure and the second gate structure and a source region is formed in the substrate. Then an inter gate dielectric layer is formed on the second conductive layer and a insulation layer is formed on the substrate surface of source region. A third conductive layer is formed between the first gate structure and the second gate structure, and a drain region is formed in the substrate.

Description

200410402 V. Description of the invention (1) The present invention relates to a method for manufacturing a semiconductor seed flash memory. η and in particular

The previous #I flash memory device has a user j, = division, and other operations that can perform data multiple times, and the stored data will not = after power off: Volatile memory device. 'A kind of atypical flash memory device for wood is doped polycrystalline, (FlOating Gate) and control gate (c0ntr〇i.) As a sub-position π gate and control gate The poles are separated by a dielectric layer, and the bottom is floated to be separated by a tunnel oxide layer. When performing fast write / erase data operations on the fast and the second, System _ Gate and source / drain regions are biased so that electrons are injected into the s; the electrons are pulled out of the floating gate. The forma of the flash memory is read

A working voltage is applied to the Hi control gate. At this time, the charged state of the floating gate will affect the opening / closing of its lower channel (Channel), and this on / off is the basis for judging the data value "0" or Γ i " . <When the flash memory is erasing data, the relative potential of the substrate, the (source) region, or the control gate is increased, and the tunneling effect is used to pass the floating gate through the tunneling tunnel. Oxidation layer (Tunneling Oxide) and 4 rows to the substrate or drain (source) side (ie, Substrate Erase or Drain (Source) Side Erase), or through the dielectric layer to the control gate. However, 'when erasing the data in the flash memory, it is easy to make the floating gate because the amount of electrons discharged from the pole is not easy to control because it is difficult to control from the floating m 10220twf.ptd page 7 200410402. The pole has a positive charge, which is called excessive erasure (0ver_Erase). If the erasing phenomenon is too serious, even the ^ track below the floating gate = the gate will continue to be in a conducting state when no working voltage is applied, and ^: misjudgment. Therefore, in order to solve the problem of excessive erasing of components, a flash memory with a high density of three levels of gates is currently being defined. ^ Please refer to FIGS. 1A to 1 (: the edges of the drawings are shown as Xi; a cross-sectional view of a flash memory manufacturing process. First, refer to FIG. 1A, provide a substrate 1 and form an insulating layer on the substrate 100 ( (Not shown) and a layer of "body acoustic diagram", the conductive layer and the insulating layer are patterned to form a dielectric layer 102 and a gate electrode 104. Then, a tunneling oxide layer is formed on the surface of the substrate 100 and an inter-gate dielectric layer is formed on the selection gate 104. Referring to FIG. 1B, a conductive layer 110 made of doped polycrystalline silicon is formed on the substrate 100, and then the conductive layer 110 is patterned so as to be distributed in a strip shape, and a part of the conductive layer 110 is located above the selection gate 104. Next, another inter-gate dielectric layer 丨 2 is formed on the conductor layer u 〇, and then another conductor layer 114 made of doped polycrystalline silicon is formed on the inter-gate dielectric layer 2. Please refer to FIG. 1C. After that, the patterned conductor layer 4, the inter-gate dielectric layer 112, the conductor layer 110, and the tunneling oxide layer 106 are formed to form the control gate 114a, the inter-gate dielectric layer n2a, Floating gate 11 &amp; and tunneling oxide layer 106a. Among them, the selection gate 108, the floating gate 110 and the control gate 11 4a constitute the gate structure of the flash memory. Then, source regions 116 and j: and a pole region 118 are formed in the substrate 100 on both sides of the gate structure. In the above flash memory manufacturing method, a control gate is formed

200410402 V. Description of the invention (3) In the step of 11 4 a, due to the problem of the alignment of the floating gates, the floating 120a and 120b cannot correctly define the length of the misalignment when 11 oa occurs. It is not equal, so the problem of asymmetry in the programming of the channel memory cells of the two memory cells in the source region arises. One manufacturing method of the present invention uses the self-aligned channel region length of the $ memory cells. A stylized asymmetry problem, and another object of the present invention is to mention the use of a self-aligned process shape but can avoid the channel 2 of the two memory cells plus the 5 rate of the floating gate and the control gate. And improve component performance. The invention proposes a flash memory: column step: providing a layer formed by a first gate structure, a second gate structure, a second conductor layer, and a cap layer, and a first conductor layer and a free pole structure. A second conductor layer is formed with the second gate electrode. Then, the electrode 110a has an optical channel for the selected gate, and the channel area below the gate 110a is set. That is, in the patterned floating gate, the channel area 120a and the channel area 1201) operate this flash memory because the length of the common area is inconsistent, so it will cause the 5th memory cell to stay idle. Slow down. The purpose is to provide a flash memory manufacturing process to form floating gates, which can avoid the problems caused, and can prevent the memory cells from having high memory cell performance. For the manufacture of flash memory with "L" shaped floating gate, it does not have the problem of inconsistent length. It can also sandwich the area to improve the manufacturing method of the gate coupling memory. This method includes a The gate structure and the two gate structures of the second gate structure are each composed of a dielectric. Next, after forming a first gap wall on a sidewall formed on the substrate, a side of the source side of the source region is formed in the structure ′ to form a source region in the substrate, and

200410402 V. Description of the invention (4) Insulation layer. Said: Cheng:] The dielectric layer is formed on the substrate surface of the source region and nitrided hard / oxygen: / closed electrode; the material of the interlayer dielectric layer is oxygen cut / body material when forming the second conductor layer, The patterned photoresist layer on the substrate is sequentially formed into an area of m followed by the two source regions to remove the conductive material layer covered by the photoresist layer. After that, the material exhibition, photoresist layer, and an anisotropic etching process are performed to remove the lead :::: to guide the layer. / Wide channel area has the same two layers) 'can make adjacent memory cells are two records of the shared source area: body time' because of the asymmetry of the i memory cell stylization, heart = record The flash, ^ system provides the first gate structure that has been formed: Γ = the first gate structure and the second gate structure are each composed of a dielectric layer and a ^ second conducting layer :: wall: 乂 成: An oxide layer, a layer of conductors, a two-layer solidification, and a nine-resistance layer are overlaid to form a source region of 10220twf.ptd Page 10 200410402 V. Description of the invention (5) A region. Then, the first patterned photoresist layer is removed after removing the material layer and the: 2 body material layer that are not covered by the first-conductor material exhibition layer. A part of the material layer and the first-conductor material layer are removed by the adhesive etching process: After the wall and the second conductor layer, the third layer is removed to form a third layer between the base surface of the source region and the third-layer structure. Conductor layer and L: -Guide 2: Sun ::! The body layer is used as the selection gate of the flash memory; the first is the “control gate of the memory”: = for silicon nitride / silicon oxide. <Li * Feng lice silicon / body 2 when it becomes the second conductive layer ' A conductive layer is sequentially formed on the substrate. Then, 'remove the unpatterned photoresist layer ;:' ”The shape of the conductive font layer is then removed after the second spacer is the same length at 2 in :: ϊ Adjacent memory The length of the channel area of the two memory cells in the channel region of the cell is equal to :::: Because of the problem of sharing the source electrode, it can be used :::; Glyph, λ degree increases and floats_ l〇220twf.ptd Page 11 200410402 V. Description of the invention (6) The pinch between the 2 pole (Λ 21 conductor layer) and the control pole (third conductor layer) Area, and the edge gate coupling rate, and improve the component performance. = To make the above and other objects, features, and advantages of the present invention more obvious and easy to implement, a preferred embodiment is given below, and the detailed description is as follows: UI ^ Figure 2A to 2F The drawing is a cross-sectional flow chart of manufacturing a split gate flash memory according to a preferred embodiment of the present invention. a First, referring to FIG. 2A, a substrate 200 is provided. The substrate 200 is, for example, a P-type silicon substrate, and a deep N-type well area 202 has been formed in the substrate 200. A P-type is located on the deep N-well area 202. Well area 204. Next, a dielectric layer 206, a conductor layer 208, and a cap layer 210 are sequentially formed on the substrate 200. The method for forming the dielectric layer 206 is, for example, a thermal oxidation method, and its thickness is, for example, about g0 to 100 angstroms. The material of the conductive layer 208 is, for example, doped polycrystalline silicon. The method for forming the conductive layer 208 is, for example, forming an undoped polycrystalline silicon layer by chemical vapor deposition, and then performing an ion implantation step to form it. The material of the capping layer 2 10 is, for example, nitride stone, and its thickness is, for example, about 1000 angstroms to 2000 angstroms. The method for forming the capping layer 2 10 is, for example, a low-pressure chemical vapor deposition method. Of course, the material of the top cover layer 210 can also be formed by using chemical vapor deposition method using tetra-ethyl-o-mono-silicic acid (Tetra Ethyl Ortho Silicate (TEOS) / ozone (〇3)) as a reaction gas source. Shi Xi et al. Next, please refer to FIG. 2B, patterning the top cap 210, the conductive layer 208, and the dielectric layer 206 to form the top cap layer 210a, the conductive layer 208a, and the dielectric layer 20 6a. Among them, the capping layer 210a, the conductive layer 208a, and the dielectric layer 206a

10220twf.ptd Page 12 200410402 V. Outline of Invention &quot; --- Open-Pole Structure 'and the conductor layer 208a is used as the gate of choice for flash memory. Then, a tunneling oxide layer 212 is formed on the substrate 200 and a spacer 2i4 is formed on the side wall of the conductor core. The method for forming the through oxide layer 212 and the spacer 214 is, for example, a thermal oxidation method. Next, referring to FIG. 2C, Yan Qing formed another = 6 on the substrate 200. The material of the conductor layer 216 is, for example, doped polycrystalline stone. The method for forming the conductor: 216 is, for example, chemical vapor deposition After forming an undoped polycrystalline silicon layer, an ion implantation step is performed on the conductor layer 216 to form a layer of photochemical #yangfeng 91β 9 back to tea photoresist layer 21 8, this patterned photoresist layer 2 ″ 8 overlay疋 = area of the source region. Then, remove the unpatterned conductive layer 2 1 8 overlying the resist layer 2 1 8. Methods for removing a part of the conductor layer 2] 6 include a wet silver engraving method or a dry etch-off method. — Next, referring to Figure 2D, after removing the patterned photoresist layer 218, a non-isotropic etching step is performed, and the side walls of the top cover layer 21a and the conductor layer 20 center: A conductor layer 2 6a (spacer wall) is formed thereon. The conductive layer 2 is used as a floating gate of the flash memory. Then, another layer ® photoresist layer m 'is formed on the substrate 200. The patterned photoresist layer 220 exposes a region where a source is to be formed. Next, dopant implantation is performed using the patterned photoresist layer 22 as a mask. A process 222 'has implanted dopants between two adjacent conductor layers 2 "a to form a pole region 224. The implanted dopants It includes an N-type dopant, which is, for example, a phosphorus ion or an arsenic ion. Next, referring to FIG. 2E, after removing the patterned photoresist layer 220, an inter-gate dielectric layer 226 is formed on the conductor layer 216a, and An insulating layer 228 is formed on the surface of the source region 224. The material of the dielectric layer 226 is, for example, nitrogen.

Page 13 200410402 V. Description of the invention (8) Siliconized silicon oxide / silicon oxide layer, the inter-dielectric layer 226 is formed; method = Angstrom / 6. Ah or so. Gate silicon J, and then use chemical vapor deposition; emulsification-layer oxidation. The material of the insulating layer 228 is, for example, oxygen, and the method of forming another layer is, for example, thermal oxidation. Bean lice silicon, the insulating layer 228 is 226 in the same step. The insulating layer 228 and the inter-gate dielectric layer have a conductive layer 230, which is the conductor 23. Of course, wheat is formed on the substrate 200. The material of the conductive layer 230 is, for example, a doped polycrystalline layer-doped polycrystalline layer? Two of them. Then, a step / sub-implantation step is formed on the conductor layer 230 to form a patterned photoresist layer 232 which is distributed in a stripe shape; ‘this = controllable closed electrode. Then, removing the unpatterned photoresist layer 2 === Formula: 2: The method of removing r to remove part of the conductor layer 230 includes a wet silver engraving method or a dry etching method. Hydrocarbon-patterned conductor layer 23-gates. 1 π 芍 Control of anaerobic flash memory / Next, please refer to Figure 2F. After removing the patterned photoresist layer 232, proceed to an ion implantation step, and the substrate on the side of the conductive layer 208a is light. Doped region 234. Then, a gap wall $ = is formed on the sidewall of the conductive layer 230, and a gate gap wall 238 is formed on the side of the top cover layer 210a, the conductive layer 208a, and the dielectric layer 206a. The method for forming the partition wall 236 and the partition wall 238 is, for example, 1 after forming an insulating layer (not shown) on the substrate 200, and then removing a part of the insulating layer by anisotropic engraving to form it. After that, another ion implantation step is performed, and a heavily doped region 24 is formed on the substrate 200 on the side of the spacer 238. Among them, the lightly doped region 2 3 4 and the densely doped region 2 4 0 constitute the shortest part of the flash memory. 10220twf.ptd Page 14 200410402 V. Description of the invention (9) Area 2 4 2. The subsequent completion of the flash memory manufacturing process is well known to those skilled in the art and will not be repeated here. In the above embodiment, the present invention uses a self-aligning method to form a floating gate electrode (conductor layer 2 1 6 a) 'so that the channel regions of adjacent memory cells have the same length. In the case of memory, since the channel region length of two memory cells sharing the ^ polar region is the same, the problem of & memory ^ stylized asymmetry can be avoided, and the reliability of the memory can be improved. FIG. 3A to FIG. 3D are cross-sectional flowcharts of the manufacture of a split-gate flash memory according to an embodiment of the present invention. 1 77 First, referring to FIG. 3A, a substrate 300 is provided. The substrate 300 is, for example, a P-type silicon substrate. In this substrate 300, a deep N-type well area 300 has been formed. P-well area 304 on 302. Then, according to the process from the ㈣ diagram to the 2β diagram, a dielectric layer 306, a conductor layer, a capping layer 310, a tunneling oxide layer 312, and a spacer 314 are sequentially formed on the substrate 300. Among them, the top 3U body layer 308 and the dielectric layer 306 form a gate structure, and the conductor ΓΓΛ / memory body selects the gate. Next, a multi-layer layer 316 is formed on the substrate 300, and the material of the conductive layer 216 is, for example, a doped product: the formation method is, for example, chemical vapor deposition. Miao De said that after the undoped crystalline silicon layer, an ion implantation step is performed to form it. Then, an acoustic material 厗 qi7 is formed on the conductor layer 316. The material of the layer 317 is, for example, the county-level gas-towel layer 317.枓 枓 枓 化 Λ Λ Λ 日 日 日 分 分 分 夕 夕 夕 夕 夕. The method of forming this material layer 31 7 is, for example, sand removal. &Gt; Tian Ran The material of this material layer 31 7 is not limited to nitrogen = select; :::: yes = thin, with different cover side ..., after A layer of patterned light 200410402 is formed on the material layer 317. 5. Description of the invention (10) = layer 32. This patterned photoresist layer 318 covers the material sound Vl 7 'of the region where the source region is to be formed. The method of moving the conductive layer 316 and the two-part two-layer conductive layer 316 and the material layer 317 covered by the \ patterned photoresist layer 318 includes a lithography method or a dry-rewind method. Line-: ΐ 向 Directional diagram: After removing the patterned photoresist layer 318, proceed to enlighten ... Λ 3 gap wall) and the gap wall 317a. It is the floating gate of flash memory. Then, a layer is opened on the substrate 3: that is, the photoresist layer 320 is patterned, and the patterned photoresist n forms a region of another layer. Next, the source line _ Λ 2 source region 324 is scheduled to be formed by the map ## @ θ 20. The implanted dopants include: dopants are formed to form arsenic ions. For soil repair, it is, for example, phosphorus ions. Then, referring to FIG. 3C, remove R, and remove the partition wall 31 7a. After J == layer 32 of the partition wall 31 7a, the method is shifted. Next, an insulating layer 328 is formed on the surface of the conductor layer 316a if the wet-etched electrode region 324 is formed. The second layer is a silicon oxide / silicon nitride / oxidation source. # 二 b &quot; 电 层 326 An example of the material is Angstrom. The tank formation is 70 Angstroms: 7 ◦ Angstroms. After forming a layer of silicon oxide, the wind is used.> First, the thermal oxidation method is applied to the Shixi layer and another layer of oxidized stone. Insulation two: Phase 2 and special product method sequentially form nitride nitride, and the method for forming insulating layer 328 is, for example, oxidizing 328 and inter-gate dielectric layer 326 series ... emulsification method. Among them, the insulating layer is formed in one step. 10220twf.ptd 200410402 V. Description of the invention (11) Then, another conductive layer 33o is formed on the substrate 300, and this 330 fills the gap between the two conductive layers 31 6a. The conductance q is doped polycrystalline silicon. The material of the shape of the conductor layer 33G is, for example, chemical vapor deposition on the substrate 30. On formation! If it is first doped with ^ layer, it is used to remove part of the dopant ^ by chemical mechanical polishing method or etch-back method until at least the surface of the cap layer 3 1 0 is exposed. However, θ: said 'layer-layered patterned photoresist layer (not shown), this figure represents the' blocking soil &amp; 00 ^ distribution, which is used to define the photoresist control layer of the flash memory in a stripe pattern. The doped polycrystalline silicon layer covered by the photoresist layer is controlled to be removed without patterning the conductive layer 330. The conductive layer 330 is used as the second fast photoresistor layer. | 邗 4 Flash memory control gate Next, referring to Figure 3D, perform a 龅 2 Μ body layer 308-side (the side where the drain is scheduled) and guide 332. Then, a lightly doped region is formed on the cap layer 310 and the conductor bank 32 = 0, and a spacer 334 is formed. The shape of the wall 334 and the dielectric layer followed by the side wall 3. 〇-layer insulation layer (not shown in the figure to remove part of the insulation layer to form it. After that, the _ specific orientation lasting method, and on the side of the partition wall 334 (scheduled, and engage another ion The implantation step becomes a heavily doped region 336. The 'lightly doped region (卩)' side) of the substrate 300 is shaped as a drain region 338 of the flash memory. The rear region ^. Also, the agricultural replacement region 336 constitutes a familiar item. As known to the skilled person, the process of flash memory is that in the above embodiment, the present invention is a gate electrode (conductor layer 316a), and the alignment method can be formed to have the same length. The channel area of the adjacent memory cells is used for this flash memory because the shared source

200410402 V. Description of the invention (12) The length of the channel region of H's cell is ㈣, so it can avoid the problem of asymmetry of the memory cell, and can improve the sound of the memory. In addition, the floating gate electrode (conductor layer 316a) is formed as "[X. The area between the two energized σ-sea closed poles (conductor layer 316a) and the control" ', which increases the gate coupling rate and improves ^ 体 / 330) Although the present invention has been disclosed in a preferred embodiment to limit the present invention, anyone skilled in the art is not using God and the range π, and can make various changes: The scope of intensive protection is subject to the scope of the patent, please be bound by the scope of the patent = the guarantee of the present invention 10220twf.ptd page 18 200410402 Simple illustration of the diagram Simple illustration of the diagram: Figure 1A to 1C Know the cross-sectional structure diagram of the flash memory manufacturing process. FIG. 2A to FIG. 2F are cross-sectional flowcharts of manufacturing a flash memory according to a preferred embodiment of the present invention. FIG. 3A to FIG. 3D are cross-sectional flowcharts of manufacturing a flash memory according to another preferred embodiment of the present invention. Graphical description: 100, 200, 30 0: substrate 102, 20 6, 30 6: dielectric layer 104: selection gate 106, 312: tunneling oxide layer 108, 112, 112a, 226, 326: gate Dielectric layers 110, 114, 208, 208a, 216, 216a, 230, 308, 316, 316a, 330Conductor layer 114a: Control gate 11 0a: Floating gate 116, 224, 324: Source region 118, 240, 338: Drain region 120a, 120b: Channel region 202, 302: Deep N-type well region 204, 304: P-type well region 210, 210a, 310: Cap layer 214, 23 6, 238, 314, 317a, 334: partition wall

10220twf.ptd Page 19 200410402 Schematic description 218, 220, 232, 318, 320: Patterned photoresist layer 222, 322: Doped implant process 2 2 8, 3 2 8: Insulating layers 234, 332: Light Doped regions 240, 336: heavily doped regions 3 1 7: material layer 11H · 10220twf.ptd page 20

Claims (1)

200410402 VI. Scope of Patent Application ------- 1 · A method for manufacturing flash memory, the method includes the following steps: a substrate is provided, and a first gate structure and a second A gate structure, the first gate structure and the second gate structure are each composed of a dielectric layer, a first conductor layer, and a capping layer; a tunneling oxide layer is formed on the substrate, and Forming a first gap wall on a side wall of the first conductor layer; forming a second conductor layer on a side wall on one side of the first gate structure and the second gate structure that is intended to form a source region; The source region is formed in the substrate; an inter-gate dielectric layer is formed on the second conductor layer, and an insulating layer is formed on the surface of the substrate in the source region; the first gate structure and the second gate are formed. A third conductor layer is formed between the electrode structures; and a drain region is formed in the substrate. 2. The method of manufacturing a flash memory as described in item 1 of the scope of patent application, wherein the first conductor layer is used as / selected a gate electrode. 3. The method of manufacturing a flash memory as described in item 1 of the scope of the patent application, wherein the second conductor layer is used as a floating gate. 4. The flash memory manufacturing method 4 described in item 1 of the scope of the patent application, wherein the third conductor layer is used to control the gate. Every 5 · The method for manufacturing a flash memory as described in item 丨 of the patent application scope, wherein the material of the inter-gate dielectric layer includes silicon oxide / silicon nitride / oxide 200410402 6. Scope of patent application 6. As the application method, in which one side of the source region faces the substrate and the first first patterned light is removed from the unlayer; moved into the seventh method, whose first The third lead is to move the layer in the second picture; using the method of shift 8. Its third lead, the second, and the second row of non-equal two conductors, such as the application on the base of the body layer, the second case, the light has not been removed, and Except for the first gate structure and the second gate structure of the flash memory, as described in item 1 of the bulkhead patent scope of the bulk layer in the application, the second gate structure is intended to form the second side wall. The step of the conductive layer includes: forming a first conductive material layer on the μ; forming a first patterned photoresist layer on the conductive material layer, the resist layer covering an area intended to form the source region; the first patterned photoresist A patterned photoresist layer covered by the first conductive material; and removing the first conductive material layer by an etch process to form a layer. The manufacturing method of the flash memory described in item 1 of the yf range: forming a gate structure between the second gate structure and the second gate structure includes: forming a second conductor material layer on the conductor material layer; Forming a stem _ ^ # ^ ^, Di Yi patterned photoresist layer, the ^ layer is covered with pre-formed areas to form the source region; 呑 first patterned photoresistive acoustic frost Yunqi "# 〆 印 载 盍The second conductive material includes two patterned photoresist layers. ^ The first gate structure of the manufacturer of the flash memory described in item 7 of the Li Fanmu and the flute _ body ^ body of the step t Θ k is formed between the first gate structure and the step is further included in 1. Formation of the side wall of the second conductor layer l〇220twf.ptd Page 22 200410402 Scope of patent application ____ Half Λ ΐ The manufacturer of the flash memory described in item 1 of the patent scope, the third conductor step, the structure and the second gate structure are formed A third conductive material layer is formed on the substrate; a part of the third conductive material is removed; &amp; μ W: a conductive material layer until the capping layer is exposed; One sign of two cabinets / 丨 丨 ^ 1¾ ^ ^ ^ a. A first patterned photoresist layer, and the third patterned photoresist layer covers an area that is intended to form the source region; remove the third pattern The third conductive material layer covered by the photoresist layer, and removing the third patterned photoresist layer. 10. The method for manufacturing a flash memory as described in item 1 of the scope of the patent application, wherein the step of forming the drain region in the substrate includes: forming a lightly doped region in the substrate; A gate structure and the second gate structure are intended to form a third gap wall on a sidewall of one side of the drain region; and a heavily doped region is formed in the substrate. 11. A method for manufacturing a flash memory, the method comprising the steps of: providing a substrate on which a first gate structure and a second gate structure have been formed; the first gate structure and the second gate structure; The gate structure since 'θ is composed of a dielectric layer, a first conductor layer, and a cap layer; 疋 forming a tunneling oxide layer on the substrate, and forming a first on the acoustic side wall of the i-th conductor A spacer; 9 forming a first conductive material layer on the substrate; 200410402 6. The scope of the application for a patent forms a material layer on the first conductor material layer; a 筮 m 9, .Pθ ^ ^ first patterned photoresist layer is formed on the material layer, and the first pattern is first blocked Layer overlying a region that is intended to form a source region; removing the layer and the first conductive material layer that are not covered by the first patterned photoresist layer; removing the first patterned photoresist layer; The directional etching process removes part of the material layer and the first conductor material layer to form a second gap wall and a second conductor layer; removes part of the second gap wall; The second gate structure is intended to form the source region in the substrate forming the source region; an inter-gate dielectric layer is formed on the second conductor layer, and an insulating layer is formed on the surface of the substrate in the source region. Forming a third conductor layer between the first gate structure and the second gate structure; and the side where the first gate structure and the second gate structure are intended to form a side of a drain region; The drain region is formed in the substrate. 12. The method for manufacturing a flash memory as described in item 11 of the scope of patent application, wherein the first conductor layer is used as a selective gate. 1 3 · The method for manufacturing a flash memory as described in item 11 of the scope of patent application, wherein the second conductor layer is used as a floating gate. 14. The method for manufacturing a flash memory as described in item 11 of the scope of patent application, wherein the third conductor layer is used as a control gate. 1 5 · Manufacture of flash memory as described in item 丨 丨 of the scope of patent application 10220twf.ptd Page 24 200410402 6. Scope of patent application Method, in which the material of the dielectric layer of the gate is silicon. Silicone / Silicon Nitride / Oxidation 16. If the scope of the patent application is No. 11, household method, ten or ten A f method, where the -gate structure and the second conductor layer The steps include: forming a second conductor material layer on the substrate between the structures; forming a second layer on the first conductor material layer; a patterned photoresist layer covering a region layer intended to form the source region; The second conductive material covered by the second patterned photoresist layer removes the second patterned photoresist layer. 17. The method for manufacturing a flash memory as described in item 6 of the scope of patent application, wherein after the step of forming the third conductor layer between the first gate structure and the first gate structure, A third gap is formed on the third conductive layer. 7 1 8 · The method for manufacturing a flash memory according to item 丨 丨 in the scope of patent application, wherein the step of forming the third conductor layer between the first gate structure and the second gate structure includes: 7 forming a third impurity-conducting material layer on the substrate; removing part of the third conductive material layer until the top cap layer is exposed; forming a third patterned photoresist layer on the substrate, the third case The photoresist layer covers the plaque area that is intended to form the source region; removes the third conductor material layer that is not widely covered by the third patterned photocell; and 10220twf.ptd 25th tribute 200410402 The third patterned photoresist layer is removed. 19. The method for manufacturing a flash memory as described in item 11 of the scope of patent application, wherein the step of forming the drain region in the substrate includes: forming a lightly doped region in the substrate; A fourth spacer is formed on a sidewall of the gate structure and the second gate structure that is intended to form one side of the drain region; and a heavily doped region is formed in the substrate. 20. The method for manufacturing a flash memory according to item 11 of the scope of the patent application, wherein the material of the material layer, the material of the cap layer, and the material of the second conductor layer have different etching selectivities. 10220twf.ptd Page 26