TW200410399A - Nitride read only memory and the manufacturing method thereof - Google Patents

Abstract

A nitride read only memory is consisted of: a control gate is set on the substrate, a source region and a drain region is set in the substrate set at the two side of the control gate, an electron trapping layer is set between control gate and substrate, and a channel region is set below the electron trapping layer between the source region and the drain region. Wherein an isolated region is set in the electron trapping layer for separating the electron trapping layer into source side electron trapping block and drain side electron trapping block to form a binary bit structure.

Description

200410399 V. Description of the invention (l) Technical field to which the invention belongs The present invention relates to a non-volatile memory (Non — ν〇 丨 a t i i e

Memory), and in particular, it relates to a silicon nitride read-only memory and its manufacturing method. Electrically Erasable Programmable Read Only (EEPR0M) in the non-volatile memory of the prior art can perform multiple operations of data storage, reading, erasing, and the like. The advantage that data will not disappear even after power failure = it has become a widely used memory element in personal computers and electronic devices; Zha 3:: fr erased and programmable read-only memory system 』Gat :) When the gate (F1〇atlng Gate) and the control gate (Control electron / both § \ v body right are stylized (Pr0graiD)), the injection floats are uniformly distributed throughout the polycrystalline stone float In the interlayer electrode layer, the leakage current under the electrode layer and the presence of defects in the oxide layer may affect the reliability of the device. The problem of current flow, before ^: A method of electrically erasing private read-only memory element leakage 1 Polycrystalline silicon floating gate is to use a charge trapping layer to take # kinds of silicon nitride charges ρ 丄 !! The material of the layer is, for example, silicon nitride. ^ A kind of stacking type containing oxygen: dinitrogen-into-layer force: usually has -layer oxidation ... forms-(Stacked) leisure structure stone, single ancient silicon (〇βΝ〇) composite layer is called silicon nitride So far, EEPR0M with this stacked gate structure is NR0M. When a voltage is applied to the control of this device, the invention is described in (2) the gate electrode and the source / drain region ~ ^ 'where the hot electrons will be generated in the electrode region, and the injection process is tokenized, the channel region is close to the drain. With the characteristics of trapping electrons' therefore; Because the nitride stone is not evenly distributed in the localized area of the charge-injection trap layer. !! Into the layer, but concentrated in the local area of U, therefore, the electrons trapped in the charge trapping layer are only concentrated in a small phenomenon. It is not easy: when the sensitivity of the defects in the formation layer is reduced, the stacking type can be made; : Another advantage is that the program voltage is being performed, and the source / drain region near the-side has a higher si, and it can also make people in the gasification layer stacked in the open-diode region have a higher level. The electrons are stored in the source / drain region on the other side of the $ pole. Therefore :: The voltage applied to the source / drain region of the nitrided f-drain region and the sources on both sides of it can be read-only among the two groups of electrons and the early siliconized silicon layer. Memory can | w From: 疋 There are no electrons. Therefore, there are four states written in the binary open-cell β ^ cryptic cell of the silicon nitride species as one body. (1 1 ^ Μ 1 1) Stored non-volatile memory However, it is common practice to inject _ ^ into the thunderbolt P Λ @ 9 two-bit silicon nitride read-only memory when programming, the cloth layer: thermionic According to the injected energy, electrons are formed to produce the so-called electric j. The two bits of the memory cell will affect each other and

Effect) 'and-Λ injection effect: Εΐ6 "Γ〇η SeC〇ndary ^ The distribution curve is broadened and connected together. Therefore, during the erasure, Yu Lei 4 and He He sink into the layer and are formed by injecting thermo holes. The distribution curve will be

200410399 V. Description of the invention (3) Method and electronic distribution curve & ,, .. Compare: the erasing time "question 7ε", which results in the inability to completely erase the effect of the injection of the thermoelectric hole of the hole-requiring system. Because the electric charge is trapped in the layer of the electric side (or the source side) of the electric two, and the injection: He is trapped in the electric hole of the layer. 曰 ^ ^ ^ ^ Wang will have too much or too little electricity to control easily Therefore, in the erasing process, it may occur when this is excessive = ir, Gver Erase) or cannot be erased. The reliability of the memory element (ReliabU is serious ... invented the internal guest w | low cattle. In view of this It is an object of the present invention to provide a memory body and a method for manufacturing the same, which can avoid nitrogen two: eliminate the phenomenon and improve the reliability of the memory element. Another object of the system is to provide a nitrogen Silicon read-only memory and the Yame & method, capable of storing multiple bits in a single memory cell, can increase the degree of component accumulation.。 贝 疋 10 卞 The invention provides a silicon nitride read-only memory 'this nitrogen Silicon memory is controlled by a gate on the substrate A source region and a drain region of a substrate disposed on both sides of the control gate, a charge trapping layer disposed between the control gate and the substrate, and a substrate disposed below the charge trapping layer and between the source region & drain ^ The charge trapping layer has an isolation region ', and this isolation region separates the charge trapping layer into a source region charge trapping block and a drain region charge trapping block, and becomes a two-bit structure. In the above structure, the isolation region in the charge trap layer causes the charge to trap

200410399 V. Description of the invention (4) The problem of separation into two electric and electric trapped areas and two trapped layers of the charge trapped layer cells. The memory of the present invention is composed of a power source pole region between the bottom and a $ and a drain region. The charge trapped block array formed by the zone is from the source two charges trapped in the block and the same column pressure is lower than the starting voltage of the different columns. The charge trapping block (source-side charge sinking block and drain-side block) forms a two-bit structure, and because the isolation zone separates into two independent charge trapping blocks (that is, the memory cells are separated from each other) 'As a result, the so-called secondary electron injection can be avoided, and component reliability can be improved. A silicon nitride read-only memory is provided. The silicon nitride read-only memory is a control gate disposed on a substrate, a polar region disposed on a control gate and a base charge trapping layer, and a substrate disposed on both sides of a charge trapping layer. And a spacer disposed in the charge trapping layer, the channel region disposed under the charge trapping layer and located in the source region and the substrate. Among them, the isolation region separates the charge trapping layer into a plurality of electric charges to form an array of charge trapping blocks. The direction from the charge trapping block to the drain region is a column direction, and each column includes the block. Including η (n is a positive integer) charge traps and 'this silicon nitride read-only memory is in the state where no charge is written in the channel area where the charge traps below the block with the same initial charge trapped below the block The channel region has different implications. In the above-mentioned silicon nitride read-only memory, the control gate and the layer of charge trapping layer have an open dielectric between the substrate and the substrate. In the above structure, the isolation region in the charge trapping layer makes Electricity is divided into 丄, 々, 』, lu, lu, lu, lu, lu, Μ, Μ, and 电荷, which are carved into a block of charge and formed a multi-bit structure, and ^ ^ 1 歹 歹 1 The channel area below the block has different starting power. Yuzhi 〇 因 ιΗ

200410399 V. Description of the invention (5) The amount of data of multiple bits can be stored in a single memory cell, which can increase the amount of component data storage and component accumulation. Moreover, because the isolation region separates the charge trapping into multiple charge trapping blocks (that is, the bits of the memory cell are separated from each other), the problem of so-called secondary electron injection can also be avoided, and the reliability of the device can be improved. The invention provides a method for manufacturing a silicon nitride read-only memory. The method is to sequentially form a silicon oxide layer and a charge trapping layer on a substrate, and then form an isolation region in the charge trapping layer. The trap layer is separated into a plurality of charge trap blocks, and these electric trap blocks form an array of charge trap blocks, and the direction of the charge trap block array from a bit line to another bit line is a column direction. Each column includes two charge trapping blocks, and each row includes n (n is a positive integer) charge trapping blocks. Then, a gate dielectric layer is formed on the charge trapping layer, and the gate dielectric layer and the charge trapping layer are patterned to expose a region where a bit line is to be formed. Next, a bit line is formed in the substrate on both sides of the charge trapping layer, and a control gate is formed on the charge trapping layer. Then, an initial voltage adjustment step is performed so that the channel regions under different columns of charge trapping blocks have different channel regions. The starting voltage. In the manufacturing method of the silicon nitride read-only memory described above, the material of the charge trapping layer is silicon nitride. Moreover, a method for forming an isolation region in the charge trapping layer is to form a patterned photoresist layer on the charge trapping layer to expose a region intended to form an isolation region, and then perform an ion implantation step in the region where the isolation region is to be formed. An oxygen ion is implanted and a tempering process is performed to make the oxygen ion react with the silicon of the charge trapping layer to form an isolation region. In addition, in the method for manufacturing a silicon nitride read-only memory,

z9947twf.ptd Page 9 200410399 V. Description of the invention (6) It includes forming a field oxide layer on the bit line. In the above-mentioned silicon nitride read-only memory, a region is formed by implanting oxygen ions in the charge trapping layer to separate the electric street trapping layer into a plurality of regions, and the channel region below the block has different initial values of the memories. The cell has a multi-bit structure, and can increase the number of bits of stored data under conditions, and because the isolation zone separates the charge into layers (that is, the bits of the memory cell are separated from each other). This is called secondary electron injection. Problems arise. In order to make the above and other objects of the present invention comprehensible, a preferred embodiment is exemplified below and described in detail as follows: Embodiments, please refer to the attached drawings, which are used to describe the memory structure. Fig. 1A (top view) shows a read-only record of silicon nitride according to an embodiment of the present invention and Fig. 2B is a top view showing the structure of another embodiment of the present invention, respectively. In Figures 2a and 2β, Figures 1B and 1B are given the same reference numerals, and reference is made to Figures 1A and 1B. According to the present invention, the substrate 1 0 〇, the gate structure 1 02, The source region is composed of the channel region 107. The gate structure 102 is located at the base and the non-electrode region 106 is located at the gate structure 102 respectively. The present invention borrows an isolation region. Because this isolation and the charge of different columns are trapped in the voltage, it can increase the degree of component integration without increasing the volume of the memory cell. By forming a plurality of independent regions, it is also possible to avoid the characteristics and advantages more clearly. In accordance with the drawings, a detailed description will be given of the structure of the nitride of the present invention and FIG. 1B (cross-sectional view). Fig. 2A illustrates the components of the nitrided eve only reading memory and Fig. 1A, and the description is omitted. The silicon nitride read-only memory 104 is connected to the drain region 106 and the bottom 100. The substrate 100 on the 104 side of the source region. through

200410399 V. Description of the invention (7) The second channel is placed in the substrate 100 between the source region 104 and the drain region 106 under the intermediate electrode structure m. μ: “η” is composed of the tunneling oxide layer 108, the charge trapping layer 110, and “A” and the control gate 1 1 4. The control gate 1 1 4 is set to the second base P: 〇〇 'charge sink The layer 110 is disposed between the control gate 1 " and the substrate 100. The gate dielectric layer 112 is disposed between the control gate 114 and the charge trapping layer no, and the gate dielectric layer 112 is, for example, a silicon oxide layer. The tunneling oxide layer 108 = is placed between the charge trapping layer 110 and the substrate 100. In the charge trapping layer 11 = there is an isolation region 116, which isolates the charge trapping layer. He is trapped in a block to form a multi-bit structure. These electric traps are formed into an array, and the direction from the source region 104 to the drain region is a column direction. Among them, the charge trapping region In the block array, each column includes two charge trapping blocks, and each row includes several charge trapping blocks. And 'This silicon nitride read-only memory has no charge trapping region in the same row when no data is written. The channel area below the block has the same starting voltage, = There are different starting voltages. In this embodiment, the example is divided into (2 arrays) four charge trapping blocks (110 a, 11 0 b, 1 1 〇c11 〇d) for illustration. Therefore, in the unwritten In the state of tribute, the charge trapping block 11 0a in the first column and the channel region under the charge trapping block 1 1 Ob have the same starting voltage. The charge trapping block 110c in the second column and The charge trapping block 11〇 (channel area 107b below 1 has the same starting voltage. The charge trapping block in the first column 丨 丨 a and the charge trapping block 丨 丨 0b channel area 丨 07a and the first The charge trapping block 110c in the two columns and the channel region 107b below the charge trapping block 1104 have

m7twf.ptd im Page 11 200410399 V. Description of the invention (8): ------- ^ Different starting voltages. In the above structure, the isolation region 1 1 6 in the charge trapping layer π 0 causes the electric trapping layer 110 to be separated into four charge trapping blocks (n〇a, n〇b, n〇c, and ^ 〇 〇 d) A four-bit structure is formed, and the charge trapping block 110a and the charge sinking channel region 107a and the charge trapping block 117a and the charge trapping channel under the block 110d are formed. 1071) have different starting voltages. Therefore, the data volume of four bits can be stored in a single memory cell, and the accumulation degree of all pieces can be improved. Moreover, because the isolation region 丨 6 separates the charge trapping layer 1 10 into four independent charge trapping blocks (that is, the four positions of the memory cell are separated from each other) ', so the so-called secondary electron injection can also be avoided. Problems arise, which can increase component reliability. — In the above structure, the charge trapping layer 11 10 is separated into four charge trapping blocks 1 1 〇a ～ i i 〇d as an example. Of course, the charge trapping layer U 0 can also be separated into two charge trapping blocks (for example, separated into two charge trapping blocks not shown in Figure 2A), or more than four charges. Trapped in the block (for example, the six charge trapped blocks shown in Figure 2B are separated into 11 〇a ~ 1 1 〇f), and then the channel areas under different blocks of charge trapped blocks have different starting voltages , And can form a multi-bit structure. The above describes the structure of the silicon nitride read-only memory of the present invention, and then describes the method of manufacturing the silicon nitride read-only memory of the present invention. 3A to 3E are top views of the manufacturing process of the flash memory of the present invention. Figures 4A to 4G are cross-sectional views showing manufacturing processes taken along lines B-B in Figures 3A to 3G, respectively. First, please refer to FIG. 3A and FIG. 4A to provide a substrate 2 0 0.

$ 947twf.ptd

200410399

The substrate 2 0 is, for example, a silicon substrate. Then, an oxide layer 202 is formed on the substrate 200 as a tunneling oxide layer. This oxide layer 20 is shaped like a thermal oxidation method. The next step is to form a charge trapping layer 204 on the oxide layer 202. The material of the charge trapping layer 204 is, for example, silicon nitride. The method for forming the charge trapping layer 204 is, for example, a chemical vapor deposition method.乂 Next, please refer to FIG. 3B and FIG. 4B to form a patterned photoresist layer 206 on the charge trapping layer 204. The patterned photoresist layer 206 exposes a region of the charge trapping layer 204 that is intended to form an isolation region. Dump

Then, an ion implantation step 208 is performed, using the patterned photoresist layer 206 as a mask, and oxygen ions are implanted in the charge trapping layer 206 exposed by the patterned photoresist layer 206, and the charge is An oxygen ion doped region 21 () is formed in the sink layer 204. The implantation dose of oxygen ions is about 10 I8 atoms / cm 2 to 2 οι 8 atoms / cm 2 and the implantation energy is about 20 仟 electron volts to about 80 仟 electron volts. Next, referring to FIG. 3C and FIG. 4C, after the patterned photoresist layer 206 is removed, a tempering process is performed so that oxygen ions and the stone Xi in the charge trapping layer 204 react to form silicon oxide to form isolation. District 21 2. Temperature of this tempering process

For example 疋 9 5 0 C to about 1 150 ° C. Among them, the isolation region 2 1 2 separates the charge trapping layer 204 into a plurality of isolated charge trapping blocks. In this embodiment, the isolation region 212 is used to isolate the charge trapping layer 204 of a single memory cell into four charge trapping blocks for illustration. Next, please refer to FIG. 3D and FIG. 4D. Then, a gate dielectric layer 2 1 4 is formed on the substrate 2000. The gate dielectric layer 1 丨 4 is, for example, silicon oxide

200410399

The thickness of the gate dielectric layer 214 is, for example, about 50 to 150 angstroms. The method for forming the electrical layer 214 is, for example, chemical vapor deposition. Then, a patterned photoresist layer 216 is formed on the dielectric layer 214. This patterned layer 2 1 6 exposes areas where bit lines are to be formed. Floor. The pole is between the gate photoresistor 21fUf with reference to Figures 3E and 然后. Then, the patterned photoresist is used as a mask. Part of the open-electrode dielectric layer 214 and the charge trapping layer 204 are exposed. The area of the yuan line. Then, using a patterned photoresist layer 216 as a mask, dopants are implanted into the substrate 200 on both sides exposed by the patterned 216, and the doped region 220 (bit Yuan line). The implanted dopants are, for example, arsenic ions, and the implantation dose of arsenic ions is 2 atoms / cm 2 to 4. It is about 15 atoms / square A knife, and the implantation energy is about 50 仟 electron volts. Next, please refer to FIG. 3F and FIG. 4F. After removing the patterned photoresist layer 2J6, a thermal process is performed to shape the surface of the doped region 22 (bit line) ^ the emulsified layer 222 and activate the doped region. 2 2 0 dopants. The field oxide layer is used to isolate the doped region 22 (bit line) from the control electrode C word line formed later). Then, a conductor layer 2 2 4 is formed on the substrate 2000. The material is, for example, doped polycrystalline silicon. The formation method of the conductor layer 224 is, for example, using a method of implanting dopants and chemical vapor deposition. To form it. Next, please refer to FIG. 3G and FIG. 4G. A mask (not shown) is used to pattern the body layer 224 to define the control gate electrode 226 (word line). While defining the conductor layer 224, continue to define the gate dielectric layer 2 1 4, the charge trapping layer 2 04 and the dielectric layer 2 2 with the same mask to form a gate structure. also

200410399 V. Description of the invention (π) means' the gate structure of the read-only memory of the present invention is controlled by the gate 2 2 8, the gate dielectric layer 2 1 4, the charge trapping layer 2 0 4 and the oxidation It is composed of a stacked structure of layers 2 0 2. In this embodiment, the charge trapping layer 204 of each memory cell includes at least four separate charge trapping blocks 204a, 204b, 204c, and 204d separated by the isolation region 2 12, where the charge trapping block 204a , 2 0 4b, 20 4c, and 20 4d are tied into a 2 array. Then, a process of adjusting the starting voltage is performed. First, a patterned photoresist layer 228 is formed on the substrate 200, and the patterned photoresist layer 228 at least exposes a charge trapped to the control gate 2 2 6 above the blocks 2 0 4 c and 2 4 d. then,

Using the patterned photoresist layer 228 as a mask, an ion implantation step is performed, and an impurity is implanted in the channel region 230b under the charge trapping block 204c and 204d to adjust the channel region under the charge trapping block 204c and 204d. 230b starting voltage. Thus, the channel region 230b under the charge trapping blocks 204c and 204d and the channel region 230a under the charge trapping blocks 204a and 204b have different starting voltages. Therefore, a memory cell can be used to store four bits of data. Later, the production process of Jiyuancheng Gas Fossil's only item of memory is well known to those skilled in the art, and will not be repeated here.

In the above embodiment, the present invention forms an isolation region 2 1 2 by implanting oxygen ions in the charge trapping layer 204. This isolation region 2 1 2 separates the charge trapping layer 2 0 4 into a plurality of charge trapping blocks to form a multi-bit structure. Therefore, without increasing the volume of the memory cell, the number of bits of stored data can be increased and can be improved. Component accumulation. Moreover, since the isolation region 212 separates the charge trapping layer 204 into four independent regions (that is, the four bits of the memory cell are separated from each other) ', the problem of so-called secondary electron injection can also be avoided.

200410399 V. Description of invention (12) In addition, this isolation region 2 1 2 can also separate the charge trapping layer 204 into more than four regions (for example, six or eight), and then make the charge trapping regions under different columns have different channel regions. The initial value voltage can form a multi-bit structure. Although the present invention has been defined by a better one, anyone familiar with this god and scope, when it can make a little coverage, see the attached patent application embodiment as disclosed above, but it is not a skilled person, The refinement and retouching of the present invention are defined by the scope of the present invention.

Page 16 200410399 Brief description of the drawing Figure 1A shows the structure of a silicon nitride read-only memory according to an embodiment of the present invention; Figure 1B shows the diagram along AA in Figure 1A 2A and 2B are top views showing the structure of a nitride nitride read-only memory according to another embodiment of the present invention; FIGS. 3A to 3G are shown as Top view of the manufacturing process of the invented silicon nitride read-only memory; and FIGS. 4A and 4G are cross-sectional views of the manufacturing process taken along lines BB 'in FIGS. 3A to 3E. Description of diagrams: 100, 20 0: substrate 1 0 2: gate structure 1 0 4 · source region 10 6: drain region 107, 107a, 10 7b, 230a, 230b: channel region 1 0 8: through Tunnel oxide layer 1 1 0, 2 0 4: charge trapping layer 1 1 2, 2 1 4: gate dielectric layer 114-22 22: control gate 1 1 6, 2 1 2: isolation regions 110a, 110b, 110c , 110d, 110e, 110f, 204a, 204b, 204c, 20 4d: charge trapped block 2 02 · · oxide layer 2 0 6, 2 1 6, 2 2 8: patterned photoresist layer

^ 7twf, ptd page 17 200410399 Brief description of the drawings 208, 218: ion implantation steps 210, 220: doped region 2 2 2: field oxide layer 2 2 4: conductor layer page 18 Eryang 7twf .ptd

Claims (1)

200410399 6. Application Patent Scope 1. A silicon nitride read-only memory, the silicon nitride read-only memory includes: a substrate; a control gate, the control gate is disposed on the substrate; a source region and A drain region, the source region and the drain region are disposed in the substrate on both sides of the control gate; a charge trapping layer is disposed between the control gate and the substrate, and the charge The trap layer has an isolation region, and the isolation region separates the charge trap layer into a source region charge trap block and a drain region charge trap block to form a two-bit structure; and a channel region, the The channel region is disposed in the substrate below the charge trapping layer and between the source region and the anode region. 2. The silicon nitride read-only memory according to item 1 of the patent application scope, further comprising a gate dielectric layer, the gate dielectric layer being disposed between the control gate and the charge trapping layer. 3. The silicon nitride read-only memory according to item 2 of the scope of patent application, wherein the gate dielectric layer includes a silicon oxide layer. 4. The silicon nitride read-only memory according to item 1 of the scope of the patent application, further comprising a tunneling oxide layer disposed between the charge trapping layer and the substrate. 5. The silicon nitride read-only memory described in item 1 of the scope of the patent application, wherein the material of the charge trapping layer includes silicon nitride. 6. The silicon nitride read-only memory as described in item 1 of the scope of patent application, wherein the material of the isolation region includes silicon oxide. 1 9947twf.ptd Page 19 200410399 VI. Patent Application Range 7 · A kind of silicon nitride read-only memory, the silicon nitride read-only memory includes: a substrate; a control gate, the control gate is arranged on the substrate A charge trapping layer disposed between the control gate and the substrate; a source region and a drain region disposed on both sides of the charge trapping layer In the substrate; a channel region disposed in the substrate below the charge trapping layer and between the source region and the non-polar region; and an isolation region disposed in the charge trapping layer And the isolation region separates the charge trapping layer into a plurality of charge trapping blocks to form an electric trapping block array. The direction of the charge trapping block array from the source region to the drain region is Column direction, each column includes two charge trapping blocks, and each row includes n charge trapping blocks (η is a positive integer); wherein the silicon nitride read-only memory is in a state where no data is written, Those charges in the same column Into the channel region below the threshold voltages of blocks having the same 'different columns of the plurality of charge trapping region below the channel of the blocks having different threshold voltages. 8. The silicon nitride read-only memory according to item 7 of the scope of the patent application, further comprising a gate dielectric layer ', which is disposed between the control gate and the charge trapping layer. 9. The rat fossil evening read-only memory as described in item 8 of the patent application scope, wherein the gate dielectric layer includes a silicon oxide layer. ' 9947twf .ptd Page 20 200410399 VI. Patent application scope 10 · The silicon nitride described in item 8 of the patent application scope further includes a tunneling oxide layer which is disposed between the layer and the substrate. . 1 1 · The nitride nitride as described in item 8 of the scope of patent application, wherein the material of the charge trapping layer includes silicon nitride. 1 2 · The silicon nitride according to item 8 of the scope of patent application, wherein the material of the isolation region includes silicon oxide. 1 3 · A method for manufacturing a silicon nitride read-only memory The following steps: Provide a substrate; form a silicon oxide layer on the substrate; form a charge trapping layer on the oxide layer; and form in the charge trapping layer An isolation zone, the separation trap layer is separated into a plurality of charge trap blocks, and the electricity forms a charge trap block array. The direction of the charge trap block to another bit line is a column direction, and each column traps Block, each row includes η (η is a positive integer) electrically forming a gate dielectric layer on the charge trapping layer; patterning the gate dielectric layer and the charge trapping layer to form the bit lines Area; forming a control gate on the charge trapping layer in the substrate on both sides of the charge trapping layer; performing an initial voltage adjustment step so that the channel regions under different columns of blocks have different Start voltage. The read-only memory is placed in the charge-trap read-only memory and the read-only memory. The method includes detaching the region and causing the charge charge to fall into a block-shaped column. One bit line includes two charge charges into the block; Pre-determined bit lines; and the charges are trapped " 9947twf .ptd Page 21 200410399 VI. Application for patent scope 1 4 · The manufacturing method of lice-ready silicon read-only memory as described in item No. 丨 3 of the patent scope, wherein the charge trapping layer is ^ including nitrogen Silicon. . 1 5. The method for manufacturing a silicon nitride read-only memory as described in item 13 of the scope of patent application, wherein the method of forming the isolation region in the conductor layer includes: forming a patterned light on the charge trapping layer A resist layer, the patterned photoresist layer is exposed to the area where the isolation area is to be formed, an ion implantation step is performed, an dopant is implanted in the area where the isolation area is to be formed; and a tempering process is performed to make the doping The mass reacts with the silicon of the charge trapping layer to form the isolation region. 16 · The method for manufacturing a silicon nitride read-only memory as described in item 15 of the scope of patent application, wherein the dopant implanted in the ion implantation step includes oxygen ions. 17 · The method for manufacturing a silicon nitride read-only memory as described in item 16 of the scope of patent application, wherein the implantation dose of oxygen ions includes about 1018 atoms / cm 2 to about 2018 atoms / cm 2. ^ 1 · The method for manufacturing a silicon nitride read-only memory as described in item 16 of the scope of patent application ', wherein the implantation energy of oxygen ions is about 120 仟 electron volts to about 80 φ 仵 electron volts. 19 · The manufacturing method of silicon read-only memory as described in item i 6 of the scope of the patent application, wherein the tempering process includes a range of 95 ° to 1150 ° C. 2 0 · Silicon nitride read-only memory as described in item 6 of patent application 200410399 ^ 47twf.ptd p. 23