TW200410349A - Method for analyzing wafer test parameters - Google Patents
Method for analyzing wafer test parameters Download PDFInfo
- Publication number
- TW200410349A TW200410349A TW91135096A TW91135096A TW200410349A TW 200410349 A TW200410349 A TW 200410349A TW 91135096 A TW91135096 A TW 91135096A TW 91135096 A TW91135096 A TW 91135096A TW 200410349 A TW200410349 A TW 200410349A
- Authority
- TW
- Taiwan
- Prior art keywords
- batch
- item
- wafer test
- wafer
- low
- Prior art date
Links
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
200410349 五、發明說明(1) (一)、【發明所屬之技術領域】 一種 本發明係關於一種製程參數分 晶圓測試參數之分析方法。 (二)、【先前技術】 製造技術中’要完成-半導體產品通常要經 j即在半導:如微影製程、蝕刻製程、離子植入製卷 台,以及許多繁項in'r到龐大數量的機200410349 V. Description of the invention (1) (1), [Technical field to which the invention belongs] This invention relates to a method for analyzing process parameters and wafer test parameters. (II) [Previous technology] In manufacturing technology, 'to be completed-semiconductor products usually go through j, that is, semiconducting: such as lithography process, etching process, ion implantation rolling table, and many complicated in'r to huge Number of machines
於確保機台運作正常皆致力 題點以及機台維修等作、積測確認" >寺作業,以期使半導體產品的生產速肩 及品質能夠合乎客戶需求。To ensure the normal operation of the machine, we are committed to the problems, machine maintenance, etc., and cumulative inspection " > temple operation, in order to make the production speed and quality of semiconductor products meet customer needs.
& ^二般而έ ’要探討半導體製程的問題可以從下列數項 資料著手進行分析,包括製程參數資料、線上品質測試 (In line QC) > 料 '缺陷檢測(defect inspection) 貢料、樣品測試(samp丨e test )資料、晶圓測試(wafer test )資料以及封裝後測試(final test )資料。其中, 晶圓測試資料乃是對晶圓進行特性測試(pause refresh t e s t )、功能測試(f u n c t丨〇 ^ t e s㈠及電源供應電流測 試(IDDQ test )所得到的測試值。 在習知技術中,請參照圖1所示,首先進行步驟1 〇 1, 此時熟知技術者會針對每一晶圓進行各項晶圓測試項目的 測試’如特性測試、功能測試及電源供應電流測試。 接著’在步驟1 〇 2中,熟知技術者會觀察每一晶圓的& ^ Two generals 'To discuss the problem of semiconductor manufacturing process, we can analyze it from the following items of data, including process parameter data, In line QC > materials' defect inspection (defect inspection), Sample test (samp and e test) data, wafer test (wafer test) data, and post-package test (final test) data. The wafer test data is a test value obtained by performing a feature refresh test, a function test (funct), and a power supply current test (IDDQ test) on the wafer. In the conventional technology, Please refer to FIG. 1. First, step 101 is performed. At this time, a skilled technician will perform a test of each wafer test item such as a characteristic test, a function test, and a power supply current test for each wafer. In Step 1 02, a skilled technician will observe the
第7頁 200410349 五、發明說明(2) 各項晶圓測試項目之結果,以便找出晶圓測試結果有偏差 的產品;如圖2所示,在一片晶圓2中會切割成複數個晶格 (d i e ),其中包括有複數個不良的晶格2 1 (以黑色顯0曰 示)以及複數個合格的晶格22 (以白色顯示),而圖2 g 表7F晶圓測试參數值的分布圖。 步驟103係由熟知技術者根據經驗,以及自步驟 所選出的異常產品之晶圓測試參數值分布圖,來列斷可处 有問題的製程站別,如微影製程、蝕刻製程、籬 σ % 程等。 _于植入製 最後,在步驟104中,熟知技術者係檢查步驟1〇3 斷之製程站別中的各機台,以便找出異常的機台。兴 言,依據圖2所不的分布圖,熟知技術者可以判 \而 的製程站別為某一金屬層的形成過程有問題,所以ΰ碭 尋進行此金屬層的製程站別,並檢查出異常的 f以搜 積機台、蝕刻機台等。 σ ’如沉 然而’由於在習知技術中乃是利用人為經驗 定分祈結果(步驟1〇3),所以最後分析出來之姓斷來決 雀度及可信度將有待商榷;再加上半導體勢造辈、°果的精 迭頻繁,導致前後期工程師之間的經驗傳承县之人士更 泣工程師能力有限、無法兼顧廠區所 作 故當半導體產品的測試結果發生異常時,工作狀態, 足夠的經驗快速且正確地判斷出是哪一個二::見得有 而可乾必須耗費許多時間來進行相關研究,甚題’因 ㈣誤的判斷’如此-來,不但降低製程的效率:能做 干' 增加生Page 7 200410349 V. Description of the invention (2) Results of various wafer test items in order to find products with discrepant wafer test results; as shown in FIG. 2, a plurality of crystals will be cut in a wafer 2 Lattice, which includes a plurality of defective lattices 2 1 (shown as 0 in black) and a plurality of qualified lattices 22 (shown in white). Figure 2g Table 7F Distribution. Step 103 is based on the experience of a skilled technician and the wafer test parameter value distribution chart of the abnormal product selected from the step to list the process stations that can be problematic, such as lithography, etching, and σ%. Cheng et al. _ In the implantation system Finally, in step 104, the skilled technician checks each machine in the process station broken in step 103 to find out the abnormal machine. Fortunately, according to the distribution diagram shown in FIG. 2, a skilled person can judge that the process station type is a problem in the formation process of a certain metal layer, so search for the process station for this metal layer and check out Anomalous f is the accumulation machine, etc. σ 'Ru Shen however' Since in the conventional technology, human experience is used to determine the score and pray for the result (step 103), the final analysis of the surname to determine the degree and credibility will be open to question; plus The semiconductor generation and the frequent convergence of results have led to the transmission of experience between engineers in the early and late stages. People in the county even cry that engineers have limited capabilities and cannot take into account the causes of the plant. When the test results of semiconductor products are abnormal, the working state is sufficient. Experience quickly and correctly determine which one is two :: Seeing something and doing it must take a lot of time to carry out related research, and even the question 'due to misjudgment' is so-come, not only reduce the efficiency of the process: can do '' Increase Health
200410349 五、發明說明(3) 產成本,還益 #、、、 因此,如 料發生異常時 的分析方法, (三)、【發明 有鑑於上 導體產品的晶 出是哪一個環 本發明之 晶圓測試項目 緣是,為 方法係用以分 複數個機台所 遇^晶圓測試 測試項目及其 測試項目、一 一實料庫中, 法及時改盖魂卜a α σ線上生產情形以提高良率。 何挺供一種能夠在半導 你千导體產扣的晶圓測試資 y f f 判斷出是哪-個環節出問題 疋田引、,導體製造技術的重要課題之一。 内容】 述課題,本 圓測試資料 卽出問題的 特徵係以良 相關之其他 達上述目的 析複數批分 製得,而每 項目之檢測 參數值、以 線上σσ質檢 本方法包括 將複數批產 發明之目的 發生異常時 晶圓測試參 率高的產品 製程項目記 ,依本發明 為提供一種 ,快速且正 數分析方法 為對照組並 錄於資料庫 之晶圓測試 別具有一批號之產品, 批產品中的每一片晶圓 以產生一晶圓測試參數值 能夠在半 確地判斷 Ο 將與各項 中。 參數分析 其係經過 係至少經 依據良率 高艮牛產品組及一低良率 依據高良 言二分析方式產 比對低良 一標準值,以 率產品組之 生一第一標 率產品組之 自低良率產 及與晶圓測 測項目以及 以下數個步 品區分為至 產品組; 各批產品的 準值; 各批產品的 品組之各批 圓 試項目相關的一樣品 一製程站別係儲存於 驟: 少二產品組,包括一 曰曰 晶圓測試參數值以統 晶圓測試參數值與第 產品之批號中刪除等200410349 V. Description of the invention (3) Production cost, also benefit # ,,,, and, therefore, the analysis method when the material is abnormal, (3), [Invention is based on which crystal of the conductor product is the crystal of the present invention The reason for the circle test project is that the method is used to divide the wafer test test items encountered in several machines and their test items, one by one in the material library, and to timely change the production situation on the abu σ a α σ line to improve the quality. rate. He Ting provided a kind of wafer test materials that can be used to deduct semiconductors from your semiconductors. You can determine which one is the problem. Putian Yin, one of the important topics of conductor manufacturing technology. Content] The characteristics of the problem described in the test data of this circle are obtained by analyzing multiple batches with good correlation and other purposes to achieve the above purpose, and the test parameter values of each item are tested by online σσ quality. This method includes the production of multiple batches. The purpose of the invention is to record a product process item with a high wafer test rate when an abnormality occurs. According to the present invention, a fast and positive analysis method is provided for the control group and the wafer test recorded in the database has a batch of products. Each wafer in the product to generate a wafer test parameter value can be determined with certainty. The parametric analysis is based on at least the yield ratio of the Gauguin beef product group and the low yield ratio of the high-yield-two analysis method. Low-yield production and the wafer test items and the following several steps are divided into product groups; the standard value of each batch of products; the batch of test items related to each batch of round test items of the product group of each batch Stored in the step: The second product group, including the wafer test parameter value, delete the wafer test parameter value and the batch number of the product, etc.
第9頁 200410349Page 9 200410349
笛1Π百 200410349 五、發明說明(5) 當判斷低良率產品組 :析動作;及當判斷低良 ,時’進行下列步驟:搜 晶格的各種電性測試值; 試規袼之晶格為目標晶格 布圖;將各晶圓之目標晶 圖進行疊圖動作;將重疊 出並定義為一目標晶圓; 之數目大於一第三標準值 中搜尋與晶圓測試項目相 承上所述,因依本發 良率高的產品為對照組並 他製程項目記錄於資料庫 題的製程站別,進而找出 少人為判斷的錯誤來提高 及時改善線上生產情形以 之剩餘批號 率產品組之 哥低良率產 疋義各晶圓 ,並取得各 格分布圖與 比率大於一 將低良率產 之產品的批 關之樣品測 明之晶圓測 將與各項晶 中,以便能 異常之機台 製程的效宁 提南良率。 的數量為零時,停止 剩餘批號的數量不為 品組之各晶圓之每一 上不合乎各種電性測 晶圓之一目標晶格分 晶圓測 第二標 品組中 號挑出 試項目 試參數 圓測試 夠正確 ,所以 、減少 試參數 準值之 包含目 ;及自 或製程 分析方 項目相 地判斷 能夠有 生產成 值分布 晶圓挑 標晶圓 資料庫 站別。 法係以 關之其 出有問 效地減本、並 (四)、【實施方式】 以下將參照相關圖 5阌試參數分析方法, 筑加以說明。 式 况明依本發明鲈技^ i ^ ^ 月車乂佳貫施例之 τ相同的元件 旰將U相同的參照 請參照圖3至圖5 ’圖中顯示本發明一丄 淚裎圖。此實施例係利用晶圓測試^ 一較佳實施例之 柝,並預計找出問題機台。 、 之結果進行分 200410349 五、發明說明(6) 如圖3所示,首先,在步驟3〇1中,依本發明較佳實施 例之晶圓測試參數分析方法係先搜尋數批產品之良率,然 後步驟302係將良率大於等於一預設值(如7〇% )之數批產 品設定為A組(高良率產品組)產品,例如包括批號1、 2、3、4、及5 (如步驟3 〇 3所示)·,以及將良率低於預設 值(如7 0 % )之數批產品設定為B組(低良率產品組)產 品’例如包括抵號6、7、8、9、及1〇 (如步驟3〇4所 示)。 其中,每一批(lot )產品係具有一批號(1〇t lumber),,且每批產品包括有託片晶圓,而每批產品係經 過複數逗製程的複數個機台。就一晶圓測試項目而言,例 如項目A ’、係對每片晶圓之每一個晶格(d丨e )進行多道電 性測試’亚獲得每一個晶格之電性測試參數值。對於每種 電性測試項目,皆設有一管制標準(c〇ntr〇1 spec )。當 一晶格之電性測試參數值合乎管制標準,則算是通過此電 性測試項目·’而當一晶格不合乎管制標準,則是無法通過 此電性^試項目’並且,在此一階段,此晶格之晶圓測試 項3A就算是不合格(faU )。是故,當一片晶圓之所有 连格穿經過晶圓測試項目A所包含之電性測試過程後,吾 人可以獲得此晶圓之晶圓測試參數分布圖,如圖2所示。 此外,熟知技術者可將此晶圓之晶圓測試項目A之合格晶 格數目,除以總晶格數目,獲得一數值,此數值稱為此晶 a ^晶圓測試參數值。而一批產品(〇ne 1〇t )之晶圓測 試參數值則是其包含之總晶圓數之晶圓測試參數值之平均Flute 1Π2004200410349 V. Description of the invention (5) When judging the low-yield product group: Analytical action; and when judging the low-yield, perform the following steps: search for various electrical test values of the crystal lattice; test the crystal lattice Is the target lattice layout; the target crystal map of each wafer is superimposed; the overlap is defined as a target wafer; the number is greater than a third standard value, and the search is consistent with the wafer test item As described above, because the product with a high yield rate is the control group and other process items are recorded in the database station of the process, furthermore, fewer human error judgments are found to improve the remaining batch rate product group in a timely manner to improve the online production situation. Brother yields low-yield wafers, and obtains grid patterns and ratios greater than those of a batch of samples that will yield low-yield products. The measured wafers will be tested with each crystal, so that the machine can work abnormally. The efficiency of the Taiwan manufacturing process will improve the yield of Nanan. When the number is zero, the number of remaining batches will not be one for each wafer in the group. It does not meet one of the various electrical test wafers. The target lattice is divided into wafers and the second standard group is selected. The test parameter circle test is correct enough, so reduce the inclusion of the test parameter standard value; and judge from the phase analysis of the project by the or process analysis that the production value distribution wafers can be targeted for the wafer database station. The legal system is effective in reducing costs, and (IV), [Implementation] The following is a description of the parameter analysis method with reference to Figure 5 below. According to the invention, according to the present invention, the perch technique ^ i ^ ^ The same components of the τ of the Jiaguan embodiment 旰 the same U is referred to Please refer to FIG. 3 to FIG. 5 ′. This embodiment uses wafer testing ^ one of the preferred embodiments, and is expected to find the problem machine. The results are divided into 200410349. 5. Description of the invention (6) As shown in FIG. 3, first, in step 3101, the method for analyzing the wafer test parameters according to the preferred embodiment of the present invention is to search for the goodness of several batches of products. Rate, and then step 302 is to set a number of batches of products with a yield greater than or equal to a preset value (such as 70%) as Group A (high-yield product group) products, for example, including batch numbers 1, 2, 3, 4, and 5 (As shown in step 3 〇3), and set several batches of products with a yield lower than a preset value (such as 70%) as Group B (low-yield product group) products. , 8, 9, and 10 (as shown in step 304). Among them, each batch of product has a batch number (10 tumber), and each batch of products includes a wafer wafer, and each batch of products is a plurality of machines through a plurality of teasing processes. As for a wafer test item, for example, item A 'is a multi-channel electrical test on each lattice (d 丨 e) of each wafer, and the electrical test parameter values of each lattice are obtained. For each type of electrical test item, there is a regulatory standard (conntro1 spec). When the electrical test parameter value of a crystal lattice meets the regulatory standard, it is considered to pass this electrical test item; 'When a crystal lattice does not comply with the regulatory standard, it cannot pass this electrical test item', and here At this stage, the wafer test item 3A of this lattice is not qualified (faU). Therefore, after all the grids of a wafer pass through the electrical test process included in wafer test item A, we can obtain the wafer test parameter distribution chart for this wafer, as shown in Figure 2. In addition, a person skilled in the art can divide the number of qualified lattices of wafer test item A of the wafer by the total number of lattices to obtain a value, which is called the crystal a ^ wafer test parameter value. The wafer test parameter value of a batch of products (One 10t) is the average of the wafer test parameter values of the total number of wafers it contains
200410349200410349
as 至=一批產品之良率,則是通過種種測試項目,包括 圓測試項目、線上品質檢測項目、樣品測試項目等 試後所獲得之產品優劣之代表值。 4 請參見圖3之步驟30 5,會先就A組產品之晶圓測試資 料進行統計分析’找出A組產品中具有代表性之晶圓測試 參數值KA。接著,參見步驟3Q6,在B組產品中,以Ka作為 標準,刪除B組產品中,晶圓測試參數值等於或優於&值 ^品,㈣’在此低良率產品組中,過濾掉通過晶圓測 試項目A (即其晶圓測試參數值優於Ka)之產品批號。之 ^ ’步驟307判斷在B組產品中剩下的批數是否為零,若為 零’則停止分析動作。若批數不為零,則連接至圖4,此 處需說明的是’當批數不為零時,代表這幾批糾組產品 的產品,其良率低之原因係可能與其晶圓測試項目 1不合格(fail )有關。 ^圖4步·i,當圖3之結果顯示出前述在b組產品 。剩餘的良率低之產品與晶圓測試項目“合格相關時, 莽自一經驗累積資料庫中去搜尋知 ^ &太 钗寸相關可用之資訊。根據以 ^ a ^ T ^ Π ^時,會根據其經驗判斷: * 3曰0測試項目A不合格時,可能與何種原因相關? 一,其答案可能是:「應該要去ϋ炉接〇 τ 方迫蹤樣品測試項目 ί samp le test)之某一個項目、十 σ w s 々甘 加s 或者應該要去追蹤線上 製程站別相關。」1故,此一經接判斷與哪-個 二秘累積資料庫係由資深工The yield of a batch of products is the representative value of the pros and cons of the products obtained after various tests including round test items, online quality test items, and sample test items. 4 Please refer to step 30 5 in Fig. 3. First, a statistical analysis will be performed on the wafer test data of Group A products' to find the representative wafer test parameter value KA in Group A products. Next, referring to step 3Q6, in Group B products, using Ka as the standard, delete the value of wafer test parameter equal to or better than the & value from Group B products, and filter in this low-yield product group. Drop the batch number of the product that passed the wafer test item A (that is, the wafer test parameter value is better than Ka). Step 307 determines whether the number of batches remaining in Group B is zero. If it is zero, the analysis operation is stopped. If the number of batches is not zero, then connect to Figure 4. What needs to be explained here is that when the number of batches is not zero, it means that the products of these batches of correction products have a low yield rate and may be tested with their wafers. Item 1 failed. ^ Figure 4 step i, when the result of Figure 3 shows the aforementioned products in group b. When the remaining low-yield products are relevant to the wafer test project, they must search the available information from an experience accumulation database for information. According to ^ a ^ T ^ Π ^, Will judge based on his experience: * What is the possible reason when test item A is unqualified on the 3rd? First, the answer may be: "Should go to the oven to pick up the sample test item of 〇τ forced trace sample samp le test ) One of the projects, ten σ ws 々 Ganjia s or should be related to the tracking of online process stations. "1 Therefore, once this is judged, which two secretarial accumulation database is a senior engineer
第13頁 200410349 五、發明說明(8) 程師將其經驗輸入此系統,用以提供一種電腦自動判 縱路徑的方向。當然,此經驗累積資料庫,亦可由電腦自 行更新,將後續問題追縱過程中所獲得之經驗自 = 此經驗累積資料庫中。 步驟402中,當此經驗累積資料庫顯示晶圓測試 與一樣品測試項目相關時,則進行步驟4〇3,以 :之同樣地,進行統計分析的動 作t出其具代表性之樣品測試參數值(可為一平均值 3?6後所㈣步叉404係以〜值為標’,將6組產品經過步驟 <3 06後所剩餘之逄^沾採口力丨」 〜/评 品批號刪除。麸後,牛趣试結果等於或優於^ Α值之產 S:,若為t v驟405判斷剩餘之產品批號是否為 格時,應追蹤之項曰貝料庫中搜尋當樣品測試項目不合 程站別(步驟40 8 ) 若經驗累積資料庫顯示應追蹤一製 料庫顯示應追蹤一,則連接至圖5之流程。若經驗累積資 接至步騾41〇。 線上品質檢測項目(步驟407 ),則連 參見步驟4〇9所一 積資料庫後,顯示曰不,此步驟係經過步驟4 0 1搜尋經驗累 相於步騍4 1 〇、巾曰曰圓測試項目Α與一線上品質檢測項目 益進行統計分析,、、’搜尋A組產品之線上品質測試資料, 宣(可為一平均值求出其具有代表性之線上品質測試參數 標準,將B組產品細)、^。接著,於步驟411中,以〜值為 剠試資料等於或傣4過步驟3 0 6後所剩餘之產品的線上品質 4 —後於A之產品批號刪除。再於步驟4 1 2Page 13 200410349 V. Description of Invention (8) The engineer inputs his experience into this system to provide a computer to automatically determine the direction of the longitudinal path. Of course, this experience accumulation database can also be updated by the computer, and the experience gained in the follow-up process can be obtained from this experience accumulation database. In step 402, when the experience accumulation database shows that the wafer test is related to a sample test item, step 403 is performed to: similarly, perform the statistical analysis action t to obtain its representative sample test parameters Value (may be an average value of 3-6 after the step fork 404 is marked with ~ value, the 6 groups of products after the step < 3 06 remaining remaining ^ ^ digging force 丨 ″ ~ / evaluation The batch number is deleted. After the bran, the result of the cattle test is equal to or better than ^ Α value: S: If it is tv step 405 to determine whether the remaining product batch number is a grid, you should search for the item in the shellfish library when the sample is tested If the project is out of range (step 40 8) If the experience accumulation database shows that a material warehouse should be tracked, the display should track one, then connect to the process in Figure 5. If the experience accumulation resource is connected to step 410. Online quality inspection project (Step 407), even after referring to the product database of step 409, it displays "No". This step is the result of the search experience in step 4 1 which is accumulated in step 4 1 0. The test item A and Statistical analysis of online quality inspection projects Product online quality test data, Xuan (may be an average value to find its representative online quality test parameter standards, fine group B products), ^. Then, in step 411, the value ~ is the test data. Equal to or equal to 4 The online quality of the product remaining after step 3 0 6 4 —The product lot number of A is deleted after that. Then in step 4 1 2
200410349 五、發明說明(9) 中’判斷剩餘之產品批號是否為零。若為零,則停止分析 動作;若不為零,則進行步驟4 1 3,以便自經驗累積資料 庫中搜尋當線上品質測試結果不合乎規袼時,應追縱哪一 個製程站別(步驟4 1 4 ),然後連接至圖5之流^。 參見步驟41 5,此步驟係經過步驟401搜尋經驗累積資 料庫後’顯示晶圓測試項目A不合格時,應追縱之項目為 一製程站別,此時連接至圖5之流程以進行後續步驟。200410349 V. In the description of the invention (9), ′ judge whether the batch number of the remaining product is zero. If it is zero, stop the analysis. If it is not zero, go to step 4 1 3 to search from the experience accumulation database. When the online quality test result is not in compliance, which process station should be tracked (step 4 1 4), and then connected to the stream of Figure 5 ^. Refer to step 41.5. This step is after searching the accumulated experience database in step 401. 'If the wafer test item A is unqualified, the item to be pursued is a process station. At this time, it is connected to the process of FIG. 5 for follow-up. step.
請參照圖5所示,於步驟501中,其係先搜尋被追蹤之 製程站別係包括哪些機台,例如E 1,E 2,E 3 ···。接著, 步驟5 0 2係计鼻B組產品中’經過步驟3 0 6、步驟4 〇 4或步驟 411的刪除動作後,剩餘產品批號之產品經過此製程站別 之該等機台的機率。另外,步驟503係計算A組產品經過此 製程站別之該等機台的機率。然後,於步驟5 〇 4中,利用 共通性分析手法,找出經過步驟3 0 6、步驟4 0 4或步驟4 11 的删除動作後,B組產品之剩餘產品批號的產品經過機率 最高之機台。由步驟504所求得的這些Β組產品剩餘產品批 號之產品經過機率最南之機台,就是依本發明較佳實施例 之晶圓測試參數分析方法所分析出的可能有問題之機台。Please refer to FIG. 5. In step 501, it first searches which machines are included in the tracked process station type, such as E 1, E 2, E 3 ···. Next, in step 502 of the Nose B group products, after the deletion of step 306, step 404, or step 411, the probability that the product with the remaining product lot number passes through the machines of this process station. In addition, step 503 calculates the probability that the products of Group A will pass through the machines of this process station. Then, in step 504, the common analysis method is used to find the product with the highest probability of passing the remaining product batch number of group B products after the deletion of step 3 06, step 4 04, or step 4 11 station. The machine with the lowest probability of passing the remaining product lot numbers of these Group B products obtained in step 504 is the machine that may have a problem that is analyzed according to the wafer test parameter analysis method of the preferred embodiment of the present invention.
另外’請參見圖6至圖1〇所示,圖中顯示依本發明第 二較佳實施例之晶圓測試參數分析方法的流程圖。由圖6 可看出,自步驟6 0 1至步驟6 〇 7係與圖3之流程相同,故不 再重複贅述,其中,若步驟6 〇 7判斷在Β組產品中剩下的批 數不為零時,則連接至圖7。此第二較佳實施例係用以分 析另一晶圓測試項目,例如晶圓測試項目Β之方法。In addition, please refer to FIG. 6 to FIG. 10, which show a flowchart of a method for analyzing a wafer test parameter according to a second preferred embodiment of the present invention. It can be seen from FIG. 6 that the process from step 601 to step 〇7 is the same as that of FIG. 3, so it will not be repeated, and if step 〇7 determines that the number of batches remaining in group B is not When zero, connect to Figure 7. This second preferred embodiment is a method for analyzing another wafer test item, such as wafer test item B.
第15頁 200410349 五、發明說明(ίο) 參見圖7,步驟7 0 1係搜尋經過步驟6 〇 β的删除動作後B 組產品中剩餘批號之產品中,以取得所搜尋之每批產品的 每一片晶圓上每個晶格之複數種電性測試結果。在本實施 例中,有些電性測試項目係依層別來進行測試,是故,可 獲得各層別之電性測試參數值。接著,於步驟7 0 2中,將 不合測試規格之晶格定義為目標晶格n aπ,同時可獲得每 片晶圓之目標晶格分布圖8,如圖8所示,其中,目標晶格 8 1以n aπ表示,而其他晶格8 2以白色表示;禽注意者,因 有複數種電性測試項目、複數個層別,故每片晶圓將會有 複數張目標晶格分布圖,換言之,各晶圓的每一層別都會 具有一對應之目標晶格分布圖。接著,步驟7 〇 3係將每片 晶圓之目標晶格分布圖(如圖8所示)與其晶圓測試參數 值分布圖(如圖2所示)進行疊圖動作。 參見步驟7 0 4,其係判斷每片晶圓之目標晶格分布圖 與晶圓測試參數值分布圖的重疊比率是否大於一預設值, 例如3 0 %。若否’則此片晶圓不做標記(步驟7 〇 5 ):若 疋,則將此片晶圓標記為目標晶圓,,ζ I,(步驟7 〇 6 )。接 著’步驟7 0 7判斷每批產品中所包含之目標晶圓的數量是 否大於等於其總片數之一定比例,例如大於等於5〇%,以 上。若否,則進行步驟7 08以刪除此產品批號;若是,則 保留此產品批號(步驟7〇9),並接著進行連接至圖9之流 程。 參見圖9所不之步驟9 〇 1,依本發明第二較佳實施例之 晶圓測试參數分析方法係自經驗累積資料庫中搜尋與晶圓Page 15 200410349 V. Description of Invention (ίο) Refer to FIG. 7. Step 7 0 1 searches for the remaining batch number of products in Group B after the deletion of step 6 〇β to obtain each of the batches of products searched. Multiple electrical test results for each lattice on a wafer. In this embodiment, some electrical test items are tested on a level-by-level basis, so the electrical test parameter values for each level can be obtained. Next, in step 702, the lattice that does not meet the test specifications is defined as the target lattice n aπ, and the target lattice distribution of each wafer is obtained as shown in FIG. 8, as shown in FIG. 8, where the target lattice 8 1 is represented by n aπ, and the other lattices 8 2 are represented by white. For poultry watchers, because there are multiple electrical test items and multiple layers, each wafer will have multiple target lattice distribution maps. In other words, each layer of each wafer will have a corresponding target lattice distribution map. Next, in step 703, the target lattice distribution map of each wafer (as shown in FIG. 8) and the wafer test parameter value distribution map (as shown in FIG. 2) are superimposed. Refer to step 704, which is to determine whether the overlap ratio of the target lattice distribution map of each wafer and the wafer test parameter value distribution map is greater than a preset value, such as 30%. If not, then this wafer is not marked (step 705): If 疋, then this wafer is marked as the target wafer, ζ I, (step 706). Following step '7 7', it is determined whether the number of target wafers included in each batch is greater than or equal to a certain percentage of the total number of wafers, such as 50% or more. If not, go to step 7 08 to delete the product lot number; if yes, keep the product lot number (step 709), and then proceed to the process of connecting to FIG. 9. Referring to step 9 in FIG. 9, the method for analyzing wafer test parameters according to the second preferred embodiment of the present invention is to search for wafers from the experience accumulation database.
第16頁 200410349Page 16 200410349
五、發明說明(11) 測試項目B相關之樣〇也丨4 中,當此經驗累積資斜、:項目或製程站別。纟步驟9〇 2 試項目相關時,則:U顯示晶圓測試項目Β與-樣品測 品之樣品測試資料,遗ζ,9G3/而步驟903會搜尋Α組產 如平均值〜。接著,於本仃統計分析以求出一代表值,例 將B組產品經過步帮7〇7;德^ 9 04中’卩平均值〜為標準, 果等於或優於^值之產/:保/之產品批號的冑品測試結 n m ^ ^ ^ ® qn4 產σ〇批號刪除。然後在步驟90 5中, 判斷經過步驟90 4之删除動作 :。若為零,m停止分析動作;若不為;之”進疋否為 906,以便自經驗累稽眘祖庙由; 订乂驟 a系積貝料庫中搜寻與此樣品測試項目相 關:製程站別。當經驗累積資料庫顯示此樣品測試項目盘 一=程站別相關時(步糊7),則進行連接至圖1〇所示、 之成程。 ^另外,如步驟90 9所示,當經過步驟901搜尋經驗累積 資料庫後,顯示晶圓測試項目B與一製程站別相關時,’則 進行連接至圖10所示之流程。 ' 請參照圖1 0所示,其分析流程(步驟s 〇丨〜s 〇 4 )係與 圖5之步騍50卜5 04相同,故此處不再贅述。因此,依、圖、 6、圖了、圖9及圖1 〇之分析流程,依本發明第二較佳實@施 封之晶圓測試參數分析方法能夠搜尋出可能有問題之機V. Description of the invention (11) Relevant test item B is also 〇4, when this experience accumulates capital, project or process station type.纟 When the test item in step 902 is related, then: U displays the sample test data of wafer test item B and-sample test, leaving ζ, 9G3 /, and step 903 will search for group A production such as the average value ~. Next, the statistical analysis is performed in this paper to find a representative value. For example, the products of Group B are processed through the step 704; Germany ^ 9 04, and the average value of 卩 is used as the standard. If the value is equal to or better than the value of ^: Counterfeit product test results of the product number of the warranty / nm ^ ^ ^ ® qn4 Production σ〇 The batch number is deleted. Then, in step 905, it is judged that the deletion action has passed through step 904 :. If it is zero, m stops the analysis; if not, it is 906, so that you can learn from the experience of the ancestor of Shenzu Temple; Order step A is searched in the jade database, which is related to this sample test item: process station type .When the experience accumulation database shows that this sample test item Pan 1 = the process station type is related (step 7), then the connection is made to the process shown in Figure 10. ^ In addition, as shown in step 90 9 when After searching the accumulated experience database after step 901, when it is shown that the wafer test item B is related to a process station, 'the connection is performed to the process shown in FIG. 10.' Please refer to FIG. 10 for the analysis process (step s 〇 丨 ~ s 〇4) are the same as the steps 骒 50 and 504 in Fig. 5, so they will not be repeated here. Therefore, the analysis process according to Fig. 6, Fig. 6, Fig. 9 and Fig. 10, according to this text. Invented the second best practice @ 施 封 's wafer test parameter analysis method can search for possible problems
最後’請參照圖11與圖1 2所示,其係顯示依本發明第 三較诖實施例之晶圓測試參數分析方法。 X 如圖11所示,其中步驟S:n〜S17係與圖3所示之步驟Finally, please refer to FIG. 11 and FIG. 12, which show a method for analyzing wafer test parameters according to the third embodiment of the present invention. X is shown in FIG. 11, where steps S: n to S17 are the steps shown in FIG. 3
200410349 五、發明說明(12) 301〜30 7相同,故此處不再重複敘述。接著,在步驟 中,其係搜尋經過步驟S16後所剩餘之每批產品是否具有 缺陷(d—efect );在本實施例中,此搜尋步驟係針對每批 產品之每片晶圓進行搜尋,若一批產品中包含一片以上之 具有缺陷的晶® ’則判定此批產品為具有缺陷之產品。若 签若是,則進行步驟si9 ’挑出具有缺陷 缺匕丄於步驟s2°中找出具有缺陷之晶圓的 有缺:,二此:者,一片晶圓可能於不同的層別皆具 有缺:則此時一片晶圓會具有一張以上之缺陷分布圖。 綴S20所朽於步驟切中,其係利用疊圖之方式比對由步 八布圍,# 4之^缺陷分布圖與該片晶圓之晶圓測試參數值 刀 ,叶算出二分布圖的重疊比率。缺後,於步驟 S22中判斷重聂比率县不丄千’、、、俊於步驟 -^目,丨故且羊否大於等於一預設值,例如為5 0 %, :否,=略:此層,卜當所有層別皆略過時停 疋,則進仃步驟S26。 時i參見步驟323,其係計算每片晶圓各層別之缺 斗”;^步驟S24中,將步·23所算*之缺陷數目除 :二Ί ! 5晶圓測試規格之晶格* (dies ),以求得- :二ίΐ,於步驟S25中,判斷步驟S24所求得之比值是 預?值’〜大於等於5°% ;若否,則略過晶 3之此層別,若是,則進行步驟S 2 6。 & :驟S26中’其係將經過上述步驟分析後之產品批 二;:貝料及缺陷數目等資料挑出,以便之後進行連接 一圖1-所不之流程。200410349 V. Description of the invention (12) 301 ~ 30 7 is the same, so it will not be repeated here. Next, in the step, it is to search whether each batch of products remaining after step S16 has a defect (d-efect); in this embodiment, this search step is to search for each wafer of each batch of products, If a batch of products contains more than one defective wafer®, the batch is judged to be defective. If yes, go to step si9 'to pick out the defective wafers in step s2 ° to find out the defects of the wafers with defects: or two: or, a wafer may have defects in different layers. : At this time, a wafer will have more than one defect distribution map. The S20 is succumbed to the step cut. It uses a stacking method to compare the defect distribution map of # 4 and the wafer test parameter value of # 4, and calculates the overlap of the two distribution maps. ratio. After the absence, it is judged in step S22 that the county is not inferior to Qian'an, it is better than the step-^ 目, and whether the sheep is greater than or equal to a preset value, such as 50%,: No, = slightly: In this layer, if all the layers are skipped, the process stops, and the process proceeds to step S26. Time i refers to step 323, which calculates the number of defects in each layer of each wafer "; ^ In step S24, divide the number of defects calculated in step · 23 *: 2Ί! 5 wafer test specification lattice * ( dies) to obtain-: two 二, in step S25, it is judged that the ratio obtained in step S24 is a pre-value '~ greater than or equal to 5 °%; if not, skip this layer of crystal 3, if it is Then, proceed to step S 2 6. &: In step S26, 'it is the second batch of the product after the analysis of the above steps ;: the shell material and the number of defects are selected, so that the process can be connected as shown in Figure 1-not .
200410349 五、發明說明(13) 請參見圖12所示,步驟S 3 1係根據圖1 2之步驟$ 2 6所挑 出之層別,自經驗累積資料庫中搜尋與此層別相關之製程 站別,而步驟S32係顯示經過步驟S3 1之搜尋後,應追蹤之 項目為一製程站別。由圖12中可知,步驟S33〜S36係與圖$ 之步驟5(Π〜5 04流程相同,故此處不再重複敘述。因此, 由步驟S31至步驟S36之分析流程,依本發明第二較佳實施 例之晶圓測試參數分析方法能夠搜尋出可能有問題之機 台0 根據圖11之步驟S26所獲得之缺陷數 同時 圖 如 12所示之步驟S37會進行統計分析之動作,'其係求出一 表值來作為該層別之缺陷數目管制標準。同時,於牛\ S38中,根據此-缺陷數目管制標準,依本發明較佳= 例之晶圓㈣參數分析方法能夠在後續 此只也 中,預測此產品之良率。 j <產品 綜上所述,由於依本發明之晶圓測試參數分 以統=分析及共通性分析手法分析晶圓測試參 Μ糸 而正確地判斷出有問題的製程站別,進而鬥枓,進 台,所以能夠有效地減少人為判斷的錯誤來續的機 玄、減少生產成本、並及時改盖線上 门I祆的坆 圭: 吋0踝上生產情形以提高良 以上所述僅為舉例性,而非為限制性 本發明之精神與範疇,而對其進行之等效修 2未脫離 應包含於後附之申請專利範圍中。 〆5支更’ %200410349 V. Description of the invention (13) Please refer to FIG. 12, step S 31 is the layer selected according to step $ 2 6 of FIG. 12, and search the process related to this layer from the experience accumulation database. Station type, and step S32 shows that after searching in step S31, the item to be tracked is a process station type. It can be known from FIG. 12 that steps S33 to S36 are the same as steps 5 (Π to 504) in FIG. $, So they will not be repeated here. Therefore, the analysis flow from step S31 to step S36 is according to the second comparison of the present invention. The wafer test parameter analysis method of the preferred embodiment can search for machines that may have problems. 0 The number of defects obtained according to step S26 in FIG. 11 and the step S37 shown in FIG. 12 will perform statistical analysis. Calculate a table value as the standard for the number of defects in this layer. At the same time, in Niu \ S38, according to this-the number of defects control standard, according to the present invention, the method of analyzing the parameters of wafers and parameters can be performed here. It only predicts the yield of this product. J < In summary of the product, the wafer test parameters according to the present invention are divided into unified = analysis and common analysis methods to analyze the wafer test parameters. If there is a problem in the process station, and then enter the stage, it can effectively reduce the mistakes of human judgment to continue the machine, reduce production costs, and timely cover the door of the online door I: 坆 0 ankle Production situation to mention Gao Liang The above description is only exemplary, rather than limiting the spirit and scope of the present invention, and equivalent modifications to it should be included in the scope of patents attached below. 〆5 支 更 ’%
第19頁 200410349 圖式簡單說明 (五)、【圖式簡單說明】 圖1為一流程圖,顯示習知晶圓測試參數分析方法的 流程; 圖2為一不意圖’顯不晶圓之晶圓測試參數值分布 圖; 圖3為一流程圖,顯示依本發明第一較佳實施例之晶 圓測試參數分析方法的流程; 圖4為一流程圖,顯示延續圖3所示之流程圖的流程; 圖5為一流程圖,顯示延續圖4所示之流程圖的流程; 圖6為一流程圖,顯示依本發明第二較佳實施例之晶 圓測試參數分析方法的流程; 圖7為一流程圖,顯示延續圖6所示之流程圖的流程; 圖8為^一不意圖’顯不晶圓之目標晶格分布圖, 圖9為一流程圖,顯示延續圖7所示之流程圖的流程; 圖1 0為一流程圖,顯示延續圖9所示之流程圖的流 程; 圖11為一流程圖,顯示依本發明第三較佳實施例之晶 圓測試參數分析方法的流程;以及 圖1 2為一流程圖,顯示延續圖1 1所示之流程圖的流 程。 元件符號說明: 101-104 習知晶圓測試參數分析方法的流程 2 晶圓Page 19, 200410349 Brief description of the drawings (five), [Simplified description of the drawings] Figure 1 is a flowchart showing the flow of the conventional wafer test parameter analysis method; Figure 2 is a wafer test with no intention to show the wafer Parameter value distribution diagram; FIG. 3 is a flowchart showing the flow of the wafer test parameter analysis method according to the first preferred embodiment of the present invention; FIG. 4 is a flowchart showing the flow continuing the flowchart shown in FIG. 3 Figure 5 is a flowchart showing a flow continuing from the flowchart shown in Figure 4; Figure 6 is a flowchart showing the flow of a wafer test parameter analysis method according to a second preferred embodiment of the present invention; Figure 7 is A flowchart showing the flow of continuation of the flowchart shown in FIG. 6; FIG. 8 is a diagram showing the target lattice distribution of a wafer that is not intended to be displayed, and FIG. 9 is a flow chart showing the continuation of the flow shown in FIG. FIG. 10 is a flowchart showing a flow continuing from the flowchart shown in FIG. 9; FIG. 11 is a flowchart showing a flow of a wafer test parameter analysis method according to a third preferred embodiment of the present invention ; And Figure 12 is a flowchart showing the delay 11 flowchart shown in the flow chart of FIG. Description of component symbols: 101-104 The process of the conventional wafer test parameter analysis method 2 Wafer
第20頁 200410349 圖式簡單說明 21 不良的晶格 22 合格的晶格 3(H 〜307 本發明第一較佳實施例之晶圓測試參數分析方 法的流程 4(Π 〜41 5 延續步驟3 0 7之流程 501 〜504 延續步驟408、步驟414或步驟415之流程 6(Π 〜607 本發明第二較佳實施例之晶圓測試參數分析方 法的流程 701 〜709 延續步驟6 0 7之流程 8 目標晶格分布圖 81 目標晶格 82 其他晶格 9(Π 〜908 延續步驟7 0 9之流程 S01 〜S04 延續步驟9 0 7或步驟9 0 8之流程 S11〜S26 本發明第三較佳實施例之晶圓測試參數分析方 法的流程 S31 〜S38 延續步驟S26之流程Page 20 200410349 Brief description of the diagram 21 Defective lattice 22 Qualified lattice 3 (H ~ 307 Flow chart 4 of the wafer test parameter analysis method of the first preferred embodiment of the present invention 4 (Π ~ 41 5 Continue to step 3 0 Flow 501 to 504 of 7 Continue to flow 6 of step 408, step 414, or step 415 (Π to 607 Flow 701 to 709 of the wafer parameter analysis method of the second preferred embodiment of the present invention Continue to flow 8 of step 6 0 7 Target Lattice Distribution Map 81 Target Lattice 82 Other Lattices 9 (Π ~ 908 Continuing Process S01 ~ S04 of Step 7 0 9 Continuing Process S11 ~ S26 of Step 9 0 7 or Step 9 0 8 The third preferred implementation of the present invention The flow of the method for analyzing the test parameters of the wafer S31 to S38 is continued from the flow of step S26
第21頁Page 21
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW91135096A TWI234217B (en) | 2002-12-03 | 2002-12-03 | Method for analyzing wafer test parameters |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW91135096A TWI234217B (en) | 2002-12-03 | 2002-12-03 | Method for analyzing wafer test parameters |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200410349A true TW200410349A (en) | 2004-06-16 |
TWI234217B TWI234217B (en) | 2005-06-11 |
Family
ID=36592771
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW91135096A TWI234217B (en) | 2002-12-03 | 2002-12-03 | Method for analyzing wafer test parameters |
Country Status (1)
Country | Link |
---|---|
TW (1) | TWI234217B (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8756028B2 (en) | 2011-06-22 | 2014-06-17 | Inotera Memories, Inc. | Fault detection method of semiconductor manufacturing processes and system architecture thereof |
CN110688546A (en) * | 2019-09-25 | 2020-01-14 | 上海华力集成电路制造有限公司 | Production data analysis method and analysis system |
CN111128779A (en) * | 2019-12-26 | 2020-05-08 | 上海华虹宏力半导体制造有限公司 | Wafer testing method |
CN111257715A (en) * | 2020-02-19 | 2020-06-09 | 上海韦尔半导体股份有限公司 | Wafer testing method and device |
CN113935652A (en) * | 2021-10-29 | 2022-01-14 | 上海华力微电子有限公司 | Abnormal product data analysis method and system |
-
2002
- 2002-12-03 TW TW91135096A patent/TWI234217B/en not_active IP Right Cessation
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8756028B2 (en) | 2011-06-22 | 2014-06-17 | Inotera Memories, Inc. | Fault detection method of semiconductor manufacturing processes and system architecture thereof |
TWI447605B (en) * | 2011-06-22 | 2014-08-01 | Inotera Memories Inc | Method of fault detection classification for semiconductor process and system structure thereby |
CN110688546A (en) * | 2019-09-25 | 2020-01-14 | 上海华力集成电路制造有限公司 | Production data analysis method and analysis system |
CN110688546B (en) * | 2019-09-25 | 2023-08-11 | 上海华力集成电路制造有限公司 | Production data analysis method and analysis system |
CN111128779A (en) * | 2019-12-26 | 2020-05-08 | 上海华虹宏力半导体制造有限公司 | Wafer testing method |
CN111257715A (en) * | 2020-02-19 | 2020-06-09 | 上海韦尔半导体股份有限公司 | Wafer testing method and device |
CN113935652A (en) * | 2021-10-29 | 2022-01-14 | 上海华力微电子有限公司 | Abnormal product data analysis method and system |
Also Published As
Publication number | Publication date |
---|---|
TWI234217B (en) | 2005-06-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7962864B2 (en) | Stage yield prediction | |
JP4728968B2 (en) | Data analysis method and apparatus | |
TWI631351B (en) | System and method for the automatic determination of critical parametric electrical test parameters for inline yield monitoring | |
KR20060026072A (en) | Methods and apparatus for data analysis | |
CN104021248B (en) | A kind of airborne machinery product FMECA analysis methods | |
JP5080526B2 (en) | Method and apparatus for data analysis | |
CN113191399B (en) | Method for improving yield of semiconductor chips based on machine learning classifier | |
JP2003506900A (en) | Method and apparatus for characterizing a semiconductor device | |
CN109447108A (en) | A kind of integrated circuit test data convergence analysis method | |
US7340352B2 (en) | Inspecting method, inspecting apparatus, and method of manufacturing semiconductor device | |
TW200411508A (en) | Method for analyzing in-line QC parameters | |
TW200410349A (en) | Method for analyzing wafer test parameters | |
Jiang et al. | Semiconductor manufacturing final test yield optimization and wafer acceptance test parameter inverse design using multi-objective optimization algorithms | |
TW569373B (en) | Method for analyzing defect inspection parameters | |
US20230377132A1 (en) | Wafer Bin Map Based Root Cause Analysis | |
WO2021076609A1 (en) | Collaborative learning model for semiconductor applications | |
US20120316803A1 (en) | Semiconductor test data analysis system | |
US6174738B1 (en) | Critical area cost disposition feedback system | |
US20230052392A1 (en) | Process abnormality identification using measurement violation analysis | |
Kim et al. | Package yield enhancement using machine learning in semiconductor manufacturing | |
CN115713209A (en) | Method for evaluating product yield | |
US7035770B2 (en) | Fuzzy reasoning model for semiconductor process fault detection using wafer acceptance test data | |
JPH10107111A (en) | Manufacturing method of semiconductor device | |
US20040193381A1 (en) | Method for analyzing wafer test parameters | |
US8160830B2 (en) | Method of yield management for semiconductor manufacture and apparatus thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MK4A | Expiration of patent term of an invention patent |