200304281 (1) 玖、發明說明 發明所屬的技術領域 本發明與信號的相位偵測有關，更明確地說，將本地 振盪器相鎖到進入之具有內嵌時鐘信號的資料流。 先前技術 在很多高速通信的應用中，諸如同步光學網路 (SONET)通信標準，收發機所接收之進入的資料信號中， 都包含有內嵌的時鐘信號。時鐘恢復單元（CRU)或時鐘與 資料恢復（CDR)電路恢復嵌於進入之資料信號內的時鐘信 號。CRU使用此恢復的時鐘信號將本地振盪器鎖定於進 入資料信號的邊緣，本地振盪器被訓練並被同步到所恢復 之時鐘信號的頻率。接著，本地振盪器用來產生本地時鐘 信號以處理及恢復時序（re-time)所接收之進入信號內的資 料。 由於本地振盪器的時鐘信號是用來從進入的信號中擷 取資料，很重要一點的是本地振盪器要被保持在參考頻率 的倍數；否則，系統就無法正確地將進入的信號解碼。因 此，在建構局速通信網路時，關鍵工作之一是使接收機的 時鐘精確地對準嵌在進入之資料內的時鐘信號。精確地控 制接收機之本地時鐘的相位與頻率是典型的要求。典型 上’時鐘的對準是使用控制相位的回授系統執行，稱爲鎖 相迴路（PLL)。構建此類系統的方法有數種，例如使用電 壓控制的振盪器，電流控制的振盪器，或其它型式控制的 -4 - (2) (2)200304281 振盪器。 圖1顯示其中一款cRU的簡單方塊圖，用以對進入 的資料信號執行恢復、恢復時序、及鎖定偵測。此CRU 中主要是鎖相迴路（PLL)，其中包含數位頻率及相位偵測 器（DFPD) 105 ’如習知的數位式自動正交相位控制電路， 它可從進入的資料中擷取資訊，且不需要外部時鐘參考即 可獲得頻率。進入的資料在DFPD 1 05內與內部電壓控制 振盪器（VCO)比較。它的輸出在濾波器]10中被微分地濾 波，並施加到振盪器1 1 5。D型正反器1 2 5使用相位相反 的 VCO時鐘輸出將資料恢復時序。此外，鎖定偵測器 ]30比較參考輸入（REF)與VCO 115(例如除以16)，以決 定本地振盪器Π 5正在產生的時鐘信號是否與嵌在進入之 信號中的時鐘信號對準。鎖定偵測器1 3 0警告電路這類問 題以使電路可以採取適當的動作。 在延遲鎖定回路（DLL)中，相位偵測器也是重要組 件。在DLL中，相位偵測器是用來鎖定進入的資料信號 以同步正交的半時鐘。在此情況，本地振盪器不被控制， 更正確地說是資料延遲。 在高頻中操作的積體電路很難實施DFPD，這是因爲 脈波最小寬度與用以組成電路之閘與電晶體的傳播延遲在 操作頻率中出現上邊界。很多使本地振盪器鎖定進入之信 號資料的習知方法需要使用大量組件且相當複雜。此外， 這些方法的操作相對較慢，因此限制了高速網路所能達到 的性能。 -5- (3) (3)200304281 在以下列舉的文獻中曾提出DFPD的各種設計，例如 Gutierrez & Kong 的“ Unaided 2.5Gb/s Silicon Bipolar Clock and Data Recovery IC” Proceedings of the IEEE Radio Frequency Integrated Circuits Symposium, 1 99 8 ! Mullner 的 “A 20Gbit/s parallel phase detector and demultiplexer circuit in a production silicon bipolar technology with fTdSGHz”，IEEE BCTM 2.2, 1996 ; Savoj & Razavi，“Design of Half-Rate Clock and Data Recovery Circuits for Optical Communications Systems，” DAC 2001， Las Vegas， Nevada， USA ; Wurzer 等人，“ 40Gb/s Integrated Clock and Data Recovery Circuit in a Silicon200304281 (1) (ii) Description of the invention The technical field to which the invention belongs The present invention relates to the phase detection of signals. More specifically, the local oscillator is phase locked to the incoming data stream with an embedded clock signal. Prior art In many high-speed communication applications, such as the synchronous optical network (SONET) communication standard, the incoming data signal received by the transceiver contains an embedded clock signal. A clock recovery unit (CRU) or clock and data recovery (CDR) circuit recovers the clock signal embedded in the incoming data signal. The CRU uses this recovered clock signal to lock the local oscillator to the edge of the incoming data signal. The local oscillator is trained and synchronized to the frequency of the recovered clock signal. The local oscillator is then used to generate a local clock signal to process and recover the data in the incoming signal received at the re-time. Since the clock signal of the local oscillator is used to retrieve data from the incoming signal, it is important that the local oscillator is kept at a multiple of the reference frequency; otherwise, the system cannot correctly decode the incoming signal. Therefore, when constructing a local-speed communication network, one of the key tasks is to precisely align the receiver's clock with the clock signal embedded in the incoming data. It is a typical requirement to precisely control the phase and frequency of the receiver's local clock. The alignment of the clock is typically performed using a phase-controlled feedback system called a phase-locked loop (PLL). There are several ways to construct such a system, such as using a voltage controlled oscillator, a current controlled oscillator, or other types of controlled -4-(2) (2) 200304281 oscillators. Figure 1 shows a simple block diagram of one of the cRUs used to perform recovery, recovery timing, and lock detection on incoming data signals. This CRU is mainly a phase-locked loop (PLL), which contains a digital frequency and phase detector (DFPD) 105 'as a conventional digital automatic quadrature phase control circuit, it can extract information from the incoming data, No external clock reference is required to obtain the frequency. The entered data is compared with the internal voltage controlled oscillator (VCO) in DFPD 105. Its output is differentially filtered in filter 10 and applied to oscillator 1 1 5. The D-type flip-flop 1 2 5 uses the VCO clock output of the opposite phase to restore the data timing. In addition, the lock detector] 30 compares the reference input (REF) with the VCO 115 (for example, divided by 16) to determine whether the clock signal being generated by the local oscillator UI 5 is aligned with the clock signal embedded in the incoming signal. The lock detector 130 warns of problems with the circuit so that the circuit can take appropriate action. The phase detector is also an important component in a delay locked loop (DLL). In a DLL, a phase detector is used to lock incoming data signals to synchronize quadrature half clocks. In this case, the local oscillator is not controlled, more precisely the data delay. It is difficult to implement DFPD for integrated circuits operating at high frequencies because the minimum pulse wave width and the propagation delay of the gates and transistors used to form the circuit have upper bounds on the operating frequency. Many known methods of locking local oscillators into incoming signal material require a large number of components and are quite complex. In addition, these methods operate relatively slowly, thus limiting the performance that high-speed networks can achieve. -5- (3) (3) 200304281 Various designs of DFPD have been proposed in the documents listed below, such as "Unaided 2.5Gb / s Silicon Bipolar Clock and Data Recovery IC" Proceedings of the IEEE Radio Frequency Integrated by Gutierrez & Kong Circuits Symposium, 1 99 8! Mullner's "A 20Gbit / s parallel phase detector and demultiplexer circuit in a production silicon bipolar technology with fTdSGHz", IEEE BCTM 2.2, 1996; Savoj & Razavi, "Design of Half-Rate Clock and Data Recovery Circuits for Optical Communications Systems, "DAC 2001, Las Vegas, Nevada, USA; Wurzer et al.," 40Gb / s Integrated Clock and Data Recovery Circuit in a Silicon
Bipolar Technology，，，IEEE BCTM 8.1， 1998 :以 及， P ottb acker 等 人， “A S i Bipolar Phase and F r e q uency Detect or IC for Clock Extraction up to 8GB/s，，， IEEE Journal of s olid- State Circuit， Vo 1.2 7, No. 12, Dec. 1 9 92。不過，以上所有文獻所描述的相位偵測器沒有一款 具有本發明全部的優點。例如，其中某些是在光學應用的 極高時鐘頻率中操作，因此速率受到極大限制。其它某些 的本地振盪器是用於對進入的資料取樣，致使相位偵測器 對資料的樣式（即1或0的長字串）很敏感。由於此敏感 度，相位偵測器不需要一直輸出正確的方向以修正相位。 最後一點，並非全部都是吾人所想要的開關式相位偵測器 (bang-bang phase detector)，因爲它們的設計最簡單。 因此，吾人需要一種用於CRU的相位偵測器，它允 (4) (4)200304281 許本地振盪器在半時鐘頻率操作，使用所接收的時鐘信號 取樣本地振盪器，並決定任何需要修正的符號（即方向）。 發明內容 本文描述一種半速率開關式相位偵測器，用以偵測進 入的資料信號相對於本地時鐘信號的相位，做爲本地時鐘 信號鎖定進入之資料信號的方向。在較佳實施例中，本地 時鐘信號的頻率大約是資料信號的一半。第一相位偵測模 組使用資料信號取樣本地時鐘信號，以及，第二相位偵測 模組使用資料信號取樣相移的本地時鐘信號。極性選擇模 組根據所取樣的本地時鐘信號與相移的本地時鐘信號決定 資料信號相對於本地時鐘信號的相位，並根據決定的結果 輸出一方向信號。此輸出的方向信號例如供本地振盪器用 來調整本地時鐘信號，以將本地時鐘信號鎖定到進入的資 料信號。在本發明的其它實施例中，相位偵測器是使用正 反器' 邏輯聞、及/或其它標準邏輯及電路組件的各種不 同配置實施。在本發明的一態樣中，極性選擇模組是使用 三穩AND閘實施。 #發B月的優點是半速率開關式相位偵測器非常強固， 因爲是使用進入的資料信號來取樣本地產生的時鐘信號。 此外’本發明所使用的組件遠比習知方法少，且因此省 電’佔用面積小且容易實施。本發明所容許的資料率也高 於其它方法，因爲它是以半時鐘頻率操作。 (5) (5)200304281 實施方式 圖2是半速率開關式相位偵測器200的方塊圖，用以 將本地時鐘信號鎖定到進入的貪料信號。操作時，相位偵 測器2〇〇接收內嵌有時鐘信號的資料信號，同時也接收時 鐘信號及經過相移的時鐘信號。相位偵測器2 0 0被架構成 輸出用以指示資料信號領先或落後本地時鐘信號的信號。 因此，輸出的信號指示本地時鐘信號爲對準資料信號中之 內嵌時鐘所需相移的方向（但非大小）。在開關模式中操作 的CRU可使用此信號連續地相位小調整以得到相位鎖定 的狀態。相位偵測器200的實施例包括第一相位偵測模組 2 1 0、第二相位偵測模組220以及與第一及第二相位偵測 模組210、220耦合的極性選擇模組23 0。 在一實施例中，時鐘信號是由本地振盪器產生，諸如 電壓控制的振盪器（VCO)，資料信號是所接收的進入資料 信號，例如來自光學通信網路。時鐘信號的頻率大約爲資 料信號之頻率的一半較佳（如圖3所示）。此允許CRU在 資料信號頻率（即資料率）一半的頻率操作。由於數位裝置 的時鐘率會呈現極大的限制，因此，半速率的特性非常有 用，因爲它能在資料率較高的系統中偵測相位。 第一相位偵測模組2 1 0耦合接收時鐘信號及資料信 號。第一相位偵測模組2 1 0被架構成在資料信號的邊緣取 樣時鐘信號。同樣地，第二相位偵測模組22〇也耦合接收 相移的時鐘信號及資料信號，且第二相位偵測模組22〇也 被架構成在資料信號的邊緣取樣相移的本地時鐘信號。第 -8- (6) (6)200304281 一及第二相位偵測模組2 1 0、22 0可以架構成分別在資料 信號的每一個上升緣、下降緣或兩者處取樣正常及相移的 時鐘信號。此外，第一及第二相位偵測模組2 1 0、220可 以被架構成在每一個上升緣、下降緣或兩者處不取樣時鐘 信號一即，模組210、22〇可以忽略某些資料。不過，爲 能正常操作，模組210、220能在同時或大致同時取樣時 鐘信號較佳。 圖3顯示按照本發明實施例之時鐘信號與相移的時鐘 信號的時序圖。相移的時鐘信號以與時鐘信號正交爲佳 (即延遲90度或1/4周期）。正常與相移的時鐘信號可以同 時產生，例如由標準的VCO或其它的本地振盪器產生， 或者，使用一簡單的延遲從其中一個信號產生另一個信 號。雖然相位延遲以大約9 0度較佳，但實際的相移量並 不是關鍵。正交的時鐘信號並不需要完全地正交，甚至在 某些應用中的相移可偏離90度甚多。 圖3中的垂直虛線3 1 0指示第一及第二相位偵測模組 2 1 0、2 2 0取樣時鐘信號的時機。這些時機3 1 0對應於資 料信號的上升及/或下降緣。不論模組2 10、220是在資料 信號的上升、下降或保持不變時實際取樣時鐘信號，也不 論模組2 1 〇、2 2 0被架構成緊接在資料信號的上升或下降 緣或兩者後取樣時鐘信號。因此，第一及第二相位偵測模 組2 1 0、2 2 0不需要在資料信號的每〜個周期期間取樣時 鐘信號。 極性選擇模組2 3 0耦合到第一及第二相位偵測模組 -9- (7) (7)200304281 2 1 0、2 2 0以接收被取樣的信號。極性選擇模組2 3 〇被架 構成根據所取樣的本地時鐘信號及相移的本地時鐘信號決 定資料信號相對於時鐘信號的相位。圖3顯示兩種可能狀 況的時序圖：（1)當資料信號提前，即，時鐘信號落後； 以及（2)當資料信號延後，即，時鐘信號領先。如前所 述’時鐘信號的取樣發生在緊接於資料信號邊緣之後較 佳，如線3 1 0所示。如圖3所示，當資料信號提前，則樣 本都一致，即同時都爲高或都爲低。反之，當資料信號延 後，則樣本不一致，即一高一低。因此，極性選擇模組 2 3 0根據所取樣的時鐘信號與相移的時鐘信號決定資料與 時鐘信號的相對相位。 極性選擇模組2 3 0被架構根據該決定輸出一方向信 號。在較佳實施例中’所輸出的方向信號是一個位元，它 指示資料信號較時鐘信號提前或落後。在開關模式（bang-bang mode)中， 此方向 信號對於將時 鐘信號 鎖定到 資料信 號的內嵌時鐘十分有用，本地時鐘信號的相位朝特定方向 調整某一個量。在一實施例中，此方向信號是提供給 VCO或其它的本地振盪器（通常是在經過平滑化之後，例 如通過低通濾波器）以調整本地時鐘信號。在開關（bang-fa a n g) 操 作中’ 本地時 纟里仏 5虎沒 有穩定 的位置 ，因 爲它的 相位是根據此方向信號連續地被調整。在正確的開關操作 中，本地時鐘信號的相位在資料信號的周圍“跳動”，保持 在其允許的容忍範圍內。當本地時鐘信號按此方法鎖定於 資料信號的內嵌時鐘時’本地時鐘即可周來恢復進入之資 -10- (8) (8)200304281 料的時序。例如，可以使用相移之時鐘信號的上升或下降 緣取樣資料信號（例如，以雙邊緣觸發D型正反器），這些 邊緣實質上出現於資料信號之每一個周期的中間位置。 圖4顯示按照本發明實施例之相位偵測器電路4 〇 〇的 槪圖。時鐘信號爲VCO_I，相移的時鐘信號爲VC0_Q。 從電壓控制之振盪器輸出的VCO-I與VCO_Q以正交爲 佳。資料信號爲D ATA。在此實施例中，第一及第二相位 偵測模組2 1 0、2 2 0 (來自圖2的實施例）分別是以d型正 反器410、420實施。DATA信號耦合到正反器410、420 的時鐘輸入，VCOJ與VCO_Q分別耦合到正反器410、 420的D輸入。按此方式架構，正反器410、420分別在 DATA信號的上升緣取樣VCO_1與VCO —Q，分別產生信 號Q 1與Q 2，如圖所示。或者，也可以將電路4 0 0架構成 在它們的下降緣取樣時鐘信號，或可使用雙緣觸發的正反 器以取樣上升及下降緣。此外，可以獲致相同或類同取樣 結果之邏輯組件的其它變化與組合也不會偏離本發明的槪 念。 極性選擇電路43 0耦合接收來自正反器410、420的 信號Q1及Q2。極性選擇電路43 0使用Q1及Q2決定 CLOCK與DATA的相位。如前文描述，如果Q1與Q2相 同，則DATA信號領先CLOCK信號。如果Q1與Q2不 同，則DATA信號落後CLOCK信號。極性選擇電路43〇 根據此比較產生OUT信號，用以指示DATA是領先或落 後於CLOCK信號。如前所述，此OUT信號可以用來校正 200304281 Ο) VCO或其它以開關模式操作的本地振盪器。因爲在開關 操作中沒有穩定位置，且本地時鐘不斷地被更新，當 DATA信號既不領先也不落後CLOCK信號的罕見狀況 (即，在電路400的度量極限內DAT A與CLOCK信號同相 位）可予忽略。 導出的OUT信號以單個位元較佳，它指示CLOCK信 號與DATA信號的相對頻率。例如高位元指示DATA信號 較早，低位元指示DATA較遲。很明顯，這些定義也可相 反。此OUT信號供應給VCO或其它本地振盪器以控制它 們的相位調整，或者，OUT信號也可供給爲本地振盪器 產生控制信號的其它預處理電路。OUT信號在供應給 VCO或其它本地振盪器之前先予平滑化較佳，例如通過 低通濾波器。 極性選擇電路4 3 0可以使用任何類型的技術實施。在 一實施例中，極性選擇電路43 0包含多工器（MUX)44〇， 如圖4所示，例如可將MUX 440架構成根據Q2的狀態送 出Q Ϊ或反相的Q 1。在另一實施例中，極性選擇電路4 3 0 包含一邏輯組件的網路，按照以下的真値表從輸入Q 1及 Q2產生OUT信號： >_91 Q2 OUT 0 0 1(資料領先） ___0 1 〇(資料落後） 1 0 〇(資料落後） __1 1 1(資料領先） -12- (10) 200304281 此表顯示反相x〇R閘所實施的邏輯；不過，也可以 使用其它的組合與順序邏輯的實施例獲致相同結果。相位 偵測器電路400使用微分邏輯實施較佳。微分邏輯有利於 高速的應用，諸如光學通信網路，因爲它能有效地使信號 的振幅加倍（因此所需求的信號較小），它也可降低雜訊的 影響，並可消除漂移。Bipolar Technology ,,, IEEE BCTM 8.1, 1998: and Pottacker et al., "AS i Bipolar Phase and F req uency Detect or IC for Clock Extraction up to 8GB / s,", IEEE Journal of s olid-State Circuit Vo 1.2 7, No. 12, Dec. 1 9 92. However, none of the phase detectors described in all the above documents have all the advantages of the present invention. For example, some of them are extremely high clocks for optical applications. It operates in frequency, so the rate is greatly limited. Some other local oscillators are used to sample incoming data, making the phase detector sensitive to the data pattern (ie, long strings of 1 or 0). Because of this, Sensitivity, phase detectors do not need to output the correct direction all the time to correct the phase. Finally, not all are the bang-bang phase detectors I want because they are the simplest in design Therefore, we need a phase detector for CRU, which allows (4) (4) 200304281 to allow the local oscillator to operate at half clock frequency, using the received clock signal to fetch Local oscillator and determine any symbols (directions) that need to be modified. SUMMARY OF THE INVENTION This document describes a half-rate switchable phase detector that detects the phase of an incoming data signal relative to the local clock signal as the local clock. The signal locks the direction of the incoming data signal. In a preferred embodiment, the frequency of the local clock signal is about half that of the data signal. The first phase detection module uses the data signal to sample the local clock signal, and the second phase detection The module uses the data signal to sample the phase-shifted local clock signal. The polarity selection module determines the phase of the data signal relative to the local clock signal according to the sampled local clock signal and the phase-shifted local clock signal, and outputs a direction according to the determined result Signal. This direction signal is used, for example, by a local oscillator to adjust the local clock signal to lock the local clock signal to the incoming data signal. In other embodiments of the present invention, the phase detector uses a flip-flop. Various configurations of logic logic and / or other standard logic and circuit components Implementation. In one aspect of the present invention, the polarity selection module is implemented using a tri-stable AND gate. # The advantage of the B-month is that the half-rate on-off phase detector is very strong because it uses the incoming data signal to sample Locally generated clock signal. In addition, 'the present invention uses far fewer components than conventional methods, and therefore saves power' occupies a small area and is easy to implement. The data rate allowed by the present invention is also higher than other methods because it uses Half clock frequency operation. (5) (5) 200304281 Implementation Figure 2 is a block diagram of a half-rate switching phase detector 200, which is used to lock the local clock signal to the incoming gluttonous signal. In operation, the phase detector 2000 receives the data signal with the embedded clock signal, and also receives the clock signal and the phase-shifted clock signal. The phase detector 2 0 0 is constructed to output a signal indicating whether the data signal is ahead or behind the local clock signal. Therefore, the output signal indicates the direction (but not magnitude) of the phase shift required to align the embedded clock in the data signal with the local clock signal. CRUs operating in switch mode can use this signal to continuously phase-adjust to obtain a phase-locked state. The embodiment of the phase detector 200 includes a first phase detection module 210, a second phase detection module 220, and a polarity selection module 23 coupled to the first and second phase detection modules 210 and 220. 0. In one embodiment, the clock signal is generated by a local oscillator, such as a voltage controlled oscillator (VCO), and the data signal is a received incoming data signal, such as from an optical communication network. The frequency of the clock signal is preferably about half the frequency of the data signal (as shown in Figure 3). This allows the CRU to operate at a frequency that is half the data signal frequency (ie, the data rate). Since the clock rate of digital devices can be extremely limited, the half-rate feature is very useful because it can detect phase in systems with higher data rates. The first phase detection module 210 is coupled to receive a clock signal and a data signal. The first phase detection module 210 is framed to sample the clock signal at the edge of the data signal. Similarly, the second phase detection module 22 is also coupled to receive the phase-shifted clock signal and the data signal, and the second phase detection module 22 is also constructed to sample the phase-shifted local clock signal at the edge of the data signal. . No. -8- (6) (6) 200304281 The first and second phase detection modules 2 1 0, 22 0 can be constructed to sample normal and phase shift at each rising edge, falling edge, or both of the data signal. Clock signal. In addition, the first and second phase detection modules 2 1 0, 220 can be constructed to not sample the clock signal at each rising edge, falling edge, or both. That is, the modules 210 and 22 can ignore some data. However, for normal operation, it is better that the modules 210, 220 can sample the clock signals at the same time or at the same time. FIG. 3 shows a timing diagram of a clock signal and a phase-shifted clock signal according to an embodiment of the present invention. The phase-shifted clock signal is preferably orthogonal to the clock signal (that is, delayed by 90 degrees or 1/4 cycle). Normal and phase-shifted clock signals can be generated at the same time, for example by a standard VCO or other local oscillator, or a simple delay can be used to generate one from another. Although the phase delay is preferably about 90 degrees, the actual amount of phase shift is not critical. Orthogonal clock signals do not need to be completely orthogonal, and even the phase shift in some applications can deviate by as much as 90 degrees. The vertical dashed line 3 1 0 in FIG. 3 indicates the timing of sampling clock signals of the first and second phase detection modules 2 1 0 and 2 2 0. These timings 3 1 0 correspond to rising and / or falling edges of the data signal. Whether module 2 10, 220 is actually sampling the clock signal when the data signal rises, falls, or stays the same, and whether module 2 1 0, 2 2 0 is framed to immediately follow the rising or falling edge of the data signal or The clock signal is sampled after both. Therefore, the first and second phase detection modules 2 1 0, 2 2 0 do not need to sample the clock signal during every ~ period of the data signal. The polarity selection module 2 3 0 is coupled to the first and second phase detection modules -9- (7) (7) 200304281 2 1 0, 2 2 0 to receive the sampled signal. The polarity selection module 23 is constructed to determine the phase of the data signal relative to the clock signal based on the sampled local clock signal and the phase-shifted local clock signal. Figure 3 shows a timing diagram of two possible situations: (1) when the data signal is advanced, that is, the clock signal is behind; and (2) when the data signal is delayed, that is, the clock signal is leading. As mentioned earlier, it is better that the sampling of the clock signal occurs immediately after the edge of the data signal, as shown by line 3 10. As shown in Figure 3, when the data signal advances, the samples are consistent, that is, both are high or both are low at the same time. Conversely, when the data signal is delayed, the samples are inconsistent, that is, one high and one low. Therefore, the polarity selection module 230 determines the relative phase of the data and the clock signal according to the sampled clock signal and the phase-shifted clock signal. The polarity selection module 230 is configured to output a direction signal according to the decision. In the preferred embodiment, the direction signal output is a bit, which indicates that the data signal is ahead or behind the clock signal. In bang-bang mode, this direction signal is very useful for the embedded clock that locks the clock signal to the data signal. The phase of the local clock signal is adjusted to a certain direction by a certain amount. In one embodiment, this direction signal is provided to a VCO or other local oscillator (usually after smoothing, such as through a low-pass filter) to adjust the local clock signal. During the switch (bang-fa a n g) operation, the local 本地 5 仏 tiger has no stable position because its phase is continuously adjusted according to this direction signal. In the correct switching operation, the phase of the local clock signal “bounces” around the data signal and remains within its allowable tolerance range. When the local clock signal is locked to the embedded clock of the data signal in this way, the local clock can recover the incoming timing in a week -10- (8) (8) 200304281. For example, a rising or falling edge of a phase-shifted clock signal can be used to sample a data signal (for example, triggering a D-type flip-flop with double edges) that appear substantially in the middle of each cycle of the data signal. FIG. 4 shows a block diagram of a phase detector circuit 400 according to an embodiment of the present invention. The clock signal is VCO_I, and the phase-shifted clock signal is VC0_Q. The VCO-I and VCO_Q output from the voltage controlled oscillator are preferably orthogonal. The data signal is D ATA. In this embodiment, the first and second phase detection modules 2 1 0 and 2 2 0 (from the embodiment in FIG. 2) are implemented with d-type flip-flops 410 and 420, respectively. The DATA signal is coupled to the clock inputs of the flip-flops 410 and 420, and VCOJ and VCO_Q are coupled to the D inputs of the flip-flops 410 and 420, respectively. In this way, the flip-flops 410 and 420 respectively sample VCO_1 and VCO —Q on the rising edge of the DATA signal, and generate signals Q 1 and Q 2 respectively, as shown in the figure. Alternatively, the circuit 400 can be configured to sample the clock signals at their falling edges, or the flip-flops can be used to sample the rising and falling edges. In addition, other changes and combinations of logic components that can achieve the same or similar sampling results will not deviate from the concept of the present invention. The polarity selection circuit 430 is coupled to receive the signals Q1 and Q2 from the flip-flops 410 and 420. The polarity selection circuit 43 0 uses Q1 and Q2 to determine the phase of CLOCK and DATA. As described earlier, if Q1 and Q2 are the same, the DATA signal leads the CLOCK signal. If Q1 and Q2 are different, the DATA signal is behind the CLOCK signal. Polarity selection circuit 43. Based on this comparison, an OUT signal is generated to indicate whether DATA is leading or falling behind the CLOCK signal. As mentioned earlier, this OUT signal can be used to correct 200304281 〇) VCO or other local oscillators operating in switch mode. Because there is no stable position in the switching operation, and the local clock is constantly updated, when the DATA signal neither leads nor lags the rare condition of the CLOCK signal (that is, the DAT A and CLOCK signals are in phase within the metric limit of the circuit 400) I ignored. The derived OUT signal is preferably a single bit, which indicates the relative frequency of the CLOCK signal and the DATA signal. For example, the high bit indicates that the DATA signal is earlier, and the low bit indicates that DATA is later. Obviously, these definitions can also be reversed. This OUT signal is supplied to the VCO or other local oscillator to control their phase adjustment, or the OUT signal can also be supplied to other pre-processing circuits that generate control signals for the local oscillator. The OUT signal is preferably smoothed before being supplied to a VCO or other local oscillator, such as through a low-pass filter. The polarity selection circuit 430 can be implemented using any type of technology. In one embodiment, the polarity selection circuit 43 0 includes a multiplexer (MUX) 44. As shown in FIG. 4, for example, the MUX 440 can be configured to output Q Ϊ or inverted Q 1 according to the state of Q2. In another embodiment, the polarity selection circuit 4 3 0 includes a network of logic components, and generates an OUT signal from the inputs Q 1 and Q2 according to the following truth table: > _91 Q2 OUT 0 0 1 (data lead) ___0 1 〇 (data lag) 1 0 〇 (data lag) __1 1 1 (data lag) -12- (10) 200304281 This table shows the logic implemented by the inverse x〇R gate; however, other combinations and Embodiments of sequential logic achieve the same result. The phase detector circuit 400 is preferably implemented using differential logic. Differential logic is beneficial for high-speed applications, such as optical communication networks, because it can effectively double the amplitude of the signal (therefore, the required signal is smaller). It can also reduce the effects of noise and eliminate drift.
極性選擇電路430也可以使用三穩AND閘5 00實 施，即如圖5所示的實施例。下表提供用於三穩AND閘 5 0 0的邏輯。 Q1 Q2 OUT OUTN 0 0 1 1 0 1 1 1 1 0 0 1 1 1 1 0The polarity selection circuit 430 can also be implemented using a tri-stable AND gate 500, that is, the embodiment shown in FIG. The following table provides the logic for the tri-stable AND gate 5 0 0. Q1 Q2 OUT OUTN 0 0 1 1 0 1 1 1 1 0 0 1 1 1 1 0
此電路5 0 0之所以被稱爲三穩，是因爲只有當輸入 Q 1爲高時它才操作。當輸入信號Q 1爲低時，三穩AND 閘5 00產生零値的結果，其中輸出信號OUT與OUTN都 爲高。當輸入信號Q1爲高時，三穩AND閘5 00正常操 作。在此正常操作中，當Q1與Q2不同時OUT信號爲低 (對應於DATA在落後狀態，如圖4所示），當Q1與Q2相 同時OUT信號爲高（對應於DATA在領先狀態，如圖4所 示）。 -13- (11) (11)200304281 三穩AND閘5 0 0的輸出可用來訓練本地振盪器’如 _ . 前所述，當OUT與OUTN都爲高時（零値狀況）本地振邊 · 器略過相位偵測器。三穩AND閘5 0 〇的操作亦如前述實 施例，除了它忽略部分的資料點一即，其中樣本Q 1爲高 的任何樣本對。由於對稱，在正常操作的狀況下’被忽略 的資料點預期是半數的資料點。由於有極大量的資料點可 供使用，因此，部分忽略不會對相位偵測器的效能產生實 質的影響。 # 在前述的發明實施例中已說明及描述了本發明的目 的。但並非意欲包羅或將本發明限制在所揭示的型式。熟 悉此方面技術的人士應暸解，由於以上的教導，可做很多 的修改與變化。例如，雖然圖中所示的三穩AND閘500 是以雙極接面電晶體實施，但熟悉此方面技術的人士應瞭 解，該電路可有各種等同的組合與取代，諸如使用NPN 雙極接面電晶體、CMOS電晶體或其它半導體技術。因 此，本發明的範圍不受此詳細描述的限制，而是由所附申 # 請專利範圍限制。 圖式簡單說明 圖1是習知時鐘恢復單元（c R U)的簡單方塊圖。 圖2是按照本發明實施例之相位偵測器的功能方塊 圖3是圖2之相位偵測器的時序圖。 圖4是相位偵測器之實施例的槪圖。 • 14- (12) 200304281 圖5是圖4之極性選擇電路43 0之另一實施例的槪 圖。 主要元/ ί牛對照表 1 05 數位 頻 率 及 相 位 偵 測 器 110 濾波 器 115 振盪 器 1 25 D型 正 反 器 13 0 鎖定 偵 測 器 200 半速 率 開 關 式 相 位 偵 測器 2 10 第一 相 位 偵 測 模 組 220 第二 相 位 偵 測 模 組 23 0 極性 選 擇 模 組 4 10 D型 正 反 器 420 D型 正 反 器 43 0 極性 選 擇 電 路 440 多工 器 500 二 fe AND聞This circuit 5 0 0 is called tri-stable because it operates only when input Q 1 is high. When the input signal Q 1 is low, the three-stable AND gate 5 00 produces a zero signal, where the output signals OUT and OUTN are both high. When the input signal Q1 is high, the three-stable AND gate 5 00 operates normally. In this normal operation, when Q1 and Q2 are different, the OUT signal is low (corresponding to DATA in the backward state, as shown in Figure 4), when Q1 and Q2 are the same, the OUT signal is high (corresponding to DATA in the leading state, such as Figure 4). -13- (11) (11) 200304281 The output of the tri-stable AND gate 5 0 0 can be used to train the local oscillator '. To bypass the phase detector. The operation of the tri-stable AND gate 5 0 0 is the same as in the previous embodiment, except that it ignores some of the data points, that is, any sample pair where the sample Q 1 is high. Due to symmetry, the data points that are ignored in normal operation are expected to be half of the data points. Since there are a very large number of data points available, partial neglect will not have a substantial impact on the performance of the phase detector. # The purpose of the present invention has been illustrated and described in the foregoing embodiments of the invention. It is not intended to be exhaustive or to limit the invention to the forms disclosed. Those familiar with this technology should understand that due to the above teachings, many modifications and changes can be made. For example, although the three-stable AND gate 500 shown in the figure is implemented with a bipolar junction transistor, those skilled in the art should understand that this circuit can have various equivalent combinations and replacements, such as the use of NPN bipolar junction Surface transistor, CMOS transistor or other semiconductor technology. Therefore, the scope of the present invention is not limited by this detailed description, but is limited by the scope of the appended claims. Brief Description of the Drawings Figure 1 is a simple block diagram of a conventional clock recovery unit (c R U). FIG. 2 is a functional block diagram of a phase detector according to an embodiment of the present invention. FIG. 3 is a timing diagram of the phase detector of FIG. 2. FIG. 4 is a schematic diagram of an embodiment of a phase detector. • 14- (12) 200304281 FIG. 5 is a 槪 diagram of another embodiment of the polarity selection circuit 43 0 of FIG. 4. Main unit / Table 1 05 Digital frequency and phase detector 110 Filter 115 Oscillator 1 25 D-type flip-flop 13 0 Lock detector 200 Half-rate switching phase detector 2 10 First phase detection Test module 220 Second phase detection module 23 0 Polarity selection module 4 10 D-type inverter 420 D-type inverter 43 0 Polarity selection circuit 440 Multiplexer 500 Two-fe AND
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