200303115 玖、發明說明 (發明說明應敘明：發明所屬之技術領域、先前技術、內容、實施方式及圖式簡單說明） 發明所屬之技術領域 本發明涉及半導體電路，特別是由半導體電路所構成之 A G C放大器。 先前技術 AGC放大器先前是用在收信機等裝置中。此處AGC放大 器自動地調整自己之增益以放大一般之輸入信號且輸出一 定振幅之信號。以此種A G C放大器爲例亦可了解起磁 (G i 1 b e r t)電路。 第1圖是此種起磁單元型之放大電路之構成圖。 第1圖中，放大電路由輸入信號P輸入用之電晶體1， 輸入信號N輸入用之電晶體2，增益控制電壓輸入用之電 晶體3及6，具固定値之基準電壓輸入用之電晶體4及5 所構成。 此種放大電路中，輸入信號P及輸入信號N之差 (difference)獲得增益之後作爲輸出信號P及輸出信號N之 差而輸出。此處所謂增益（gain)是以輸出信號P及N爲準 而由回授電壓之增益控制電壓及基準電壓之差所決定。又 ，此種回授之動作會使輸出信號之振幅成爲一定値，因此 ，輸出信號P及N之振幅收斂於一定之値。 然而，在此種AGC放大器中，VDD〜GND間直接連接之 電晶體數目較多。 例如，第1圖之放大電路中，VDD〜GND之間有電流源 200303115 2 1，電阻3 1及3 2，輸入用電晶體1及2，及增益控制用電 晶體3〜6，電阻3 3及3 4，直接連接之元件段數亦增加。 於是VDD〜GND間之元件加入相當多之段數時，由於各 元件中所產生之電壓下降，則不能得到足夠之輸入動態範 圍。即，若輸入信號之振幅變大時，輸出波形即失真。 本發明之目的是提供一種輸入動態範圍可設定成較大之 放大電路。 發明內容 若藉由本發明之一形式，則本發明之半導體電路之特徵 是具有：第1電路部份，其含有一個以上之電晶體；第2 電路部份，其對第i電路部分配置成折回方式且含有一個 以上之電晶體，以流過第1電路部份之電流爲基準使與第 1電路部份之輸入電壓相對應之電壓被輸出；電流傳送電 路，其具有一個以上之電晶體且使與流過第1電路部份之 電流相對應之電流傳送至第2電路部份。 在上述構造中，由於第1電路部份及第2電路部份間之 切換以及第2電路部份對應於第1電路部份而以折回方式 配置著，則由電源至接地之路徑中直接連接之元件之數目 可較少，各元件中所產生之電壓降之影響可被抑制，輸入 動態範圍即可變大。 在本發明之其它形式中，本發明之半導體電路之特徵是 包含：第1電路部份，其包含一個以上之電晶體；第2電 路部份，其含有一個以上之電晶體，以流過第1電路部份 之電流爲基準使與第1電路部份之輸入電壓相對應之電壓 200303115 被輸出；電流傳送電路，其含有一個以上之電晶體，使與 流過第1電路部份之電流相對應之電流由第2電路部份流 出。 在上述構成中，第1電路部份與第2電路部份未直列地 連接，與流過第1電路部份之電流相對應之電流由第2電 路部份流出。因此，由電源到接地之路徑中直列地連接之 元件數目即可減少，各元件中所產生之電壓降之影響可被 抑制，輸入動態範圍即可變大。 在本發明之其它形式中，本發明之半導體電路之特徵是 包含：第1電路部份，其包含一個以上之電晶體且設在第 1直流電位側；第2電路部份，其含有一個以上之電晶體 且設在第1直流電位側，以流過第1電路部份之電流爲基 準使與第1電路部份之輸入電壓相對應之電壓被輸出；電 流傳送電路，其含有一個以上之電晶體且設在一與第1直 流電位不同之第2直流電位側，使與流經第1電路部份之 電流相對應之電流傳送至第2電路部份。 在上述之構成中，第1電路部份與第2電路部份共同設 在第1直流電位側。於是，第1電路部份及第2電路部份 未直到地連接，與流經第1電路部份之電流相對應之電流 由第2電路部份流出。因此，由電源至接地之路徑中直列地 連接之元件之數目可減少，各元件中所產生之電壓降之影響 受到抑制，輸入動態範圍即可變大。第1直流電位例如是一 種電源，又，第2直流電位例如處於接地電位。但反之以第 1直流電位作爲接地電位且第2直流電位作爲電源亦可。 200303115 在以上之各種形式中，所稱之”使與流經第1電路部份之 電流相對應之電流由第2電路部份流出（或傳送）所用之電 流傳送電路’’例如是由一對以上之電流鏡所構成，當流經第 1電路部份之電流流過電流鏡之任一個時，以對應於該電 流鏡之電晶體大小之比率所決定之另一個電晶體中所流過 之電流作爲π對應之電流”而由第2電路部份引出所用之電 路即稱爲”電流傳送電路”；或當電流鏡之任一個中流過所 定之値之電流時，以對應於該電流鏡之電晶體大小之比率 所決定之另一電晶體中所流過之電流及流過第1電路部份 之電流之差作爲’’對應之電流’’而由第2電路部份引出所用 之電路亦稱爲π電流傳送電路’’。又，上述比率未必是1對 1 ° 在上述各種形式中，該電流傳送電路例如可以是一種電 流鏡構造或一種折疊式串接（folded cascode)構造。 又，在上述各種形式中，第1電路部份可含有P通道型 電晶體。 實施方式 以下將依據圖面來說明本發明之實施形式。 本實施形式之AGC放大器之構造顯示在第2A圖中。 本實施形式之放大電路中，以箭頭A所指之處使第1圖 中所示之先前電路分離，同時使用電流鏡連接至該處，然 後使輸入該增益控制電壓或基準電壓所用之電晶體3〜6 折回至電源側以形成本實施形式之放大電路。 第2A圖中，AGC放大電路由第1電路部份、第2電路部 200303115 份、電流傳送電路所構成。第1電路部份含有接收該輸入 信號（輸入電壓）P及N所用之電晶體1、2。又，第2電路 部份含有該增益控制用之電晶體3〜6且使輸出信號P及 N (對應於第1電路部份之輸入電壓）被輸出。電流傳送電路 含有使第1電路部份之電流轉移於第2電路部份中所用之 電晶體 7a、 7b、 8a、 8b。 因此，電晶體1中輸入該輸入信號P，電晶體2中輸入 該輸入信號N。即，電晶體1及電晶體2構成一組接收該 差動輸入所用之電晶體（差動對）。又，電晶體3及6中輸 入該增益控制電壓，電晶體4及5中輸入一固定値之基準 電壓。構成此電路所用之這些元件亦出現在第1圖之習知 之電路中。 在以上述方式構成之AGC放大電路中，輸入信號P及輸 入信號N之差（差動輸入）以增益控制電壓信號及基準電壓 信號之差來達成增益（gain)之後作爲輸出信號P及輸出信 號N之差（差動輸出）而輸出。 又，電流i2對應於電流i 1，其値依據電晶體大小（電流 鏡）之比率來決定。即，由於電晶體7 a及7 b是電流鏡，則 第2A圖中電流il及2是與電晶體7a及7b之大小成比例之 値。但是，由於信號之流動路徑折回，即使第1圖之習知 例之電路中電流i流入電晶體3及4中，第2 A圖之本實施 形式之電路中該電流i 2卻由電晶體3及4中流出。於是， 第1圖之習知例中由電晶體3取出該輸出信號N，由電晶體 4取出該輸出信號P，第2 A圖中由電晶體3取出該輸出信 -10- 200303115 號P，由電晶體4取出該輸出信號N。 又，電晶體8 a及8 b同樣構成電流鏡，其動作與電晶體 7a及7b相同。 因此，輸入用電晶體1及2之電流轉移於增益控制用之 電晶體3〜6。 第2A圖中，輸入電晶體1及2中爲了抑制雜訊（noise) ，則可使用P通道型。 又，在以上之說明中，電流源2 1及增益控制用之電晶體 3〜6之一端是設在VDD側，電流傳送用電晶體7a、7b、 8a、8b之一端設在GND側，反之，電流源21及增益控制 用電晶體3〜6之一端設在GN D側，電流傳送用電晶體7 a 、7 b、8 a、8 b之一端設在V D D側時亦可。 在上述之構成中，V D D〜GN D間若電阻經由一次且電晶 體經由2次，或電流源經由1次，電阻經由1次，電晶體 經由2次，則可由VDD到達GND，若與第1圖之習知例 之放大電路中經由電流源1次，電阻2次，電晶體2次而 由V D D到達GN D之情況相比較，由於經由電阻之次數可 減少1次，則可抑制其分壓降，對更廣範圍之輸入可得到 線性之輸出。又，電流源2 1之構成如第2 B圖所示，第2 A 圖之電流源2 1所造成之電壓降相當於電晶體1 1之一部份。 第3圖是本實施形式之另一實施例之AGC放大電路之構 成。第3圖中與第2 A及2 B圖重複之部份不再說明。 第3圖類似於第2 A圖，由第1圖所示之習知例之電路 之箭頭A之處切斷使電路分開。然後使用折疊式串接構造 -11- 200303115 來連接該已切斷之電路，使輸入該增益控制電壓或 壓所用之電晶體3〜6折回至電源側，這樣即得第3 大電路。 第3圖中，由電流源2 2使所定値之電流i 3流經 9a。此處由於電晶體9a及9b是電流鏡，則電流i: 之値是依電晶體9 a及9 b之大小之比（r a t i 〇 )來分配 由於電晶體9 a及9 c亦爲電流鏡，則電流i 3及i 5 依電晶體9a及9c之大小之比來分配。 上述電晶體9a、9b及9c之大小之比（ratio)是1 ，貝丨J例如i 3 = 1 0 m A時，i 4 = i 5 = 1 0 m A。此時，若輸7 之電流値i 2成爲3 m A，輸入信號P之電流値i 1成 ，貝U i6 = i5-i2=10-3 = 7mA，i7 = i4-il = 10-5 = 5mA 〇 因 入信號P之電流値Π及輸入信號N之電流値i 2之 2mA)正確地傳送至增益控制用電晶體3〜6而成爲 及i 7之差。又，這表示電流i 7對應於電流i 1，電 應於電流i 2。即，電流鏡之電晶體9 a及9 b或9 a〕 之任一個（具體而言是9a)中流過之所定値之電流i3 之電流i 4、i 5是以電流鏡之另一方之電晶體（具體丨 9 b、9 c)中對應於電晶體大小之比率所流過之流經另 電晶體之i 4、i 5及輸入用電晶體1及2之電流i 1、 作爲對應於i 1、i 2之電流i 7、i 6而由增益控制用之 3〜6弓1出。 於是，輸入用電晶體1及2之電流即轉移至增益 之電晶體3〜6。 基準電 圖之放 電晶體 3及i 4 。又， 之値是 對1時 、信號N 爲5mA 此，輸 差（5-3= 電流i 6 流i6對 艮9 c中 所對應 而言是 一方之 i2之差 電晶體 控制用 -12- 200303115 又，第3圖之電路在與第1圖之習知例比較時，信 流動路徑會折回。因此，第1圖之電路中電流i流入 體3及4，但第3圖之電路中電流i 6由電晶體3及4 € 第3圖與第2A圖同樣可在輸入用電晶體1及2中 通道型以抑制雜訊。 又，在以上之說明中各電流源2 1及2 2及增益控制 晶體3〜6之一端設在V D D側，電流傳送用電晶體9 、9 c之一端設在GN D側，反之，各電流源2 1及2 2 益控制用電晶體3〜6之一端設在GND側，電流傳送 晶體9 a、9 b、9 c之一端設在V D D側亦可。 在上述之構成中，V D D〜GN D之間若經電阻1次及 體2次，或電流源經由1次，電阻經由1次，電晶體 2次，則可由VDD到達GND，若與第1圖之習知例之 電路中經由電流源1次，電阻2次，電晶體2次而由 到達GN D之情況相比較，由於經由電阻之次數可減少 ，則可抑制其分壓降，對更廣範圍之輸入可得到線性 出。 以上之說明是以A G C放大電路來進行，電源及接地 所設有之電路切斷後以電流傳送用之電晶體來連接， 接地間以直列方式連接之元件之數目即可被抑制，輸 態範圍即可擴大，但此種構成亦可適用於AGC放大電 外之電路。例如，亦可適用於乘算電路。 如以上之說明所示，本發明可達成一輸入電壓範圍 且輸出波形之失真很小之半導體電路。 號之 電晶 Π出。 g用P 用電 a、9 b 及增 用電 電晶 經由 放大 VDD 1次 之輸 之間 電源- 入動 路以 廣泛 -13- 200303115 本發明以下將依據圖式來說明。 圖式簡單說明 第1圖 先前之放大電路之構造。 第2 A圖本發明之實施形式之放大電路之一種構造。 第2 B圖電流源之詳細圖。 第3圖本發明之實施形式之放大電路之另一種構造。 主要部分之代表符號說明 1，2,3〜6 電晶體200303115 发明 Description of the invention (The description of the invention should state: the technical field, prior art, contents, embodiments, and drawings of the invention are briefly described) The technical field to which the invention belongs The present invention relates to semiconductor circuits, and particularly to semiconductor circuits AGC amplifier. Prior art AGC amplifiers were previously used in devices such as receivers. Here the AGC amplifier automatically adjusts its own gain to amplify the general input signal and output a signal with a certain amplitude. Taking this A G C amplifier as an example, you can also understand the magnetization (G i 1 b e r t) circuit. Fig. 1 is a configuration diagram of such a magnetizing unit type amplifier circuit. In Figure 1, the amplifier circuit is composed of transistor 1 for input signal P, transistor 2 for input signal N, transistors 3 and 6 for gain control voltage input, and fixed reference voltage input. Crystal 4 and 5. In such an amplifier circuit, the difference between the input signal P and the input signal N is obtained as a difference between the output signal P and the output signal N after gain is obtained. The gain here is determined by the difference between the gain control voltage of the feedback voltage and the reference voltage, which is based on the output signals P and N. In addition, this feedback action makes the amplitude of the output signal constant, so that the amplitudes of the output signals P and N converge to a certain amplitude. However, in such an AGC amplifier, the number of transistors directly connected between VDD and GND is large. For example, in the amplifier circuit of Fig. 1, there is a current source 200303115 2 1 between VDD and GND, resistors 3 1 and 32, input transistors 1 and 2, and gain control transistors 3 to 6, and resistor 3 3 And 3 4, the number of directly connected component segments also increased. Therefore, when a considerable number of segments are added to the components between VDD and GND, due to the voltage drop in each component, a sufficient input dynamic range cannot be obtained. That is, when the amplitude of the input signal becomes large, the output waveform is distorted. An object of the present invention is to provide an amplifying circuit whose input dynamic range can be set to be large. SUMMARY OF THE INVENTION According to one form of the present invention, the semiconductor circuit of the present invention is characterized by having a first circuit portion containing more than one transistor, and a second circuit portion configured to return to the i-th circuit portion. And contains more than one transistor, and the voltage corresponding to the input voltage of the first circuit part is output based on the current flowing through the first circuit part; the current transfer circuit has more than one transistor and A current corresponding to the current flowing through the first circuit portion is transmitted to the second circuit portion. In the above structure, since the first circuit part and the second circuit part are switched and the second circuit part corresponds to the first circuit part and is configured in a folded-back manner, the path from the power source to the ground is directly connected The number of components can be small, the influence of the voltage drop generated in each component can be suppressed, and the input dynamic range can be increased. In other forms of the present invention, the semiconductor circuit of the present invention is characterized by comprising: a first circuit part containing more than one transistor; a second circuit part containing more than one transistor to flow through the first The current of the 1st circuit part is used as a reference to cause a voltage 200303115 corresponding to the input voltage of the 1st circuit part to be output. The current transmission circuit contains more than one transistor, which is related to the current flowing through the 1st circuit part. The corresponding current flows from the second circuit part. In the above configuration, the first circuit portion and the second circuit portion are not connected in line, and a current corresponding to the current flowing through the first circuit portion flows from the second circuit portion. Therefore, the number of components connected in-line in the path from the power source to the ground can be reduced, the influence of the voltage drop generated in each component can be suppressed, and the input dynamic range can be increased. In another form of the present invention, the semiconductor circuit of the present invention is characterized by comprising: a first circuit part including more than one transistor and provided on the first DC potential side; and a second circuit part including more than one The transistor is set on the first DC potential side, and the voltage corresponding to the input voltage of the first circuit part is output based on the current flowing through the first circuit part as a reference; the current transfer circuit contains more than one The transistor is also provided on a second DC potential side different from the first DC potential, so that a current corresponding to the current flowing through the first circuit portion is transmitted to the second circuit portion. In the above configuration, the first circuit portion and the second circuit portion are commonly provided on the first DC potential side. Then, the first circuit part and the second circuit part are not connected to the ground, and a current corresponding to the current flowing through the first circuit part flows out from the second circuit part. Therefore, the number of components connected in-line in the path from power to ground can be reduced, the influence of the voltage drop generated in each component is suppressed, and the input dynamic range can be increased. The first DC potential is, for example, a power source, and the second DC potential is, for example, a ground potential. Conversely, it is also possible to use the first DC potential as the ground potential and the second DC potential as the power source. 200303115 In each of the above forms, the so-called "current transmission circuit for causing a current corresponding to the current flowing through the first circuit part to flow out (or transmit) from the second circuit part" is, for example, a pair The above current mirror is constituted. When the current flowing through the first circuit part flows through any one of the current mirrors, the current flowing through the other transistor is determined by the ratio corresponding to the size of the transistor of the current mirror. The current used as the current corresponding to π is derived from the circuit used in the second circuit part is called "current transfer circuit"; or when a predetermined current flows through any one of the current mirrors, the current corresponding to the current mirror The difference between the current flowing through the other transistor and the current flowing through the first circuit part is determined by the ratio of the transistor size as the `` corresponding current '', and the circuit used by the second circuit part is also derived. Called π current transfer circuit. In addition, the above ratio is not necessarily 1 to 1 °. In the above various forms, the current transmission circuit may be, for example, a current mirror structure or a folded cascode structure. Further, in the above-mentioned various forms, the first circuit portion may include a P-channel type transistor. Embodiments The embodiments of the present invention will be described below with reference to the drawings. The structure of the AGC amplifier of this embodiment is shown in FIG. 2A. In the amplifying circuit of this embodiment, the previous circuit shown in the first figure is separated by the position indicated by the arrow A, and at the same time, it is connected to it with a current mirror, and then the transistor used to input the gain control voltage or reference voltage is input. 3 ~ 6 Fold back to the power supply side to form the amplifier circuit of this embodiment. In Fig. 2A, the AGC amplifier circuit is composed of a first circuit portion, a second circuit portion 200303115, and a current transmission circuit. The first circuit part contains transistors 1, 2 for receiving the input signals (input voltages) P and N. In addition, the second circuit section includes the transistors 3 to 6 for gain control and outputs the output signals P and N (corresponding to the input voltage of the first circuit section). The current transfer circuit includes transistors 7a, 7b, 8a, and 8b for transferring the current of the first circuit portion to the second circuit portion. Therefore, the input signal P is input to the transistor 1, and the input signal N is input to the transistor 2. That is, the transistor 1 and the transistor 2 constitute a group of transistors (differential pairs) for receiving the differential input. The gain control voltage is input to transistors 3 and 6, and a fixed reference voltage is input to transistors 4 and 5. The components used to construct this circuit also appear in the conventional circuit of FIG. In the AGC amplifier circuit configured as described above, the difference between the input signal P and the input signal N (differential input) is obtained by using the difference between the gain control voltage signal and the reference voltage signal to achieve gain (gain) as the output signal P and the output signal. N difference (differential output) is output. In addition, the current i2 corresponds to the current i1, and 値 is determined by the ratio of the size of the transistor (current mirror). That is, since the transistors 7a and 7b are current mirrors, the currents il and 2 in Fig. 2A are 値 proportional to the size of the transistors 7a and 7b. However, because the flow path of the signal is turned back, even if the current i flows into the transistors 3 and 4 in the circuit of the conventional example in FIG. 1, the current i 2 in the circuit of this embodiment in FIG. 2A is transmitted by the transistor 3 And 4 out. Therefore, in the conventional example in FIG. 1, the output signal N is taken out by the transistor 3, the output signal P is taken out by the transistor 4, and the output signal is taken out by the transistor 3 in FIG. 2A-10-200303115 P, The output signal N is taken out by the transistor 4. The transistors 8a and 8b also constitute a current mirror, and their operation is the same as that of the transistors 7a and 7b. Therefore, the currents of the input transistors 1 and 2 are transferred to the transistors 3 to 6 for gain control. In FIG. 2A, in order to suppress noise in the input transistors 1 and 2, a P-channel type can be used. In the above description, one terminal of the current source 21 and the transistors 3 to 6 for gain control are provided on the VDD side, and one terminal of the current transmission transistors 7a, 7b, 8a, and 8b is provided on the GND side, and vice versa One terminal of the current source 21 and the gain control transistor 3 to 6 is provided on the GND side, and one terminal of the current transmission transistor 7a, 7b, 8a, 8b may be provided on the VDD side. In the above configuration, if the resistance is passed once between VDD and GND and the transistor is passed twice, or the current source is passed once, the resistance is passed once, the transistor is passed twice, and VDD can reach GND. In the conventional amplification circuit of the figure, when the current passes through the current source once, the resistance is twice, and the transistor is twice passed from VDD to GND, compared with the case where the number of times through the resistor can be reduced by one, the partial voltage can be suppressed. The result is a linear output for a wider range of inputs. The configuration of the current source 21 is shown in FIG. 2B, and the voltage drop caused by the current source 21 in FIG. 2A is equivalent to a part of the transistor 11. Fig. 3 is a configuration of an AGC amplifier circuit according to another embodiment of the present embodiment. The parts in Figure 3 that overlap with Figures 2 A and 2 B are not explained. Fig. 3 is similar to Fig. 2A, and the circuit is separated by cutting off the arrow A of the conventional example circuit shown in Fig. 1. Then use foldable series connection structure -11-200303115 to connect the cut-off circuit, and make the transistor 3 ~ 6 used to input the gain control voltage or voltage fold back to the power supply side, so as to obtain the third largest circuit. In Fig. 3, a predetermined current i 3 is passed through 9a by a current source 22. Here, since the transistors 9a and 9b are current mirrors, the current i: 値 is distributed according to the ratio of the sizes of the transistors 9a and 9b (rati 〇). Since the transistors 9a and 9c are also current mirrors, Then the currents i 3 and i 5 are distributed according to the ratio of the sizes of the transistors 9a and 9c. The ratio of the sizes of the transistors 9a, 9b, and 9c is 1, and for example, when i 3 = 10 m A, i 4 = i 5 = 10 m A. At this time, if the current 输 i 2 of input 7 becomes 3 m A, the current 输入 i of the input signal P becomes 10%, U i6 = i5-i2 = 10-3 = 7mA, i7 = i4-il = 10-5 = 5mA 〇 The current of the input signal P and the current of the input signal N (2mA of i 2) are correctly transmitted to the gain control transistors 3 to 6 and become a difference from i 7. This means that the current i 7 corresponds to the current i 1 and that the current i 7 corresponds to the current i 2. That is, the currents i 4 and i 5 of the current i3 flowing through any one of the transistors 9 a and 9 b or 9 a] (specifically 9 a) of the current mirror are the electricity of the other side of the current mirror. The current i 1, i 5 flowing through the other transistor and the input transistors 1 and 2 in the crystal (specifically 9 b, 9 c) is the ratio corresponding to the size of the transistor. 1. The currents i 7 and i 6 of i 2 are obtained by 3 ~ 6 bows for gain control. Then, the currents of the input transistors 1 and 2 are transferred to the gain transistors 3 to 6. The discharge crystals 3 and i 4 of the reference electric diagram. In addition, if the signal N is 5 mA at 1, the input difference (5-3 = current i 6 current i 6 is corresponding to one of i 2 in Gen 9 c is used for transistor control -12- 200303115 In addition, when the circuit in FIG. 3 is compared with the conventional example in FIG. 1, the flow path of the letter is turned back. Therefore, in the circuit in FIG. 1, the current i flows into the bodies 3 and 4, but the current i in the circuit in FIG. 6 by transistors 3 and 4 € Figure 3 is the same as Figure 2A. Input channels 1 and 2 can be used to suppress noise. Also, in the above description, each current source 2 1 and 22 and gain One terminal of the control crystals 3 to 6 is provided on the VDD side, and one of the current transmission transistors 9 and 9 c is provided on the GND side. Conversely, one of the current sources 2 1 and 2 2 is used to control the transistor 3 to 6. On the GND side, one of the current transmitting crystals 9 a, 9 b, and 9 c may be provided on the VDD side. In the above-mentioned configuration, between VDD and GN D, the resistance is once and the body is twice, or the current source is passed through Once, the resistance is passed once, the transistor is passed twice, and VDD can reach GND. If the circuit of the conventional example shown in Fig. 1 is passed through the current source once, the resistance is passed twice, and the transistor is passed twice. Compared with the case of reaching GND, because the number of times through the resistor can be reduced, the voltage drop can be suppressed, and a linear output can be obtained for a wider range of inputs. The above description is based on the AGC amplifier circuit. The power supply and ground After the circuit is cut off, it is connected with a transistor for current transmission. The number of components connected in-line between grounds can be suppressed, and the range of output states can be expanded. However, this structure can also be used outside the AGC amplifier. For example, it can also be applied to a multiplication circuit. As shown in the above description, the present invention can achieve a semiconductor circuit with an input voltage range and a small distortion of the output waveform. No. of electric crystals. Power a, 9 b and additional power transistors are amplified by amplifying VDD once between the power supply and the input circuit-13-200303115 The present invention will be described below with reference to the drawings. The drawings briefly explain the previous enlargement of Figure 1. Circuit structure. Fig. 2A shows a structure of an amplifying circuit according to an embodiment of the present invention. Fig. 2B shows a detailed diagram of a current source. Fig. 3 shows another embodiment of an amplifying circuit according to an embodiment of the present invention. Configuration. The main part of the symbol for the transistor described 1,2,3~6
7a，7b，8a，8b，9a，9b，9c,11 電晶體 2 1 電流源 2 2 電流源 31，32,33,34 電阻 P，N 輸入信號 i 1 5 i 2 , i 3，i 4，i 5，i 6，i 7 電流7a, 7b, 8a, 8b, 9a, 9b, 9c, 11 Transistor 2 1 Current source 2 2 Current source 31, 32, 33, 34 Resistor P, N Input signal i 1 5 i 2, i 3, i 4, i 5, i 6, i 7 current
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