TW198109B - - Google Patents

Info

Publication number
TW198109B
TW198109B TW080106670A TW80106670A TW198109B TW 198109 B TW198109 B TW 198109B TW 080106670 A TW080106670 A TW 080106670A TW 80106670 A TW80106670 A TW 80106670A TW 198109 B TW198109 B TW 198109B
Authority
TW
Taiwan
Application number
TW080106670A
Other languages
Chinese (zh)
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Application granted granted Critical
Publication of TW198109B publication Critical patent/TW198109B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30072—Arrangements for executing specific machine instructions to perform conditional operations, e.g. using predicates or guards
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3846—Speculative instruction execution using static prediction, e.g. branch taken strategy

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Executing Machine-Instructions (AREA)
TW080106670A 1990-06-29 1991-08-22 TW198109B (OSRAM)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US54762990A 1990-06-29 1990-06-29

Publications (1)

Publication Number Publication Date
TW198109B true TW198109B (OSRAM) 1993-01-11

Family

ID=24185458

Family Applications (1)

Application Number Title Priority Date Filing Date
TW080106670A TW198109B (OSRAM) 1990-06-29 1991-08-22

Country Status (7)

Country Link
US (1) US6167509A (OSRAM)
EP (1) EP0463977B1 (OSRAM)
JP (1) JP2951064B2 (OSRAM)
KR (1) KR100190252B1 (OSRAM)
CA (1) CA2045791A1 (OSRAM)
DE (1) DE69129881T2 (OSRAM)
TW (1) TW198109B (OSRAM)

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US5732242A (en) * 1995-03-24 1998-03-24 Silicon Graphics, Inc. Consistently specifying way destinations through prefetching hints
US5951678A (en) * 1997-07-25 1999-09-14 Motorola, Inc. Method and apparatus for controlling conditional branch execution in a data processor
US6449713B1 (en) * 1998-11-18 2002-09-10 Compaq Information Technologies Group, L.P. Implementation of a conditional move instruction in an out-of-order processor
US6205544B1 (en) 1998-12-21 2001-03-20 Intel Corporation Decomposition of instructions into branch and sequential code sections
US6308322B1 (en) * 1999-04-06 2001-10-23 Hewlett-Packard Company Method and apparatus for reduction of indirect branch instruction overhead through use of target address hints
US6453389B1 (en) * 1999-06-25 2002-09-17 Hewlett-Packard Company Optimizing computer performance by using data compression principles to minimize a loss function
US6449706B1 (en) * 1999-12-22 2002-09-10 Intel Corporation Method and apparatus for accessing unaligned data
JP3940539B2 (ja) * 2000-02-03 2007-07-04 株式会社日立製作所 半導体集積回路
US6782469B1 (en) 2000-09-29 2004-08-24 Intel Corporation Runtime critical load/data ordering
US6662273B1 (en) 2000-09-29 2003-12-09 Intel Corporation Least critical used replacement with critical cache
US6760816B1 (en) * 2000-09-29 2004-07-06 Intel Corporation Critical loads guided data prefetching
US6785687B2 (en) 2001-06-04 2004-08-31 Hewlett-Packard Development Company, L.P. System for and method of efficient, expandable storage and retrieval of small datasets
US6907511B2 (en) * 2001-06-11 2005-06-14 Fujitsu Limited Reducing transitions on address buses using instruction-set-aware system and method
US7051168B2 (en) * 2001-08-28 2006-05-23 International Business Machines Corporation Method and apparatus for aligning memory write data in a microprocessor
US7203817B2 (en) 2001-09-24 2007-04-10 Broadcom Corporation Power consumption reduction in a pipeline by stalling instruction issue on a load miss
EP1442363A1 (en) * 2001-10-02 2004-08-04 Koninklijke Philips Electronics N.V. Speculative execution for java hardware accelerator
US7013382B1 (en) * 2001-11-02 2006-03-14 Lsi Logic Corporation Mechanism and method for reducing pipeline stalls between nested calls and digital signal processor incorporating the same
US7075462B2 (en) * 2002-08-07 2006-07-11 Lsi Logic Corporation Speeding up variable length code decoding on general purpose processors
US6925551B2 (en) * 2002-10-10 2005-08-02 International Business Machines Corporation Method, apparatus and system for accessing a global promotion facility through execution of a branch-type instruction
US7017031B2 (en) * 2002-10-10 2006-03-21 International Business Machines Corporation Method, apparatus and system for managing released promotion bits
US7483167B2 (en) * 2003-08-27 2009-01-27 Marvell International Ltd. Image forming apparatus for identifying undesirable toner placement
US7697169B2 (en) * 2004-10-29 2010-04-13 Marvell International Technology Ltd. Laser print apparatus with toner explosion compensation
US7694286B2 (en) * 2005-02-10 2010-04-06 International Business Machines Corporation Apparatus and method for detecting base-register usage conflicts in computer code
JP2007041837A (ja) * 2005-08-03 2007-02-15 Nec Electronics Corp 命令プリフェッチ装置及び命令プリフェッチ方法
US7243210B2 (en) * 2005-05-31 2007-07-10 Atmel Corporation Extracted-index addressing of byte-addressable memories
JP5103396B2 (ja) * 2005-08-23 2012-12-19 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド コンピュータシステムにおいて能動的に同期をとる方法
CN102077195A (zh) * 2008-05-08 2011-05-25 Mips技术公司 具有紧凑指令集架构的微处理器
US20100312991A1 (en) * 2008-05-08 2010-12-09 Mips Technologies, Inc. Microprocessor with Compact Instruction Set Architecture
US9158701B2 (en) 2012-07-03 2015-10-13 International Business Machines Corporation Process-specific views of large frame pages with variable granularity
US9405534B2 (en) 2013-01-21 2016-08-02 Tom Yap Compound complex instruction set computer (CCISC) processor architecture
US9110657B2 (en) 2013-01-21 2015-08-18 Tom Yap Flowchart compiler for a compound complex instruction set computer (CCISC) processor architecture
GB2519801A (en) 2013-10-31 2015-05-06 Ibm Computing architecture and method for processing data
US9772824B2 (en) * 2015-03-25 2017-09-26 International Business Machines Corporation Program structure-based blocking
US9934041B2 (en) 2015-07-01 2018-04-03 International Business Machines Corporation Pattern based branch prediction
CN114035850A (zh) * 2021-12-08 2022-02-11 苏州睿芯集成电路科技有限公司 一种基于risc-v的用于直接跳转的预编码设计方法及系统
JP7506718B2 (ja) 2022-08-05 2024-06-26 たけおかラボ株式会社 ジャンプ命令に基づくパイプライン処理を制御するプロセッサ及びプログラム
JP7421850B1 (ja) 2022-10-21 2024-01-25 たけおかラボ株式会社 間接アドレス指定方式の条件ジャンプ命令を実行するプロセッサ、プログラム及び方法
CN119668697B (zh) * 2024-12-06 2025-12-02 西安电子科技大学 一种基于预取的处理器加速取指方法及其装置

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* Cited by examiner, † Cited by third party
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US4777587A (en) * 1985-08-30 1988-10-11 Advanced Micro Devices, Inc. System for processing single-cycle branch instruction in a pipeline having relative, absolute, indirect and trap addresses
US4991080A (en) * 1986-03-13 1991-02-05 International Business Machines Corporation Pipeline processing apparatus for executing instructions in three streams, including branch stream pre-execution processor for pre-executing conditional branch instructions
JPH081602B2 (ja) * 1988-02-23 1996-01-10 三菱電機株式会社 データ処理装置
US5228131A (en) * 1988-02-24 1993-07-13 Mitsubishi Denki Kabushiki Kaisha Data processor with selectively enabled and disabled branch prediction operation
US5193205A (en) * 1988-03-01 1993-03-09 Mitsubishi Denki Kabushiki Kaisha Pipeline processor, with return address stack storing only pre-return processed address for judging validity and correction of unprocessed address
JPH0769814B2 (ja) * 1988-04-07 1995-07-31 三菱電機株式会社 パイプライン処理機構を持つデータ処理装置
US5136696A (en) * 1988-06-27 1992-08-04 Prime Computer, Inc. High-performance pipelined central processor for predicting the occurrence of executing single-cycle instructions and multicycle instructions
JPH0259822A (ja) * 1988-08-25 1990-02-28 Mitsubishi Electric Corp 命令先取り方式
US5131086A (en) * 1988-08-25 1992-07-14 Edgcore Technology, Inc. Method and system for executing pipelined three operand construct
US5050068A (en) * 1988-10-03 1991-09-17 Duke University Method and apparatus for using extracted program flow information to prepare for execution multiple instruction streams
US5113515A (en) * 1989-02-03 1992-05-12 Digital Equipment Corporation Virtual instruction cache system using length responsive decoded instruction shifting and merging with prefetch buffer outputs to fill instruction buffer
US5142634A (en) * 1989-02-03 1992-08-25 Digital Equipment Corporation Branch prediction
US5136697A (en) * 1989-06-06 1992-08-04 Advanced Micro Devices, Inc. System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache
US5163140A (en) * 1990-02-26 1992-11-10 Nexgen Microsystems Two-level branch prediction cache

Also Published As

Publication number Publication date
JPH06103067A (ja) 1994-04-15
EP0463977A2 (en) 1992-01-02
DE69129881T2 (de) 1999-04-01
JP2951064B2 (ja) 1999-09-20
DE69129881D1 (de) 1998-09-03
CA2045791A1 (en) 1991-12-30
KR100190252B1 (ko) 1999-06-01
EP0463977B1 (en) 1998-07-29
EP0463977A3 (en) 1993-09-22
US6167509A (en) 2000-12-26
KR920001321A (ko) 1992-01-30

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