TR201917294A2 - Tersi̇ni̇r ve korunumlu kapilardan yararlanilarak cmos devrelerde oluşan eş zamanli hatalarin tamami̇yle tespi̇ti̇ - Google Patents

Tersi̇ni̇r ve korunumlu kapilardan yararlanilarak cmos devrelerde oluşan eş zamanli hatalarin tamami̇yle tespi̇ti̇ Download PDF

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Publication number
TR201917294A2
TR201917294A2 TR2019/17294A TR201917294A TR201917294A2 TR 201917294 A2 TR201917294 A2 TR 201917294A2 TR 2019/17294 A TR2019/17294 A TR 2019/17294A TR 201917294 A TR201917294 A TR 201917294A TR 201917294 A2 TR201917294 A2 TR 201917294A2
Authority
TR
Turkey
Prior art keywords
reversible
cmos circuits
simultaneous faults
detection
doors
Prior art date
Application number
TR2019/17294A
Other languages
English (en)
Inventor
Parvin Sajjad
Altun Mustafa
Original Assignee
Univ Istanbul Teknik
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Univ Istanbul Teknik filed Critical Univ Istanbul Teknik
Priority to TR2019/17294A priority Critical patent/TR201917294A2/tr
Priority to US17/092,352 priority patent/US11307252B2/en
Publication of TR201917294A2 publication Critical patent/TR201917294A2/tr

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Geometry (AREA)
  • Evolutionary Computation (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Monitoring And Testing Of Exchanges (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

Buluş, tersinir ve korunumlu kapılar kullanılarak eşzamanlı (çevrimiçi) hataların CMOS devrelerde %100 tespitini sağlayan bir yöntem ile ilgilidir. Söz konusu yöntem ile CMOS devrelerinde oluşan hatalar maskelenmeden tespit edilebilmektedir.
TR2019/17294A 2019-11-07 2019-11-07 Tersi̇ni̇r ve korunumlu kapilardan yararlanilarak cmos devrelerde oluşan eş zamanli hatalarin tamami̇yle tespi̇ti̇ TR201917294A2 (tr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TR2019/17294A TR201917294A2 (tr) 2019-11-07 2019-11-07 Tersi̇ni̇r ve korunumlu kapilardan yararlanilarak cmos devrelerde oluşan eş zamanli hatalarin tamami̇yle tespi̇ti̇
US17/092,352 US11307252B2 (en) 2019-11-07 2020-11-09 Perfect detection of concurrent faults in CMOS circuits by exploiting reversible and preservative gates

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TR2019/17294A TR201917294A2 (tr) 2019-11-07 2019-11-07 Tersi̇ni̇r ve korunumlu kapilardan yararlanilarak cmos devrelerde oluşan eş zamanli hatalarin tamami̇yle tespi̇ti̇

Publications (1)

Publication Number Publication Date
TR201917294A2 true TR201917294A2 (tr) 2021-05-21

Family

ID=75846522

Family Applications (1)

Application Number Title Priority Date Filing Date
TR2019/17294A TR201917294A2 (tr) 2019-11-07 2019-11-07 Tersi̇ni̇r ve korunumlu kapilardan yararlanilarak cmos devrelerde oluşan eş zamanli hatalarin tamami̇yle tespi̇ti̇

Country Status (2)

Country Link
US (1) US11307252B2 (tr)
TR (1) TR201917294A2 (tr)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1004381B (it) 1974-03-15 1976-07-10 Sie Soc It Elettronica Dispositivo elettronico bistabile verificabile durante il servizio
JPS6029680A (ja) 1983-07-27 1985-02-15 Toshiba Corp Ｃｍｏｓ論理回路の試験方法
EP0249119A1 (de) 1986-06-10 1987-12-16 Siemens Aktiengesellschaft Aufwandsreduzierte Antivalenz-und Äquivalenz-Gatterschaltung zur Verwendung in aktiven Testhilfen für Schaltungsanordnungen in CMOS-Technik
JPH11145800A (ja) 1997-11-10 1999-05-28 Toshiba Corp Ｃｍｏｓ型可変遅延回路及びその遅延時間の制御方法並びに半導体試験装置
KR100360717B1 (ko) 2000-03-27 2002-11-13 김강철 Ｃｍｏｓ논리회로의 고장감지장치

Also Published As

Publication number Publication date
US11307252B2 (en) 2022-04-19
US20210141015A1 (en) 2021-05-13

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