TH8440B - Memory preservation system for devices with volatile memory. - Google Patents

Abstract

Memory preservation systems for electronic machines with multiple logical devices driven by oscillators, including one or more logic stabilization devices and oscillator stabilization devices. The router stops working while the power is down.

Claims (2)

1. The system maintains memory. Contains the first and second bias voltage sources. This will show the drop in voltage and the value during energy loss. First and second common circuits Each bias voltage input step is connected to receive the first and second bias voltage, respectively. And there is an input oscillator, each of which is connected together to receive a normal clock signal. Such a simple clock-generating oscillator consists of one component inside the first IC and the second external component of the first IC. Such oscillator parts Will be connected to the input terminal of Oscile The aforementioned IC-1 to provide the aforementioned clock signal at the first and second IC terminals. The aforementioned built-in memory path for data storage and about the loss of stored data at the aforementioned bias voltage. Shows the drop in the voltage during the energy loss and the capacitor path is connected to the bias voltage. Of the aforementioned IC to maintain the said first bias voltage for a predetermined period of time. During energy loss To prevent the loss of data stored in such a memory lane for at least a predetermined time. The aforementioned secondary ICs responds to the aforementioned voltage drop of the aforementioned second bias voltage during energy losses to provide a low impedance at the input source. The silencer of the second IC. Such low impedance loads the oscillator and stops generating the clock. 2. The system according to claim 1 also includes the methods incorporated into the said source. Of the aforementioned first and second bias voltages for the detection of such energy loss, such energy loss detection methods provide such a second bias voltage to the second IC. Such Switches that are connected to the said energy-loss sensing path To connect a selectable signal of the tuning signal to the setting terminal of the first IC In response to the said energy loss detection and the way it is connected to that energy loss detection path And connect to the aforementioned second IC To delay the drop in the aforementioned bias voltage arising from the energy loss to the said IC until after the set signal. It is connected to the first IC by the switch for the second preset time.