TH4826B - Powerful two-way buffer to latch, parity monitoring. - Google Patents

Abstract

A transient support circuit to detect and detect the parity of the data signal between the first and second data buses. Supports two-way pause bits bad bit support circuit Two-way multi-module, each circuit also has passage of information The first has a data receiver unit. Signal unit and driver unit The signals are connected in series between the first and second data buses. The second data corridor has a receiving unit. sensor data and the signal drive unit is connected in series between the data bus One with two control mechanisms to select the drive unit to make The signal is in a high impedance or active state and the coupling mechanism Controls that the data signal selects to capture or transmit through it. The signal generator circuit is always connected to the output side of the capture unit at the walk at one of the information of the temporary bit support circuit for The signal generator always responds to the data at the exit of the capture unit. Integrated signal transmission and signaling circuit Circuit breaks make the circuit pass signals faster and at the same time Don't need to increase the power consumption.

Claims (9)

1. A device for supporting transient data and for verifying the integrity of numeric data communicated between buses. First and second bus data Which consists of One of the two temporary bits is supported by a number of two temporary bits. One data corridor consisting of a receiver unit. With the input side of the first bus data bus and the The output is connected to the embodiment of the circuit center one. Available data capture units Connector to the center of the circuit to lock and hold the data. Placed at the center of the said circuit and the receiver unit with side Connect to the center of the said circuit and output to the bus. Second mulbus A path of information that consists of a receiver unit with The input side is connected to the data bus. The aforementioned second and output side are connected with The embodiment of one zero circuit Data capture unit that is connected to The embodiment of the circuit to selectively hold data at the center. The combination of the said circuit and the driver unit with the input side connected to The center of the aforementioned circuit and the output is connected to the first such bus data bus. Factors for controlling the aforementioned driver units to select the condition. Of the signal from the driving unit, the signal is in working condition Drive a high impedance signal or condition and a control factor for each capture unit to Optionally, hold data at the respective central cycle hubs. Or let the signal exit from the receiver unit At the center of the band The relevant center traffic changes the data at the center of the circuit. Related centers and The factor generating the fundamental state, which is connected to the center of the cycle of One such data path in the network supports bit data. Such two temporary circuits each. For responding to information At the center of the cycle of the first such passageway By always generating a signal, an underlying signal 2. Equipment according to claim 1, which also includes factors Check for faults connected to the output side of the generating factor. Such parity conditions for comparing such signals Always say to the second signal And create a warning signal Error of one signal when the signal is always the two data are not the same. 3. Equipment according to claim No. 2, in case of inspection factor Such errors consist of Only logic gate or any type (Exelusive-OR Gate), which has one inward side and the output of the factor And Factor for always transmitting such a second signal to The second input side of the logic gate or any of the above types. 4. Equipment according to claim 3, in case of factor for Sends a parity signal. The second signal consists of Secondary signal connector for receiving second signal as a second source of signal receiving unit, which has the input side to the signal connector. It is equal and has an output side to the second inward direction as Say of a logic gate or only one of these types and Equal state drive unit, which has the input side to the output of the factor Generates such an equation and has an output to the connector Such parallels 5. Equipment according to claim No. 4 in case of factor for Always transmit signal. The second such signal also consists of a unit. Receiving control signal, which has output side to control signal connector of The drive unit of such a constant state and the gate open signal connector. Placenta or only one such type, both poles 6. Equipment according to claim No. 1 in the event that the driver signal Each unit has a separate circuit which is connected to the receiving unit. Signals and data capture units relevant to them at the center of the said circuit 7. Equipment according to claim No. 1, in the event that the unit captures the data In each passageway of such information, there are also factors that are connected with A receiver unit in the path of that information to turn off in that receiver unit when it is captured Forced to hold data at the embodiment of the respective zero cycle. 8. Equipment for supporting temporary data and for verification. The equation state of numerical data communicated between the buses. The first and second bus data inside the computer, which There are at least two data buses for communicating. The device consists of a number of temporary two-way bits, each of which consists of One path of information, which consists of a receiver unit that There is an input side to the first bus data bus and an exit side. Connected to the embodiment of the circuit center one Terminal data capture unit Connect to the center of the circuit to select and hold data. At the embodiment of the said circuit and the driver unit with the input Connected to the embodiment of the said circuit And the output side is connected to the joint bus Second mulbus A second data passageway consisting of a receiver unit that There is an input side to the aforementioned second bus data bus and an exit side. With the embodiment of one zero circuit Data capture unit with connector With the embodiment of the said circuit when choosing to hold the data at The embodiment of the said circuit and the driver unit with the input side. With the embodiment of the said circuit And the output side is connected to the bus data bus That one Factors for controlling such signal drive units to select the condition Of the signal from the driving unit, the signal is in working condition Drive a high impedance signal or condition and a control factor for each capture unit to Optionally, hold data at the respective central cycle hubs. Or let the signal exit from the receiver unit As mentioned at the center The integration of the related center circuit, change the data at the embodiment of the related center circuit and The factor generating the fundamental state, which is connected to the center of the cycle of One such data path in the network supports bit data. These two transients, each cycle for responding to the information that The embodiment of the cycle of the first such data corridor. By always generating a signal, an underlying signal 9. Equipment according to claim No. 8 in the event that the driver signal Each unit has a separate circuit which is connected to the receiving unit. Signals and data capture units relevant to them at the center of the said circuit 1 0. Equipment according to claim No. 8 in the event that the unit catches the clause In each such data path there are also factors. Which is connected to the receiver unit in the path of the information that way when the receiver unit is turned off It was forced to hold the data at the center of the circuit center. Related (10 claims, 4 pages, 3 pictures)