TH41599A - Programmable memory type device with variable page size. - Google Patents

Abstract

DC60 (29/02/43), programmable memory-type device. That has been updated will allow Pages are defined within an array of memory cells that can vary in size and allow specific deletions. That data contained within a defined variable page while not affecting the rest of the data in the sequence of Memory cells and reprogrammed with the assigned variable pages. Can be re-programmed Improved page size with variable page size comprises an array of memory cells. Where the memory cells Are arranged in rows and columns, the logic of decoding numbers An address connected to an array of memory cells for accessing the array of memory cells, the logic of moving extends that Was connected with An array of memory cells for expanding the voltage levels between unit cells. A certain amount of memory and a data bus when accessing an array of memory cells, the logic for selecting a column connected to a memory cell array determines whether Any word from the selected row of the trunk row Outage of the memory cells that are being accessed and for each cell. A number of memory to the amplifier logic, the control signal is connected to the logic of the amplifier. For accessing an array of memory cells And the signal that opened the way for the right block Connected to the logic of Decode address numbers for varying page size within an array of memory cells to be deleted. Programmable memory-type devices. The improved allows pages within array memory cells to be variable in size. And allows for specific deletion That data contained within a defined variable page while not affecting the rest of the data in the sequence of Memory cells and reprogrammed with the assigned variable pages.Programmable memory type devices. Improved page size with variable page size comprises an array of memory cells. Where the memory cells Are arranged in rows and columns, the logic of decoding numbers An address that is connected to an array of memory cells for Accessing the array of memory cells, the logic of the path expands at Is connected to a memory cell array for amplifying the voltage level between a number of memory cells and the data bus.When accessing a memory cell array, the column selection logic is connected to an array of Unit cell Memory for determining that Any word from the selected row of the trunk row Off of the memory cell being accessed. And for per cell A number of memory to the amplifier logic, the control signal is connected to the logic of the amplifier. For accessing an array Of memory cells And the signal that opened the way for the blocked Connects to address decoding logic for varying page size within an array of memory cells to be deleted.

Claims (1)

1. A programmable memory-type device that includes An array of memory cells In which the memory cells are Arrange in rows and columns. Logic for decoding addresses connected to an array. Of a memory cell for accessing an array of amplified logic memory cells connected to an array of unit cells. Memory for amplifying voltage levels between Unit cells Memory and data bus When accessing an array of memory cells, the logic in selecting a column is connected to an array of Memory cells for tag: