TH40503A - Bandwidth tuning of a phase-locked loop. - Google Patents

Abstract

The DC60 phase-locked loop bandwidth is tuned to a desirable level by operating the phase-locked loop in phase-locked condition at a first frequency and applying a step response to the phase-locked loop, causing it to begin locking to a second frequency, different from the first. The parameters associated with the applied step response are then detected, indicating that the phase-locked loop bandwidth is at the desired level. The bandwidth is then adjusted, and the operating procedure at the first frequency, where the step response is applied, is repeated. The detection of parameters and adjustment of the phase-locked loop bandwidth is repeated until the bandwidth is at the desired level. When the desired bandwidth for tuning is not the operational bandwidth, the bandwidth is further adjusted by a predetermined amount. Thus, the phase-locked loop bandwidth is tuned to an operational level. The step response may be applied by changing the frequency division in the phase-locked loop feedback path. The detected parameter may be a pulse jump. This indicates that the bandwidth of the phase-locked loop is not yet at the desired level. The bandwidth of the phase-locked loop is tuned to the desired level by operating the phase-locked loop at a first frequency and applying a step response to the phase-locked loop by causing it to start logging at a second frequency, different from the first. Then, parameters related to the applied step response are detected, indicating that the bandwidth of the phase-locked loop is at the desired level. The bandwidth of the phase-locked loop is adjusted, and the operating procedure at the first frequency, applying the step response, parameter detection, and bandwidth adjustment are repeated until the bandwidth of the phase-locked loop is at the desired level. When the desired bandwidth for tuning is not the operational bandwidth, the bandwidth of the phase-locked loop is further adjusted by a predetermined amount. Thus, the bandwidth of the phase-locked loop is tuned to the operational level. This step response may be applied by changing the frequency division value in the phase-locked loop feedback path. The detected parameter may be a pulse jump, indicating that... The band width of this phase-locked loop is not yet at the desired band width level.

Claims (46)

1. The method for tuning the bandwidth of a phase-locked loop to a desired level consists of the following steps: a) making the phase-locked loop operate in phase-locked condition at a first frequency; b) applying a step response to the phase-locked loop, causing it to initially lock onto a second frequency different from the first; c) detecting parameters related to the applied step response, which indicate that the bandwidth of the phase-locked loop is at the desired level; and d) adjusting the bandwidth of the phase-locked loop, repeating steps a) to d) until the bandwidth of the phase-locked loop is at the desired level. 2. The method of Claim 1, which is further comprising a procedure for adjusting the band width of this phase-locked loop by a predetermined amount, thus fine-tuning the band width of this phase-locked loop to an operational level. 3. The method of claim 1, in which the procedure for bringing the step response to this phase-locked loop involves changing the frequency division value in the feedback path of this phase-locked loop. 4. The method of claim 1, where the parameter detection procedure relating to the response to the applied step, includes a step to detect whether a pulse jump has occurred. 5. The method of claim 4, in which the phase-locked loop bandwidth correction procedure and the repetition of steps a) through d) until the bandwidth of the phase-locked loop is at the desired level, shall consist of the phase-locked loop bandwidth correction procedure and the repetition of steps a) through d) until no pulse jumps are detected when the step response is applied to the phase-locked loop. 6. The method of claim 4, where the procedure for detecting whether an obscuring pulse jump occurs, shall consist of the following steps: detecting whether two leading edges of the phase-locked loop reference frequency signal occur in succession without the occurrence of an obscuring leading edge of the phase-locked loop feedback signal. 7. The method of claim 6, where the procedure for detecting whether an obscuring pulse jump occurs, shall consist of the following steps: detecting whether two leading edges of the phase-locked loop feedback signal occur in succession without the obscuring of the leading edge of the phase-locked loop reference frequency signal. 8. The method of claim 6, in which the procedure for detecting whether two leading edges of the phase-locked loop reference signal occur in succession without the occurrence of a phase-locked loop feedback leading edge, shall consist of the following steps: the use of the source reference signal in response to the occurrence of the first leading edge of the phase-locked loop reference signal; the use of the sync reference signal in response to the occurrence of the phase-locked loop feedback leading edge; the cessation of the use of the source and sync reference signals in response to the simultaneous use of the source and sync reference signals; and the detection of whether the source signal is simultaneously referenced with the occurrence of the second leading edge of the phase-locked loop reference signal. 9. The method of claim 8, where the procedure for determining whether the source signal is referenced concurrently with the emergence of the second leading edge of the reference frequency signal of this phase-locked loop, consists of the following steps: delaying the source signal by a predetermined quantity; and determining whether the delayed source signal is referenced concurrently with the emergence of the second leading edge of the reference frequency signal of this phase-locked loop. 10. The method of claim 4, where the procedure for detecting whether an obscuring pulse jump occurs, shall consist of the following steps: checking whether two leading edges of the phase-locked loop feedback signal occur in succession without the obscuring of the leading edge of the phase-locked loop reference frequency signal. 11. The procedure of claim 10, which involves the steps of detecting whether two leading edges of the phase-locked loop feedback signal occur consecutively without the occurrence of a leading edge of the phase-locked loop reference signal, consists of: using the source reference signal in response to the occurrence of the leading edge of the phase-locked loop reference signal; using the sync reference signal in response to the occurrence of the first leading edge of the phase-locked loop feedback signal; abandoning the source and sync reference signals in response to the simultaneous use of the source and sync reference signals; and detecting whether the sync signal is simultaneously used with the occurrence of the second leading edge of the phase-locked loop feedback signal. 12. The method of claim 11, where the procedure for determining whether the sync signal is cited concurrently with the occurrence of the second leading edge of the phase-locked loop feedback signal, shall consist of the following steps: delaying the sync signal by a predetermined amount; and determining whether the delayed sync signal is cited concurrently with the occurrence of the second leading edge of the phase-locked loop feedback signal. 13. The method of claim 1, which involves adjusting the band width of the phase-locked loop, includes steps for adjusting the output current of the charge pump. 14. The method of claim 13, in which the procedure for correcting the output current of the charge pumps is performed, involves correcting the output current of the charge pumps in steps that are logarithmically spaced apart from each other. 15. The method of claim 1, in which the parameter detection procedure relating to the response to this applied step shall include a procedure for detecting whether a predetermined number of pulse jumps has occurred, where this predetermined number is greater than one. 16. The method of claim 15, in which the phase-locked loop bandwidth correction procedure and the repetition of steps a) through d) until the phase-locked loop bandwidth is at the desired level, shall consist of the following steps: the phase-locked loop bandwidth correction procedure and the repetition of steps a) through d) until a number less than a predetermined number of pulse jumps is detected when a step response is applied to the phase-locked loop. 17. The method of claim 15, which involves the procedure for detecting whether a predetermined number of pulse jumps have occurred, shall consist of the following steps: the use of the detection reference whenever two leading edges of the phase-locked loop reference frequency signal occur in succession without the occurrence of a leading edge of the phase-locked loop feedback signal; the deactivation of this detection reference whenever two leading edges of this phase-locked loop reference frequency signal do not occur in succession without the occurrence of a leading edge of this phase-locked loop feedback signal; and the use of the pulse jump reference in response to this detection signal being used a predetermined number of times. 18. The method of claim 17, where the procedure for detecting whether a pulse skipping occurs, is further comprised of the following steps: the use of the detection reference whenever two leading edges of the phase-locked loop feedback signal occur in succession without the occurrence of a leading edge of the phase-locked loop reference signal; the deactivation of this detection reference whenever two leading edges of this phase-locked loop feedback signal do not occur in succession without the occurrence of a leading edge of this phase-locked loop reference signal; and the use of the pulse skipping reference in response to this detection signal being used a predetermined number of times. 19. The procedure of claim 17, whereby the steps of the detection reference whenever two leading edges of the phase-locked loop reference signal occur in succession without the occurrence of a leading edge of the phase-locked loop feedback signal, shall consist of the following steps: the reference of the source signal in response to the occurrence of the first leading edge of the phase-locked loop reference signal; the reference of the sync signal in response to the occurrence of a leading edge of the phase-locked loop feedback signal; the termination of the reference of both the source and sync signals in response to the simultaneous sampling of both signals; and the detection reference whenever the source signal is referenced simultaneously with the occurrence of the second leading edge of the phase-locked loop reference signal. 20. The method of claim 19, where the procedure for using the detection signal whenever the source signal is referenced concurrently with the emergence of the second leading edge of the phase-locked loop reference frequency signal, shall consist of the following steps: delaying the source signal by a predetermined quantity; and using the detection signal whenever the delayed source signal is referenced concurrently with the emergence of the second leading edge of the phase-locked loop reference frequency signal. 21. The method of claim 15, where the procedure for detecting whether a predetermined number of pulse jumps has occurred, shall consist of the following steps: the use of the detection reference whenever two leading edges of the phase-locked loop feedback signal occur in succession without the occurrence of a leading edge of the phase-locked loop reference signal; the deactivation of this detection reference whenever two leading edges of this phase-locked loop feedback signal do not occur in succession without the occurrence of a leading edge of this phase-locked loop reference signal; and the use of the pulse jump reference in response to this detection signal being used a predetermined number of times. 22. The procedure of claim 21, which states that the detection reference whenever two leading edges of the phase-locked loop feedback signal occur in succession without the occurrence of a leading edge of the phase-locked loop reference signal, shall consist of the following steps: the use of the source reference signal in response to the occurrence of the leading edge of the phase-locked loop reference signal; the use of the sync reference signal in response to the occurrence of the first leading edge of the phase-locked loop feedback signal; the termination of the source and sync reference signals in response to the simultaneous sampling of the source and sync signals; and the use of the detection reference whenever the sync signal is referenced simultaneously with the occurrence of the second leading edge of the phase-locked loop feedback signal. 23. The method of claim 22, which the procedure for referencing the detection signal whenever this sync signal is referenced simultaneously with the occurrence of the second leading edge of the phase-locked loop feedback signal, shall consist of the following steps: delaying the sync signal by a predetermined amount; and referencing the detection signal whenever this delayed sync signal is referenced simultaneously with the occurrence of the second leading edge of the phase-locked loop feedback signal. 24. The device consists of: a phase-locked loop that generates an output signal whose frequency is a function of the reference frequency and feedback factor; and a pulse skipping detector coupled to this phase-locked loop, which generates a pulse skipping signal indicating whether an obstructed pulse skipping has occurred in this phase-locked loop, where this phase-locked loop contains a controllable charge pump; and a) making this phase-locked loop operate in a phase-locked state at a first frequency; b) applying a feedback response to this phase-locked loop by causing it to initially lock onto a second frequency different from the first; c) using the pulse skipping signal generated by the pulse skipping detector to determine whether an obstructed pulse skipping has occurred, where the occurrence of an obstructed pulse skipping indicates whether the band width of this phase-locked loop is at an acceptable level; and d) correcting the band width of this phase-locked loop by adjusting the output current of the controllable charge pump. And repeat steps a) through d) until the band width of this phase-locked loop is at this desired level. 25. The instrument of claim 24, after the band width of the phase-locked loop has been at the desired level, further adjusts the output current of the controllable charge pump by a predetermined amount, thus fine-tuning the band width of the phase-locked loop to an operational level. 26. The instrument of claim 24 in which this controller applies the step response to the phase-locked loop by changing the feedback factor in the feedback path of this phase-locked loop. 27. The device comprises: a phase-locked loop that generates an output signal whose frequency is a function of the reference frequency and feedback factor; and a pulse skipping detector coupled to the phase-locked loop, which generates a pulse skipping signal indicating whether a certain number of pulse skips have occurred in the phase-locked loop, where X is a predetermined number, in which the phase-locked loop contains a controllable charge pump; and further comprises a controller for: a) making the phase-locked loop operate in a phase-locked state at a first frequency; b) applying a step response to the phase-locked loop by causing it to initially lock onto a second frequency different from the first; c) using the pulse skipping signal generated by the pulse skipping detector to determine whether a pulse skip has occurred, where the occurrence of a pulse skip indicates whether the band width of the phase-locked loop is at an acceptable level; and d) Adjusting the band width of this phase-locked loop by adjusting the output current of this controlled charging device, and repeating steps a) to d) until the band width of the phase-locked loop is at the desired level. 28. The instrument of claim 27, after the band width of this phase-locked loop has been reached to the desired level, further adjusts the output current of the controllable charge pump by a predetermined amount, thus fine-tuning the band width of the phase-locked loop to an operational level. 29. The instrument of claim 27 in which this controller applies the step response to the phase-locked loop by changing the feedback factor in the feedback path of this phase-locked loop. 30. A product of manufacturing that includes a computer-readable data storage medium containing computer-readable program paths that enable the tuning of the phase-locked loop to a desired level. These computer-readable program paths in such product of manufacturing shall include: a) a computer-readable program path for enabling the computer to operate the phase-locked loop in phase-locked state at a first frequency; b) a computer-readable program path for enabling the computer to apply a layer response to the phase-locked loop, causing it to initialize at a second frequency different from the first; c) a computer-readable program path for enabling the computer to detect parameters related to the applied layer response, and thus determine whether the phase-locked loop bandwidth is at the desired level; and d) a computer-readable program path for enabling the computer to adjust the phase-locked loop bandwidth. And to repeat the operation of the computer-readable program code a) through d) until the band width of this phase-locked loop is at the desired level. 31. The product of the production of claim 30, which also includes a means of computer-readable program code for enabling the computer to adjust the band width of this phase-locked loop by a predetermined amount, thus fine-tuning the band width of this phase-locked loop to an operational level. 32. The product of the production of claim 30, in which the computer-readable program code path for causing the computer to apply a step response to the phase-locked loop, shall include the computer-readable program code path for causing the computer to change the frequency division value in this phase-locked loop feedback path. 33. The product of the production of claim 30, where the computer-readable program code path for enabling the computer to detect parameters relating to the applied step response, includes the computer-readable program code path for enabling the computer to detect whether a pulse jump has occurred. 34. The product of the production of claim 33, where the computer-readable program code path for enabling the computer to adjust the band width of this phase-locked loop and the band width of this phase-locked loop is at a desired level, includes the computer-readable program code path for enabling the computer to adjust the band width of the phase-locked loop and the operation of computer-readable program code paths a) through d) is performed until no pulse jump is detected. When a step response is applied to this phase-locked loop, the phase detector uses the phase detector signal as a reference for the response. In response to the emergence of the first leading edge of the reference frequency signal, the phase detector ceases to use the phase detector signal as a reference in response to the emergence of the leading edge of the divided feedback signal, and the pulse jump detector receives the phase detector signal and generates from this signal a delayed phase detector signal, and generates a pulse jump signal when this delayed phase detector signal is simultaneously referenced in response to the emergence of the second leading edge of this reference frequency signal. 29. The instrument of claim 28 in which the pulse jump detector is located shall consist of a delay block for receiving the phase detector signal and generating from this signal a delayed phase detector signal, and a flip-flop with a coupled data input to receive the delayed phase detector signal and a coupled clock input to receive the reference frequency signal. With this, the output of the flip-flop shall indicate the pulse jump. This pulse occurs in this phase-locked loop. 30. The device of claim 25, in which the phase detector uses the phase detector signal as a reference in response to the occurrence of the first leading edge of the divided feedback signal, the phase detector ceases to use the phase detector signal as a reference in response to the occurrence of the leading edge of the reference frequency signal, and the phase-skip detector generates a pulse jump signal when this phase detector signal is simultaneously referenced in response to the occurrence of the second leading edge of this divided feedback signal. 31. The device of claim 30, in which the pulse-skip detector consists of a flip-flop with a data input coupled to receive the phase detector signal and a clock input coupled to receive the divided feedback signal. The output of this flip-flop indicates when a pulse jump has occurred. 32. The device of claim 25, in which the phase detector takes the phase detector signal as a reference in response to the occurrence of the first leading edge of the divided feedback signal, the phase detector ceases to take the phase detector signal as a reference in response to the occurrence of the leading edge of the reference frequency signal, and the pulse jump detector receives the phase detector signal and generates from this signal a delayed phase detector signal, and generates a pulse jump signal when this delayed phase detector signal is simultaneously referenced in response to the occurrence of the second leading edge of the divided feedback signal. 33. The device of claim 32, in which the pulse jump detector consists of a delay block for receiving the phase detector signal and generating from this signal a delayed phase detector signal, and a flip-flop with a coupled data input to receive the delayed phase detector signal and a coupled clock input to receive the delayed phase detector signal. The reference frequency signal; with this, the output of this flip-flop indicates that the jump of this pulse occurs in this phase-locked loop. 34. The instrument of claim 24 which: shall include a controllable charge pump device, and which shall further include a controller for: a) causing the phase-locked loop to operate in a phase-locked state at a first frequency; b) applying a step response to the phase-locked loop by causing it to initially lock into a second frequency different from the first; c) using a pulse skipping signal generated by a pulse skipping detector to determine if an obstructed pulse skip has occurred, which indicates that the bandwidth of the phase-locked loop is at a desirable level; and d) correcting the bandwidth of the phase-locked loop by adjusting the output current of the controllable charge pump device and repeating steps a) to d) until the bandwidth of the phase-locked loop is at a desirable level. 35. The instrument under claim 34, after the phase-locked loop bandwidth has been attained to the desired level, further corrects the output current of the controllable charge pump by a predetermined amount, thus fine-tuning the phase-locked loop bandwidth to an operational level. 36. The device under claim 34, in which the controller applies the step response to the phase-locked loop by changing the feed factor in the feedback path of this phase-locked loop. 37. A device consisting of: a phase-locked loop which generates an output signal whose frequency is a function of the reference frequency and the feedback factor; and a pulse jump detector coupled to the phase-locked loop which generates a pulse jump signal indicating the number of pulse jumps X that occur in this phase-locked loop, where X is a predetermined number. 38. The instrument of claim 37, which is a pulse jump detector, shall consist of: a single pulse jump detection path for the generation of the first signal which is referenced each time a pulse jump is detected; a coupled frequency divider to receive this first signal for the generation of this first signal as a pulse jump signal which is referenced for every X number of references of this first signal. 39. The instrument of claim 37 which: shall include a controllable charge pump device, and which shall further include a controller for: a) causing the phase-locked loop to operate in a phase-locked state at a first frequency; b) applying a step response to the phase-locked loop by causing it to initially lock into a second frequency different from the first; c) using the pulse jump signal generated by the pulse jump detector to determine the number of pulse jumps that have occurred, which indicates that the band width of the phase-locked loop is at the desired level; and d) correcting the band width of the phase-locked loop by adjusting the output current of the controllable charge pump device and repeating steps a) to d) until the band width of the phase-locked loop is at the desired level. 40. The instrument of claim 39, after the band width of the phase-locked loop has been attained to the desired level, further corrects the output current of the controllable charge pump by a predetermined amount, thus fine-tuning the band width of the phase-locked loop to an operational level. 41. The device under claim 39, in which the controller applies a step response to the phase-locked loop by changing the feed factor in the feedback path of this phase-locked loop. 42. A production item consisting of a computer-readable program medium containing computer-readable program paths that are modeled within it for tuning the bandwidth of a phase-locked loop to a desired level. These computer-readable program paths in such a production item shall consist of: a) a computer-readable program path for causing the computer to operate the phase-locked loop at a first frequency; b) a computer-readable program path for causing the computer to apply a step response to the phase-locked loop, causing it to initialize at a second frequency, different from the first; c) a computer-readable program path for causing the computer to interact with the applied step response, indicating that the bandwidth of the phase-locked loop is at the desired level; and d) a computer-readable program path for causing the computer to adjust the bandwidth of the phase-locked loop and to repeat operations a) through d) until the bandwidth of the phase-locked loop is reached. This phase-locked loop is at a desirable level. 43. The product of claim 42, which is further comprised of a method of computer-readable program code for enabling the computer to adjust the band width of this phase-locked loop by a predetermined amount, thus fine-tuning the band width of this phase-locked loop to an operational level. 44. The product of claim 42, which is a computer-readable program code path for enabling the computer to apply a step response to a phase-locked loop, shall consist of a computer-readable program code path for enabling the computer to change the frequency division value in the feedback path of the phase-locked loop. 45. The product of claim 42, which is a computer-readable program code path for enabling the computer to detect parameters relating to the response to an implemented step, shall consist of a computer-readable program code path for enabling the computer to detect that a pulse jump has occurred. 46. The product of claim 42, which is a computer-readable program code path for causing the computer to adjust the band width of this phase-locked loop and the operation of computer-readable program code paths a) through d), until the band width of this phase-locked loop is at the desired level, shall consist of a computer-readable program code path for causing the computer to adjust the band width of this phase-locked loop and the operation of computer-readable program code paths a) through d), until no pulse skips are detected when the step response is applied to this phase-locked loop.