KR20210092412A - Frequency Synthesizer With Auto Frequency Calibrator Robust To Initial Phase Error - Google Patents

Abstract

The present invention relates to a frequency synthesizer that activates an automatic frequency correction circuit when an initial phase difference between a reference frequency and a frequency-divided frequency is within a predetermined range in order to prevent a designation error of an output correction code. The present invention has an effect that can solve a problem wherein a settling time of the frequency synthesizer is very long or an unlock state may occur by detecting the initial phase relationship of the reference frequency and the divided frequency and activating the automatic frequency correction circuit when located within a predetermined range. The frequency synthesizer comprises: a phase loop circuit; an automatic frequency correction circuit; and a frequency phase determination part.

Description

Frequency Synthesizer With Auto Frequency Calibrator Robust To Initial Phase Error

The present invention relates to a frequency synthesizer including an automatic frequency correction device capable of reducing an error of an initial phase, and more particularly, to prevent a designation error of an output correction code, an initial phase difference between a reference frequency and a divided frequency is predetermined It relates to a frequency synthesizer that activates an automatic frequency correction circuit when located within the range of

Next-generation wireless communication such as 5G is being developed, and as the use of high-bandwidth frequencies is gradually expanded, interest in high frequency is increasing. In general, a wireless communication device uses a high-frequency (Radio Frequency) transceiver, and the high-frequency transceiver fixes a frequency using a phase locked loop (PLL).

Although a voltage controlled oscillator (VCO) is used as a frequency source of the phase locked loop (PLL), there is a problem in that the output frequency is slightly changed due to the influence of the circuit, the influence of the surrounding equipment, the influence of temperature and weather, and the like. In order to solve this problem, the phase-locked loop (PLL) includes a divider for comparing the frequency divided by the output frequency with the reference frequency, and an output correction code by counting the reference frequency and the divided frequency to adjust the output frequency. An Auto Frequency Calibrator (AFC) designated by any one of them is used.

Korean Patent Registration No. 10-0532476 (hereinafter referred to as 'prior literature') relates to a frequency synthesizer using a wide-band voltage controlled oscillator and a fast adaptive frequency correction technique. By selecting one of the operating characteristic curves from among them, the setting time of the frequency synthesizer is controlled quickly and accurately.

However, since the automatic frequency compensator uses a digital counter method, an error may occur at the time of completion of counting depending on the initial phase relationship between the reference frequency and the frequency division. Hereinafter, errors that may be generated in a frequency synthesizer including a conventional automatic frequency correction circuit will be described with reference to FIGS. 1 to 5 .

1 is a view showing a frequency synthesizer including a conventional automatic frequency correction device. Conventional frequency synthesizer has a reference frequency crystal oscillator (TCXO), the output frequency (f _o) the output of voltage control oscillator (VCO), the output frequency (f _o) a frequency divider frequency divider to that (N) for generating a (f _REF) the reference frequency (f _REF) with a divided frequency (f _DIV) for comparing the phase detector and the charge pump of frequency dividing and (PFD / CP) of the phase loop circuit (PLL) it includes a to (f _DIV) with a reference frequency (f a counter (CNT), a reference frequency (f _REF) and the comparator (comparator) for specifying any one of a plurality of operating characteristic curve of the output correction code assigned in response to the comparison of the divided frequency (f _DIV) for counting the _REF), It may consist of an automatic frequency correction circuit (AFC) including a state machine that transmits a digital signal for a specified output correction code.

_{1 is a case in which a reference frequency f REF} of 5 MHz is generated in a crystal oscillator (Temperature Compensated X-tal Oscillator; TCXO), and the output frequency f _o is 2455 MHz. The crystal oscillator (TCXO) is hardly affected by external temperature and is an oscillator capable of stably maintaining a desired output frequency, and can generate a frequency of a low frequency band.

A value of 491 in which the output frequency of 2455 MHz is divided by 5 MHz, which is the reference frequency, is assigned to the divider of the phase loop circuit (PLL). A phase detector and a charge pump (PFD / CP) is corresponding to a difference between the reference frequency (f _REF) and comparing the divided frequency (f _DIV), a divided frequency (f _DIV) with a reference frequency (f _REF) pulse value create In the embodiment of FIG. 1 , the digital signal is 100, and there is no phase difference between the _{frequency f DIV} and the reference frequency f _{REF in which} the period of the reference frequency of 5 MHz is 200 ns and the period of 491/2455 MHz is 200 ns.

The reference frequency f _REF is fixed at a period of 200 ns as it is generated by the crystal oscillator (TCXO), but the output frequency of 2455 MHz is a high frequency and may be minutely changed according to the external environment. Therefore, if the value of the output frequency (f _o ) is changed, the phase detector and the charge pump (PFD/CP) generate a pulse value corresponding to the difference between the _{divided frequency (f DIV} ) and the reference frequency (f _{REF ).} The pass filter (LPF) varies the input voltage input to the voltage controlled oscillator (VCO) according to the generated pulse value.

2 is a view for explaining the operation of the frequency synthesizer according to the change of the conventional output frequency, when the output frequency (f _o ) is changed from 2455MHz to 2460MHz. Referring to FIG. 2 , the divider is changed to a division ratio of 492 in which an output frequency of 2460 MHz is divided by a reference frequency of 5 MHz, and the voltage-controlled oscillator (VCO) receives the intermediate power (V _DD /2) of the current output correction code.

The counter CNT counts the frequency and the reference frequency divided by the division ratio corresponding to the frequency at which the frequency of the intermediate power of the current output correction code is to be changed. A comparator generates a change signal of the output correction code by determining whether a time difference between the period of the divided frequency and the period of the reference frequency satisfies a preset time difference.

Hereinafter, designation of the output correction code according to the change of the output frequency will be described with reference to FIGS. 3 to 4 .

3 is a case in which the digital signal of the currently designated output correction code among the output correction codes to which a plurality of operation characteristic curves is assigned is 100, and _{the frequency of the Vc voltage (intermediate power supply V DD} /2) is 2430 MHz. Therefore, the divided frequency is 492/2430MHz with a period of 202.47ns, and has a difference of 2.47ns from the reference frequency.

The comparator compares the time difference for the period counter number of 16, 32, and 64 with the time difference between 127.5ns, which is three times the period 42.5ns for _{f AFC_clk (230MHz).} It can be seen that the period counter number 16 of FIG. 3 is 39.52 ns, 32 is 79.04 ns, and 64 is 158.08 ns, and the number of period counters 16 and 32 has a time difference within 127.5 ns, but 64 is out of the time difference of 127.5 ns. A comparator generates a change signal for 'UP' the output correction code.

4 is a case in which the existing digital signal of 100 is changed to 011 by the output correction code 'UP'. _{The frequency for the intermediate power (V DD} /2) of the output correction code corresponding to the digital signal 011 is 2444 MHz with a period of 201.3 ns, and has a difference of 1.3 ns from the _{reference frequency (f REF ).}

Accordingly, in FIG. 4, the number of period counters 16 is 20.8 ns, 32 is 41.6 ns, and 64 is 83.2 ns, and all of the period counters 16, 32, and 64 have a time difference within 127.5 ns. The comparator 'Stop' the output correction code in the digital signal 011, and the state machine transmits the digital signal 011 to the voltage controlled oscillator (VCO). The voltage-controlled oscillator (VCO) generates a frequency of 2460 MHz through an output correction code corresponding to the digital signal 011.

Although the operation of the conventional frequency synthesizer including the automatic frequency has been described above with reference to FIGS. 1 to 4 , the conventional frequency synthesizer outputs according to the initial phase relationship between the _{reference frequency (f REF} ) and the _{divided frequency (f DIV )} There is a problem that an error in changing the correction code may occur.

5 is a diagram illustrating an error in changing an output correction code according to an initial phase relationship. Referring to FIG. 5 , it can be seen that there is an initial phase difference of 90θ between the _{reference frequency f REF} and the frequency _{divided frequency f DIV .} So, in digital 100, the period counter count of 16 is -50.48 ns (39.52-90), 32 is -10.96 ns (79.04-90), 64 is 68.08 ns (158.08-90), and the period counter counts 16, 32, and 64 are all 127.5 There is a time difference within ns. If the initial phase difference is 0, it must be changed to a digital signal of 011 in order to change the output frequency to 2460 MHz, but if there is an initial phase difference of 90° between the _{reference frequency (f REF} ) and the _{divided frequency (f DIV ), digital} There is a problem that the signal is not changed. Therefore, as an incorrect output correction code is set, the settling time of the frequency synthesizer may be very long or an unlock state may occur.

Korean Patent Registration No. 10-0532476 (Title of the invention: Wide-band voltage controlled oscillator and frequency synthesizer using fast adaptive frequency correction method, registration date: November 24, 2005)

An object of the present invention is to provide a frequency synthesizer capable of reducing an initial phase relationship between a reference frequency and a frequency-divided frequency in order to solve the above problems.

The frequency synthesizer including an automatic frequency correction device robust to an initial phase error according to the present invention prevents an output frequency generated according to an input voltage from being changed by an external environment, and divides the reference frequency and the output frequency to be set A phase loop circuit for changing the output frequency by comparing the frequency divided by the ratio, an automatic frequency correction circuit for counting the reference frequency and the divided frequency to designate a synthesis range of the frequency as any one of the designated output correction codes, and the In order to prevent a designation error of the output correction code, when the initial phase difference between the reference frequency and the frequency-divided frequency satisfies a preset condition, a frequency phase determination unit for activating the automatic frequency correction circuit may be included.

The frequency phase determining unit according to the present invention is a first sequential logic circuit in which a rising signal is output at the rising clock edge of the reference frequency, and a rising signal at the rising clock edge of the frequency divided by the division ratio corresponding to the output frequency to be set. A second sequential logic circuit to be output, a first delay unit configured to initialize the first sequential logic circuit after controlling the signal output from the first sequential logic circuit to be output for a preset time, in the second sequential logic circuit After controlling the output signal to be output for a preset time, when a rising signal is simultaneously inputted from the second delay unit for initializing the second sequential logic circuit, the first sequential logic circuit and the second sequential logic circuit, another and a logic circuit gate for outputting a rising signal, and another sequential logic circuit for generating a control signal for operating the automatic frequency correction circuit when the rising signal is output from the logic circuit gate.

In the automatic frequency correction circuit according to the present invention, when the control signal is received from the another sequential logic circuit, a counter for counting the frequency divided by the division ratio corresponding to the reference frequency and the output frequency to be set, the divided A comparator for generating a change signal of the output correction code by determining whether a time difference between a frequency period and a period of the reference frequency satisfies a preset time difference, a state of transmitting a digital signal corresponding to the change signal to the voltage-controlled oscillator includes machine.

The phase loop circuit according to the present invention includes a crystal oscillator for generating the reference frequency, a voltage-controlled oscillator for outputting the output frequency according to the input voltage, a divider for dividing by a division ratio corresponding to the output frequency, and the divider A phase detector and charge pump that compares the frequency divided by , and the reference frequency generated by the crystal oscillator, and generates a pulse value corresponding to the difference between the divided frequency and the reference frequency, and the generated pulse value and a low-pass filter for varying an input voltage input to the voltage-controlled oscillator.

The present invention provides a frequency synthesizer capable of reducing the initial phase relationship between a reference frequency and a divided frequency, thereby preventing an error in changing an output correction code, and the settling time of the frequency synthesizer is very long or unlocked (Unlock) has the effect of solving problems that may occur.

1 is a view showing a frequency synthesizer including a conventional automatic frequency correction device.
2 is a view for explaining the operation of the conventional frequency synthesizer according to the change of the output frequency.
3 to 4 are diagrams for explaining the designation of an output correction code according to a conventional output frequency change.
5 is a diagram illustrating an error in changing an output correction code according to an initial phase relationship.
6 is a block diagram of a frequency synthesizer including an automatic frequency correction device robust to an initial phase error according to the present invention.
7 is a diagram illustrating a condition of a phase difference between a reference frequency and a frequency-divided frequency for controlling the automatic frequency correction device according to the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In describing an embodiment of the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

6 is a block diagram of a frequency synthesizer including an automatic frequency correction device robust to an initial phase error according to the present invention.

Referring to FIG. 6 , the frequency synthesizer may include a phase loop circuit (PLL), an automatic frequency correction circuit (AFC), and a frequency phase determination unit.

The phase loop circuit PLL may include a crystal oscillator 110 , a voltage controlled oscillator 120 , a divider 130 , a phase detector and a charge pump 140 , and a low-pass filter 150 . The configuration of the phase loop circuit PLL will be briefly described as the configuration described above.

The crystal oscillator 110 is _{configured to generate a reference frequency f REF} , and can stably generate a frequency of a low frequency band. The voltage-controlled oscillator 120 outputs an output frequency f _o according to the input voltage, and is designated as any one of the output correction codes to which a plurality of operating characteristic curves are assigned. The divider 130 _{divides by a division ratio corresponding to the output frequency f o} . For example, when the input frequency is 5 MHz and the output frequency is 2455 MHz, it has a division ratio 491. The phase detector and charge pump 140 compares the frequency divided by the divider 130 with the reference frequency f _REF generated by the crystal oscillator 110 , and the divided frequency _{f DIV and the reference frequency f REF} ) to generate a pulse value corresponding to the difference. For example, if the period T of the divided frequency _{f DIV is smaller than the period T of the reference frequency f REF} , a voltage lower than the current input voltage is applied _{, and the divided frequency f DIV} ) If the period T of the reference frequency f _REF is greater than the period T of the reference frequency f REF , a voltage higher than the current input voltage is applied. The low-pass filter 150 varies the input voltage input to the voltage-controlled oscillator 120 according to the generated pulse value.

When the output frequency (f _o ) is being fixed, the voltage-controlled oscillator 120 and the low-pass filter 150 are connected, but when the output frequency ( _fo ) is changed, the voltage-controlled oscillator 120 is the middle of the current output correction code. It is connected to the power supply (V _DD /2).

The frequency phase determination unit controls the automatic frequency correction circuit when the phase difference between _{the reference frequency (f REF} ) and the _{frequency-divided frequency (f DIV} ) satisfies a preset condition in order to prevent a designation error of the output correction code. The frequency phase determination unit includes a first sequential logic circuit 211 , a second sequential logic circuit 212 , a first delay unit 221 , a second delay unit 222 , a logic circuit gate 230 , and another sequential logic circuit. (240).

The first sequential logic circuit 211 _{outputs a high signal ('logic 1') at the rising clock edge of the reference frequency f REF} , and the second sequential logic circuit 212 is the intermediate power V of the current output correction code. _A high signal ('logic 1') is output at the edge of the rising clock of the frequency corresponding to DD /2).

The first delay unit 221 initializes the first sequential logic circuit 211 after controlling the high signal ('logic 1') output from the first sequential logic circuit 211 to be output for a preset time, The second delay unit 222 initializes the second sequential logic circuit 212 after controlling the high signal ('logic 1') output from the second sequential logic circuit 212 to be output for a preset time. For example, when the time set in the first delay unit 221 and the second delay unit 222 is 15 ns, the first sequential logic circuit 211 sets a time width of 15 ns for each rising clock edge _{of the reference frequency f REF .} The branch is initialized after outputting a high signal ('logic 1'), and the second sequential logic circuit 212 is a high signal ('logic 1') having a time width of 15 ns for every rising clock edge of the divided _{frequency f DIV .} It is initialized after outputting . The time set in the first delay unit 221 and the second delay unit 222 may be arbitrarily set by the user.

The logic circuit gate 230 outputs a high signal ('logic 1') when signals are simultaneously input from the first sequential logic circuit 211 and the second sequential logic circuit 212 . The logic circuit gate 230 is preferably configured as an AND gate that outputs a hign signal ('logic 1') when two high signals ('logic 1') are input.

Another sequential logic circuit 240 operates the automatic frequency correction circuit when a high signal ('logic 1') is output from the logic circuit gate 230 . On the other hand, the first sequential logic circuit 211, the second sequential logic circuit 212, and another sequential logic circuit 240 are D- to output a hign signal ('logic 1') when a specific signal is input. It is preferably configured as a flipflop.

7 is a diagram illustrating a condition of a phase difference between a reference frequency and a frequency-divided frequency for controlling the automatic frequency correction device according to the present invention. The configuration of the frequency phase determination unit of the present invention can be made clearer through the following description.

[When activating the automatic frequency correction circuit]

Looking at the case of activating the automatic frequency correction circuit of FIG. 7 , the first sequential logic circuit 211 is in an initialized state (0), and a high signal ('logic 1') is generated at the rising clock edge of the _{reference frequency f REF .} create Here, the output time of the first sequential logic circuit 211 and the second sequential logic circuit 212 is set to 15 ns.

The second sequential logic circuit 221 was also in the initialized state (0), but after 9 ns after the signal was output from the first sequential logic circuit 211, at _{the rising clock edge of the division frequency f DIV} , the hign signal ('logic 1') ') is printed. As the hign signal ('logic 1') is output from the second sequential logic circuit 212 while the high signal ('logic 1') is output from the first sequential logic circuit 211, the logic circuit gate 230 is high Output a signal ('logic 1').

[When the automatic frequency correction circuit is not activated]

Looking at the case in which the automatic frequency correction circuit of FIG. 7 is not activated, the first sequential logic circuit 211 is in an initialization state (0), and a high signal ('logic 1') at the rising clock edge of the _{reference frequency f REF .} create

On the other hand, the second sequential logic circuit 212 was also in the initialized state (0), but after 20 ns after the high signal ('logic 1') output from the first sequential logic circuit 211 is reset, the frequency division frequency f _DIV ) outputs a hign signal ('logic 1') at the rising clock edge. Even when the hign signal 1 is output from the second sequential logic circuit 212, the first sequential logic circuit 211 is a low signal ('logic 0'), so that the logic circuit gate 230 generates a high signal ('logic 1'). ') is not output.

As described above, the present invention determines whether the phase difference between the two signals input to the first sequential logic circuit 211 and the second sequential logic circuit 212 is within an arbitrarily set time, and then activates the automatic frequency correction circuit based on this. or deactivation to solve problems such as unlocking due to the existing phase error relationship.

On the other hand, the result of applying the frequency synthesizer including the automatic frequency correction device to which the frequency phase determination unit of the present invention is applied to the example of FIG. 3 is as follows. Here, in FIG. 3 _{, the period between the reference frequency (f REF} ) and the frequency- _{divided frequency (f DIV} ) has a difference of 2.47 ns, and the number of period counters 16 is 39.52 ns, 32 is 79.04 ns, and 64 is 158.08 ns.

In the case of the automatic frequency correction device operation in FIG. 7 , _{the initial phase difference between the reference frequency (f REF} ) and the _{frequency-divided frequency (f DIV} ) is 9 ns, the number of cycle counters 16 is 30.52 ns (39.52-9), and 32 is 70.04ns (79.04-9) and 64 are 149.08ns (158.08-9), and it can be seen that the number of cycle counters 16 and 32 has a time difference within 127.5ns, but 64 is outside the time difference of 127.5ns. Therefore, it operates in the same way as when there is no initial phase difference.

On the other hand, in the case of not operating the automatic frequency correction device, the initial phase difference between the _{reference frequency (f REF} ) and the _{frequency-divided frequency (f DIV ) is 35 ns.} 43.04ns (79.04-35), 64 is 123.08ns (158.08-35), and the number of cycle counters 16, 32, and 64 all have a time difference within 127.5ns. That is, the same error as that of FIG. 5 described above occurs, and the present invention does not operate the automatic frequency correction device to prevent the above error.

Referring back to FIG. 6 , the automatic frequency correction circuit (AFC) may include a counter 310 , a comparator 320 , and a state machine 330 . The configuration of the automatic frequency correction circuit will be briefly described as the configuration described above.

When the control signal is received from another sequential logic circuit 240, the counter 310 counts the frequency and the reference frequency divided by the division ratio corresponding to the frequency at which the frequency for the intermediate power of the current output correction code is to be changed. The comparator 320 generates a change signal of the output correction code by determining whether the time difference between the period of the divided frequency and the period of the reference frequency satisfies a preset time difference. The state machine 330 transmits a digital signal corresponding to the change signal to the voltage-controlled oscillator 120 .

110: crystal oscillator 120: voltage controlled oscillator
130: divider 140: phase detector and charge pump
150: low-pass filter 211: first sequential logic circuit
212: second sequential logic circuit 221: first delay unit
222: second delay unit 230: logic circuit gate
240: another sequential logic circuit 310: counter
320: comparator 330: state machine

Claims (4)

a phase loop circuit that prevents an output frequency generated according to an input voltage from being changed by an external environment and changes the output frequency by comparing a frequency divided by a division ratio corresponding to a reference frequency and an output frequency to be set;
an automatic frequency correction circuit for counting the reference frequency and the frequency-divided frequency and designating one of the output correction codes in which a frequency synthesis range is specified; and
In order to prevent a designation error of the output correction code, when the initial phase difference between the reference frequency and the divided frequency satisfies a preset condition, it comprises a frequency phase determination unit for activating the automatic frequency correction circuit. Frequency synthesizer with robust automatic frequency compensator.
The method of claim 1, wherein the frequency phase determination unit
a first sequential logic circuit outputting a rising signal at a rising clock edge of the reference frequency;
a second sequential logic circuit outputting a rising signal at a rising clock edge of a frequency divided by a division ratio corresponding to the output frequency to be set;
a first delay unit configured to initialize the first sequential logic circuit after controlling the rising signal output from the first sequential logic circuit to be output for a preset time;
a second delay unit configured to initialize the second sequential logic circuit after controlling the rising signal output from the second sequential logic circuit to be output for a preset time;
a logic circuit gate for outputting another rising signal when a rising signal is simultaneously input from the first sequential logic circuit and the second sequential logic circuit; and
When another rising signal is output from the logic circuit gate, it includes an automatic frequency correction device robust to initial phase error, characterized in that it includes another sequential logic circuit that generates a control signal for operating the automatic frequency correction circuit. frequency synthesizer.
The method of claim 2, wherein the automatic frequency correction circuit
a counter for counting a frequency divided by a division ratio corresponding to the reference frequency and the output frequency to be set when the control signal is received from the another sequential logic circuit;
a comparator for generating a change signal of the output correction code by determining whether a time difference between the divided frequency period and the period of the reference frequency satisfies a preset time difference; and
and a state machine for transmitting a digital signal corresponding to the change signal to the voltage-controlled oscillator.

The method of claim 1, wherein the phase loop circuit
a crystal oscillator for generating the reference frequency;
a voltage-controlled oscillator for outputting the output frequency according to the input voltage;
a divider for dividing by a division ratio corresponding to the output frequency;
a phase detector and a charge pump for comparing the frequency divided by the divider with the reference frequency generated by the crystal oscillator and generating a pulse value corresponding to the difference between the divided frequency and the reference frequency; and
A frequency synthesizer comprising an automatic frequency correction device robust to an initial phase error, characterized in that it includes a low-pass filter that varies an input voltage input to the voltage-controlled oscillator according to the generated pulse value.

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