TH34343A - Storage device And how to access - Google Patents

Abstract

DC60 storage devices and access methods for hierarchical encryption actions by No cycle required For delaying more rows from memory For image collection The addressing circuit provides a 9-bit vertical address and a 9-bit vertical address. Exist, solve the memory of the first layer While providing eight higher rated bits of the number in Levels and vertical numbers that lack the lowest significant bits to the memory of the second layer, the result is at the time when each point in the first layer is written to the number. Addresses (2s, 2t), (2s + 1, 2t), (2s, t + 1), and (2s + 1, 2t + 1) in memory of the first layer, each address, same address. (s, t) in the memory of the second layer will be accessed based on the positive effect, at this point the adaptive read-write circuit is determined. The sum of the values stored at the address (2s, 2t), (2s + 1, 2t), (2s, t + 1), and (2s + 1, 2t + 1) in memory. Of the first layer came out And will write down the sum at the address (s, t) in the memory of the second layer. Storing devices and access methods for hierarchical coding actions without the need for cycles for delaying additional rows up from memory for image storage an addressing circuit is provided. The 9-bit address and the 9-bit vertical address are addressed to the first layer of memory. While providing the eight higher-ranking bits of the horizontal number and the lowest significant bit to the memory of the second layer, the result is at the timing at the point. In the first layer, each dot is written to the addresses (2s, 2t), (2s + 1,2t), (2s, 2t + 1) and (2s + 1,2t + 1). Each address number of the first layer, the same address (s, t) in the second layer's memory is accessed. By relying on good results at this point The modified read-write circuit defines the sum of the values stored at the address numbers (2s, 2t), (2s + 1,2t), 2s, 2t + 1) and (2s + 1,2t + 1) in memory. Remember the first class came out. And will write down the sum at the address (s, t) in the memory of the second layer.

Claims (1)

1. A storage device for storing illustrations with a first memory for storing image data sent at the address specified by at least the first address signal and the second address signal. A second memory is used to store data through one processor. Processed From the said image data together with the storage of such input image data at the address specified by part of the signal, the address number one. And the second aforementioned address signal At the very least, and A controller for controlling the writing and reading of data to and from one such memory. And a second such second memory for performing pre-defined processing on such data. 2. The storage device according to the claim clause 1, where the control is written on each address in that memory as the sum of the data written on the address number in the first memory inserted. Attached to each of the said address in the said second memory 3. The storage device according to the claim clause 1, where the aforementioned second memory stores long data Which is longer than the data length of the data The memory of the first one has been stored. 4. The storage device according to Clause 3, where the contract number at the first signal. And the second aforementioned address signal 5. The storage device according to claim 4, where the memory one has a capacity of memory, is respectively corresponding to the horizontal position and the vertical position of the image point for such input data. Remember the corresponding number of dots that compose. Creates a one-screen display of the said input image data. 6. The storage device according to claim 4, where the first memory unit has a memory capacity corresponding to the acquired number, by subtracting the number of numbers in the memory. The second is remembered by the number of image dots that make up one display of the said image data. 7. Storage device in accordance with claim 4, where the control unit writes the said input. On the first memory address number Which is specified by the contract number at the first signal And the second number signal Read the retention information stored at the second memory address. This is determined by part of the first and second address signals. Data is calculated through one such processing. By processing the results of such collection And the image data sent therein; And write the data through the aforementioned processing on a number of the aforementioned memory addresses in the second memory where the said storage data is stored. 8. Storage device in accordance with Clause 4, where the control unit reads the data. Stored at a number that is in memory of one such Which is specified by the first and second address signals that are issued While reading the data stored at the said second memory address Which is determined by part of the address signal. The first and second signals are issued; And select and export one of the two readings 9.Storage device for collecting images that include First memory for storing image data sent at the address specified by the first signal address number. And the second signal is at least Second memory for storing data through one processing. Which has been processed from such input image data at the address specified by the part of the signal, the number one signal And the second aforementioned address signal At the very least, a controller for controlling the writing and reading of data goes down and out of memory at one such. And such a second memory And for the predetermined processing of such data; And the delay for the formation of the address signal delay by delaying the address signal for the first and second signals. Where the controller reads the said imported image data stored at that number one memory address. Which is specified by the signal number at the first signal And the second one came out While reading data through the aforementioned processes stored at the aforementioned second memory address, identified by part of the aforementioned first and second address numbers, comes out. The data is computed through a second processing by processing such input image data. And the data through one such processing And will write information Through one such processing And will write the data through that second processing onto the number in the said second memory. Which stores the data through one such processing while at the same time The controller reads the said input stored at the number one address in the memory. This is defined by the address signal, such delay is output while reading through the aforementioned second processing. Stored at the address in the second memory Which is determined by the part of the signal, the address number, the delay said out It calculates the data through the original first processing by processing the imported image data. And data through such second processing The second processing is written to the address in the second memory, which stores the data through that second processing, where the second processing stores the data. Length of the data which is longer than the data length which one such memory has stored; And the number one signal at the address And the second signal address Will be correspondingly correspondingly with the horizontal position And the vertical position of the image point for the aforementioned image data 1 0. Access method in a storage device equipped with a first memory for storing the image data sent at the specified address. By the address signal specified by the signal address number one And the second signal is the least second signal; And a second memory for storing data through first processing. Which is processed from such imported image data together with the storage of such imported image data at the specified address. By part of the first address signal and the second address signal. At least By the method of access, it includes the steps of Writing the said image data onto the first memory address number. Which is specified by the signal number at the first signal And second as mentioned Reading the storage data stored at the second memory address. Which is specified by part of the signal, the address number one And second as mentioned Data is calculated through one such processing. By processing such collection information And the above-mentioned image data and the writing of the data via the aforementioned computation on the number of the aforementioned second memory that stores the said storage1 1. The access method in a storage device consisting of a first memory for storing image data sent at the address specified by the first signal address number. And the second signal at least A second memory for storing the data through the first processing, which is processed from the said input at the specified address part of the signal one, is the number one address. And the second aforementioned address signal To be the least; And the delay for the formation of the address signal delay by delaying the address signal for the first and second signals. The methods of such access include the steps of The reading of the said image data stored at the first memory address specified by the first and second address signal numbers are output. While reading the data through the first processing stored at the aforementioned secondary address numbers identified by part of the aforementioned first and second address signals. Data calculation through second processing By processing the aforementioned image data and data through the aforementioned processing; And writing the data through the aforementioned second processing onto the said second processing number, which holds the data through that first processor while at the same time. Will read the said imported image data stored at the address in the first memory Which is determined by the signal number, address the delay said out While reading the data through the aforementioned second delay, stored at the said second memory address. Which is determined by the part of the signal, the address number, the delay said out The data is computed through the traditional one processing by the processing of the said input and the data through the aforementioned second processing; It writes the data through that second processing onto the address in the aforementioned second processing that holds the data through that second processing.