TH3379A - A hidden memory for transmitting data that is shared between multiple processors. - Google Patents

Abstract

A unit of hidden memory has been created with a two-stage transmission system in which multiple sources can be shared.These are the central processing unit or the CPU (CPU) running independently of each other, etc. The devices installed within the hidden memory alternate the intervals between the two processors, where the performance of the two processors is spaced equal to one transmission step. This allows one submission process of the hidden memory to perform a table of contents search to a central processing unit, while another transmission step performs reading data from a data holder. Another central processing unit Each central processor is programmed for a less than allotted time interval. Consequently, the processor operates without conflicts, while the transmission process has a period of time to process requests from others. For example, reading data from main memory, replacing it, or chasing data from hidden memory into main memory.

Claims (3)

1. One data processing system, consisting of; - multiple sources of information. Each works by generating a request for information from memory. Each request for information is accompanied by a location signal. And a unit of hidden memory that contains a procedure for transmitting a certain amount of information and cycles with various sources of information. To receive requests for information from that memory This is where the hidden memory consists of: - timing and control factors, which are connected to the circuit to transmit such cadence to each such source. To set the timing of those sources to the said hidden memory Such timing and control factors generate a series of cadence signals. Each set of rhythm signals defines a number of intervals. Each source is allocated at a different time in advance for the first step of the Submit Procedure to be accepted. The process of transmitting information is the first phase of the hidden memory, which is cycles with different sources. And such timing and control factors to receive step control signals that timing and control factors generate when requested by different sources. As mentioned above, one of the sources in a pre-allocated period of time is the transmission phase. The first phase is triggered when it receives a signal that controls that phase by generating a data signal at the next time to retrieve. The requested information, as specified by the requested location, if the requested information is stored in hidden memory; and The second stage of the hidden memory transmits the second step of the recirculated memory to receive the step control signal from the timing and control factor. This second transmission phase is forced by the control signal of that phase to receive the said signal and retrieve the specified data over time. Continue for another period to broadcast to the requested source. This allows the processing of requests from multiple sources to be executed simultaneously without conflicts, where one source may use one of the submission steps while another. One source is using the second transmission step 2. The system according to claim 1, where such hidden memory also consists of: - Location selection factor which is cyclic to the first transmission phase of Hidden memory and its sources The said source to accept the location of the said request. And where such timing and control factors include: - Position selection logic factor connected to the aforementioned data processing sources and the said location selection factor. The logic factor for selecting such positions serves to generate a selection signal to make the position selection factor convey the requested location obtained from the source. One of the pre-allocated periods of time goes to the first transmission phase of such hidden memory, when the qualifying rational factor in that location receives a memory request signal. 3. The system according to claim 2, where such timing and control factors also consist of: - The main timing factor which generates the said cadence, series after series. Each set of strokes This includes the number of time intervals and the sending factors for generating the said step control signal, the factor for setting the start of the transmission per cycle, the main timing factor, and each such source. The initial transmission of the information includes: - Number one cycles factor, each per cycle with one different source. And connected to the aforementioned key timing factor and timing factor, connected to the number of cycles, and per cycle with each such transmission step. The cycle generating factor generates a predetermined set of step control signals. The different signal flow control signals will cause the transmission procedure to perform the tasks necessary to contain the processing of such requests simultaneously in each hidden memory cycle. Clause 3. In the case of such a system, it also consists of the system's cables and the first-in-out break subsystem, which is connected to the signal cables of that system. One number of central processing systems, each subsystem per circuit, with a factor for Make at least one of these cycles differently.Each such central processor subsystem makes a cycles that correspond to one factor, starting a read cycle to retrieve data from the hidden memory. Say at each such pre-assigned period And the first in, first out, rest subsystem causes different factors for creating cycles, initiating hidden memory cycles to process data to replace and to chase logs. Which is obtained from the said system's signal cable for a pre-allocated period, but is not used by the said central processor subsystem. 5. System according to claim No. 1, in the event that the data transmission procedure The first one consists of: - Memory factor, table of contents which are connected to the cycles and the timing and control factors. Memory Factor The table of contents has multiple locations for a table of contents that indicates where the hidden memory data is stored. And there was a signal generating factor found to indicate whether the requested data was collected in the second step, and the first order decoding factor connected to the memory factor, table of contents, timing and control factors. And data processing sources for each such source The first level command decoding factor is triggered when the request is received by generating a control signal forcing the memory factor to read the signal and generating such a signal at the interval following the period. Such pre-allocated This is to retrieve the information requested from the aforementioned second step. 6. System in accordance with claim 5, in case of multiple transmission steps, the second step consists of: - Hold memory factor, which is positioned for Stores multiple positions identified by corresponding table of contents. The storage factor to be transmitted, which is connected to the data hold, the timing and control factor. And each such data-processing source and the second-level instruction decoding factor connected to the data hold, timing and control factors. And decoding factor of the aforementioned order The second level of the decoding factor is forced from the step control signal generated over the next period, creating a control signal to allow the hold memory factor to accept that information signal. And retrieve the requested information to be stored in the storage factor to be sent. This is to be transmitted to any such source. 7. System according to claim 1, in the event that each source requests such amount of information, it consists of: - timing factors which are connected to the said timing and control factors. To receive a cadence signal, which sets the timing of the timing factor to the aforementioned hidden memory, and programmable control factors at a specified location, which are connected to the circuit with the setting factor. Loud rhythm Said and the timing and control factors thereof The micro-level programmed control factor stores and sends commands at the micro level during the duty cycle of the predefined field control factors.In this micro-level instruction, one field contains the code when the request was made. Any corresponding source of such data will be able to request information from the hidden memory during each such pre-allocated period. 8. System according to claim 7, in the event of a predefined field of command. At the micro level, pre-defined in the micro-level programmed control factor of each such source of information, only some commands with an identifying code request data from hidden memory and can only be requested in The cycles determined by the pre-allocated intervals for each such source only. 9. System according to Clause 8, in the event that the timing factor of each such source serves. Forces the micro-programmed control factor to send such micro-order at the pre-allocated time period that is separate from the pre-allocated period of another source of information. One by one A predetermined number of time intervals in order to be able to simultaneously process such requests for number 1 0. System in accordance with Clause 9 in the event that the aforementioned predetermined number is two and in In the event that the source requests such amount of information, the first source is allocated a period of time for each set in advance. The second source is pre-allocated a third period of each set 1 1. System according to claim 9, where the micro-order pre-defined on the control factor. Each source is a micro-switch command, which triggers a hidden request for information at intervals. The pre-allocation of such control factor cycles is reversed to service requests for data from hidden memory from another request source without conflict during a non-pre-allocated period. Use 1 2. System according to claim 11, in the event that the first and second source is the processor. And another such source is the first-in, first-out, dormitory subsystem, which processes the requested data and the data to be replaced.1 3. The system according to claim 5, in the event that the table of contents includes: - Units A pair of positions to store a number of paired position signals. A pair of position signaling devices which are circuit connected to the memory. Timing and control factors And the selection factor for such position signal For receiving dual position signals Memory of the odd number of positions for storing first number of position signals. Odd position signal detectors which are connected to the circuit with the memory. Timing and control factors And the selection factor for such position signal For position signals and such odd and even position signals, they are governed by a timing factor and controlled at each pre-allocated time period for use by one such source. Such odd and even position signals shall be stored for reading such position information from the memory, table of contents, even and odd, to retrieve the requested information. 1 4. System according to claim 6 in case of memory factor The hold contains: - The odd fold memory, which contains a number of repositories associated with a number of different odd position signals. An odd position hold signal collector which is connected to the odd hold memory circuit. The timing and control factor and the aforementioned transmitting step one for receiving odd position signals. Dual hold memory contains a number of positions associated with a number of different pair position signals. Dual position signal collector, which is circuit connected to the dual sleep memory. The timing and control factor and the transmission step are one step. For receiving dual position signals and the storage factor to be transmitted, it consists of a receiver, one device and a second device. Which is connected to the first and second source of data processing In this case, such odd and even break signals are subject to timing and control over the next period, to store odd and even position signals for retrieving information requested from memory for Rest oddly and such pairs And the first and second devices The selected equipment will be forced and controlled over a period of time thereafter the requested data is collected to be transmitted to the corresponding source of information. 5. One data processing system, which consists of: - Subsystem for Processes a certain amount of data, each of which can generate a request for information from memory. Each request for information has a location. The hidden memory subsystem has a first and second transmission phase and cycles with each such data-processing subsystem to receive a request for that information. These hidden memory subsystems include: - timing and control factors, which circuit each such data-processing subsystem to generate a series of cadence signals. The timing and control factors are connected to the circuit to transmit the timing to each such data-processing subsystem. This is to set the timing of all such data-processing subsystems to the said hidden memory subsystem. Each stroke signal A series consists of the intervals with a corresponding number. A predetermined amount of such period has been allocated. To each such subsystem An input selection factor, which is circuitry with such a data-processing subsystem, for selecting one of the requested positions from one of the subsystems, the system for a certain period of time, pre-allocated for that subsystem. The process of transmitting the first phase of the said hidden memory to the circuit with the timing and control factor and the said input selection factor. The first such transmission phase is forced by the said timing and control factor to generate a beacon to indicate where the requested data is stored during the pre-allocated time for that subsystem. Corresponding systems are used when each such request is received from the said signal selection factor and the second transmission phase of the said hidden memory to the circuit with such timing and control factors. The number of subsystems And the first step of the transmission of the said hidden memory for receiving the beacon The second step of this hidden memory is forced to store the beacon and retrieve the specified data for the next one. This is to convey such information to the aforementioned number subsystems. Makes processing requests from a subsystem for processing a number of It can go hand in hand without conflict, where one subsystem may use one of the submission steps, while another data processing subsystem is using the submission step. Two 1 6. The system according to claim 15, where the pulsation and control factor also includes: - The main timing factor which generates the said clock cycle over and over for each such clock cycle. This includes the number of time intervals and the sending factor for generating the signal, the transmission process, the factor for setting the initiation per cycle, the aforementioned key timing factor and each aforementioned subsystem. Factors for setting the initiation of such information include: - A number of cycle factors, each per cycle with one different subsystem, and one per cycle, to the main timing factor, and the timing factor, which Connect the circuit to the inputs for the number of cycles and the circuits with each step of the transmission. However, the factor for creating such cycles will generate signal to start transmitting during the pre-allocated period. When requesting information from hidden memory specifies the usage types used by the various data processing subsystems. The transmission signal is required and the timing factor generates a predetermined set of transmission phase signals. When the timing factor receives a signal, it starts transmission each time. Each signal is responsible for each step of the transmission of such information. Required to achieve sequential processing of data requests from hidden memory in each hidden memory cycle defined around one such clock cycle. Article 16 Where such a system also consists of the system cables and the first-in-the-way hold subsystems that are connected to the cables of that system, the data processing subsystems include: A number of central processor subsystems Each subsystem is connected to a circuit with The factor for creating such cycles is at least one different factor. Each such central processor subsystem makes a factor for generating cycles corresponding to one factor, starting the processor's read cycle. To retrieve data from that hidden memory at each of those pre-allocated periods And such first in and out of the rest subsystem forces a factor for creating different cycles to initiate a hidden memory cycle to process the data to be replaced and to scavenge the record which receives the signal of that system. During the pre-allocated period but not used 1 8. System according to claim 15, in the event of the aforementioned submission procedure, the first step consists of: - the memory factor, the table of contents which is connected to the timing factor; Control it Memory Factor The table of contents has multiple locations for a table of contents that indicates where the hidden memory data is stored. And there is a signal generating factor found to indicate whether the requested data is collected in the second step, and the first order decoding factor, which is circuitry with the table of contents factor. Timing and control factors And the subsystem for processing each such data The first level command decoding factor is triggered when the request is received by generating a control signal forcing the memory factor to read the signal and generating such a signal at the interval following the period. Such pre-allocated This is to retrieve the information requested from the aforementioned second step. 1. 9. System according to claim 18, in the event that the second transmission stage consists of: - a data hold factor with a storage location. Multi-position information identified by the corresponding table of contents. The storage factor to be transmitted, which is connected to the data hold, the timing and control factor. And each such data-processing subsystem and the second-level order decoding factor connected to the data hold, timing and control factors. And decoding factor of the aforementioned order The second level of decoding factor generates a control signal for causing the hold memory factor to accept such a signal and relays the requested data to be stored in the storage factor to be sent. In the next such period, in order to transmit to any such source 2 0. System according to claim 15, in the event that each such data processing subsystem consists of: - The timing factor, which is circuit-connected to receive the clock signal from the timing and control factor, sets the timing of the timing factor to the said hidden memory and the derived control factor. Micro-programmable and positionable programming, which is connected to the said timing factor and the timing and control factor. The micro-programmed control factor stores and sends commands at the micro level during the control factor duty cycle. A predefined field in this micro-level command contains a code indicating when the subsystem is for processing that amount of data, which corresponding system can request data from the hidden memory at the time. Each of these pre-allocated sessions: 1. System according to claim 20, where a predefined field of micro-level instructions is pre-defined in the control factor programmed at the micro level of the subsystem. For processing this amount of data, each system, only some commands with a specific code, request data from the hidden memory, and are only requested in cycles defined by the pre-allocated intervals for the number data processing subsystem. 2 2. System in accordance with claim 21 Where the timing factor of each such data-processing subsystem is responsible for the regulated control factor to be controlled. The micro-level program sends such micro-instructions at a pre-allocated time interval, separated from the other data-processing subsystem's pre-allocated intervals by a predetermined amount of time. In advance of a certain amount In order to be able to process requests from the aforementioned number of data processing subsystems simultaneously within the aforementioned submission process 2 3. The system according to claim 22, in the event of such a predetermined number For example, two, and in the event that the subsystem for processing that amount of data, the first system is allocated a period of time in each round in advance. The second system is allocated a third period of each round in advance. 2. 4. System according to claim 22, where the pre-defined micro-order in The micro-programmed control factor of the subsystem for processing that amount of data, the first and second systems, are micro-switches, which generate a memory request. Concealed during the pre-allocated period of the said control factor alternately to serve the hidden memory data request from the other request source without conflict during the allocated time period. Unused advance 2. 5. Systems according to claim 24, in the event that the subsystems for processing such amount of data at the first and second systems is the central processor. And another such source is the first-in-one hold subsystem, which processes the requested data and the information it replaces 2 6. The system according to claim 18, where the table of contents includes: - Dual Contents Memory, which contains a number of positions to store a number of pair position signals. A pair of position signaling devices which are circuit connected to the memory. Timing and control factors And the selection factor for such position signal For receiving dual position signals Contents memory, where there are a number of positions to store a certain number of odd position signals. Odd position signal detectors which are connected to the circuit with the memory. Timing and control factors And the selection factor for such position signal For receiving the odd position signal and the aforementioned odd and even position signaling devices, it is forced and controlled during each pre-allocated time frame.For use by one of the subsystems, the even position signal is stored. And odd for reading the said position data from the memory of the table of contents, even and odd to retrieve the requested information. 2 7. The system according to Clause 19 in case of such resting memory factor: : - Hold memory in which a certain number of positions are associated with a number of different odd position signals. A collector for odd position hold, circuit connected to memory for odd breaks, timing and control factors. And the process of sending information on the aforementioned steps For receiving odd position signals Dual hold memory contains a number of positions associated with a number of different pair position signals. Dual position hold signal collector, which is circuit connected to memory for dual timing, timing and control factors. And the aforementioned first transmitting step for receiving dual position signals and the storage factor to be transmitted consists of the first and second signal acquisition devices. It is connected to the first and second system data processing subsystem. The odd and even break signal collector is then subjected to timing and control over the next period, to store odd and even position signals for retrieving the requested information from the break memory. Such odd and even And the first and second devices The selected device is then governed by a timing factor and controlled at a later time. The requested data is then collected to be transmitted to the corresponding data-processing subsystem. One is for the use of hidden memory, which has a shared two-step transmission process between a number of data processors that are per cycles and need to be serviced. The method consists of the following steps: - (a) Creating a series of rhythmic sets. By the timing and control devices, which are in the said hidden memory and connected to the source of the data processing Different sets of rhythmic signals (B) Allocation of one or more of these intervals in advance for each such source to match the hidden memory. Service requests from each of the aforementioned sources. And the hidden memory, which has two transmission stages, also consists of a first and second transmission phase, which is connected to the source of the data processor (c). The first phase of data generates a signal for the next one when it receives a request for information from that number of sources, corresponding sources during each pre-allocated period. Such a signal indicates where the request is stored in the hidden memory and (d) the execution of the second phase of the transmissions thereafter to receive the signal from. Submission procedure Step one to retrieve the requested information to transmit to the said source corresponding source. This enables the processing of requests from such data processors, which share the hidden memory by the said first and second transmission steps, to be performed simultaneously without conflict. However, one data processor may use a second submission process while another is using a second submission process 2. 9. Claim Method. Article 28 Where such pre-allocation procedures include: - Specifying such pre-allocated intervals separated from each other by the pre-assigned number of intervals selected to facilitate the processing of requests from The number of sources can be run simultaneously 3. 0. Clause 29 method, if the method also consists of a programming procedure for each such source, use the time period. The maximum pre-allocated only occurs in an alternate set. This leaves a pre-allocated period left to serve at least one other source without conflict. 1. a data processing unit, which contains: - a number of sources which are connected to a circuit with a hidden memory; Each request source works by generating a memory request to access that shared hidden memory. Each request contains a signal position signal. Such hidden memory has a number of transmission processes that cycles with that number of sources. And the first and second steps of the data transmission phase, the numbers contain the table of contents and hold factors, respectively. The hidden memory includes: - Timing and control factors for generating different sets of cadence signals. Such timing and control factors are per circuit to send the pulsation to each such source to determine the timing of those sources to match the hidden memory. Consists of a number of moments A predefined period of time is allocated to receiving requests from each such source in advance. The second step per cycle with the said timing and control factor, and the sources, the second transmission phase, per the cycle, and the first such transmission phase. Such timing and control factors And various sources Some such sources When the said timing and control factor receives the position signal of each request during the aforementioned time interval. The timing and control factor generates a series of control signals to make the first and second transmitting steps run at subsequent intervals within each set of timing signals. Generate a data signal by invoking the table of contents of the transmission process. The first step, based on the location signal of the request, is to retrieve the hold factor of the second transmission phase based on the signal. Reading or recording of hidden memory is performed as requested by one source, one source may use the first submission process, while another source is using the submission process. Two live 3 2. The data processor according to claim 31, in the event that the source requests the amount, it consists of at least one central processing unit and one first-in-exit occupancy unit 3. 3. The data processor pursuant to claim 31 in the event that each of the aforementioned pre-allocated periods are separated by a certain number of periods and that number is equal to the total number of periods in the set. Strokes divided by the number of steps transmitted.