TH18352A - One type of circuit for creating multiple display screens. - Google Patents

Abstract

A multi-display circuit has been revealed that can independently display multiple displays on a large main screen, corresponding to a number of sub-display configurations of 4, 9, 13, and 16 sub-displays, depending on the size of the main screen. This circuit can also provide independent selection of any of these multi-display configurations, regardless of the number of broadcast channels, which may vary from region to region. The invention, which accomplishes the intended purpose, comprises: a decoding unit No. 10; an address generator No. 20; a write reference (WRS) circuit No. 30; a write display controller No. 140; a continuous numeric clock generator No. 188; a primary modulator No. 70; a read timing circuit No. 80; and a 1-byte memory device for data storage. One temporary number, 90, and one data mixing device, number 100.

Claims (7)

1. A multi-display circuit is used to create one or more sub-displays, each sub-display being a uniformly compressed version of an image corresponding to one of a number of user-selectable media channels. The circuit consists of an input section arranged to receive video signals representing a number of video media channels; a sequential converter to convert video signals representing a number of video media channels; another sequential converter to convert video signals to numerical values; a processing section arranged to create video data representing a number of video segments from the video signal, each image corresponding to a different video media channel in relation to the display-n operating method selection data (where n is 1 or greater); and an output section arranged to create a composite video signal containing this video data so that multiple sub-displays can be displayed simultaneously on a main monitor, each sub-display residing in a separate section. Selection data is used to choose the desired operating method from at least one of the selectable display-n operating methods. One operating method can display two different sizes of sub-displays simultaneously on the main monitor. 2. A multi-display circuit under Claim 1 where the sampling rate of the continuous-to-digital converter is variable in accordance with the operating method of the selected display. 3. The multi-display circuit under claim 1 or 2 shall include a dual-output data memory, a simultaneous signal generator, and a microcomputer. This circuit shall consist of an instruction decoder, which receives the vertical simultaneous signal from the simultaneous signal generator and the display-n operation selection data, along with the control signal from the microcomputer, and after decoding, generates the display operation data signal. An address generator consisting of vertical/horizontal write and read address generation circuits shall generate write address signals to be used with the dual-output data memory for read and write operations corresponding to the display-n operation selection data. A write reference (WRS) circuit shall generate a signal modified from the vertical and horizontal simultaneous signals generated by the simultaneous signal generator and a write reference signal corresponding to the write after receiving the display operation data from the instruction decoder. A write display controller shall receive the vertically sampled signal from the write reference circuit and the display operation data. The output from the decoded instruction is then used to identify the address generator for writing vertical/horizontal data. This address generator will be written with the display operating information and controls the creation of the address for writing data. A continuous time signal generator converts the signal to a numeric value, receiving the simultaneous horizontal signal generated from the video signal of the simultaneous signal generator together with the reference frequency signal from the base clock terminal and the display operating information from the decoded instruction. The reference frequency signal is then separated sequentially, corresponding to the display operating information selection data-n, and a clock signal is generated for the continuous numeric converter. The first mixing device mixes the address signal generated by the address generator, corresponding to the control, and then uses this signal as address information for the dual-output memory. A serial-to-parallel converter produces the numerically converted video signal by controlling the dual-output memory and serial brightness and color information after converting the parallel brightness information to the first and second brightness and color terminals under the control of the converter. The serial-to-parallel conversion uses a write timing generator that takes the sampling clock signal for the numerical video signal corresponding to the selected display operating method from the continuous clock generator, converting it to the aforementioned numerical value, and the write authorization signal for the dual-output data memory and the write initiation signal from the write reference generator. It then generates control signals for the first and second brightness selection and color signals for the serial-to-parallel converter, along with the address switch signal and the data transmission signal of the first mixing device. It also generates a DT data transmission signal, which carries transmission control to the R/CAS (horizontal/vertical address) and WE (write authorization) devices of the dual-output data memory and the serial output register. The read timing circuit receives the simultaneous horizontal signal from the simultaneous signal generator and the signal from the terminal device of the reference frequency timing signal, generating a logic circuit signal separate from the original and clock signals of the numerical converter, converting it to a continuous value, and then regenerating it. A serial clock signal and timing control signal correspond to the read-only memory device. A 1-byte memory device temporarily stores data representing multiple display outputs from addresses specified by generating data from the horizontal/vertical read-only addressing circuit to an address generator corresponding to the vertical signal of the serial clock from the read-only timing circuit. This is then used to temporarily store data corresponding to the first and second brightness and color signals dependent on the clock signal and a data mixing device which mixes the data from the 1-byte memory device in accordance with the clock control signal of the read-only timing circuit and then outputs the result to a sequential converter to convert it into a numerical value. 4. Processing equipment and/or video processing equipment that provides multiple display circuits as specified in one of the preceding claims. 5. The device under claim 4 shall consist of a color monitor. 6. The device under claim 4 or 5 shall include a video recorder. 7. The device under claim 6 where the recorder is a tape recorder (Clause 7, 3 pages, 8 figures).