TH18344B - Phase adjustment of video/raster signals for horizontal deviation systems? - Google Patents

Abstract

Adjusting and maintaining the phase relationship between the video signal and the sweep synchronization signal. To ensure the accuracy of the horizontal centering correctly Has been provided in a horizontal deflection system The first loop-locked phase produces a first time signal at the first frequency. Asynchronous with the horizontal synchronization component in the video signal, the preset counter works in sync with the first time signal. For dividing the signal Clock to produce a second time signal at a second frequency The second phase locked loop produces a sweep synchronization signal from the second time signal. Microprocessors may send different numbers to registers. The register output will be connected to a predefined counter. The differential number changes the relative phase between the first and second timing signals, through a microprocessor-modifying step measures the selection of a video signal source that switches to one of the gates of the microprocessor. Switchable video source to video signal and output. Synchronized signal and correlate phase between the synchronization components. According to the selected video signal source horizontal line, hand operated circuit May be connected in the reverse path of the second phase-locked loop. For adjusting the relative phase between the second timing signal and the sweep synchronization signal. Throughout the range corresponding to the adjusted step.

Claims (33)

1. The horizontal deviation system for adjusting and maintaining the phase relationship between the video signal and the sweep synchronization signal consists of: a path for producing a first-time signal at the first frequency corresponding to the horizontal synchronization component in the video signal, and synchronizing it with that horizontal synchronization component; a counting path operating in synchronization with the first-time signal to produce a second-time signal at a second frequency higher than the first frequency; a path for sending different numbers to the counting path to adjust the phase relationship between the first and second-time signals to control the horizontal image centering in different operating modes; and a path that responds to the second-time signal to produce the sweep synchronization signal at that second frequency. 2. The system of claim 1 in which such counting pathway consists of a pathway for dividing the clock signal to produce such second time signal. 3. The system of claims in clause 1 in which such different numbers are sent via such counting pathways from a distant source. 4. The system of claim 1 also includes microprocessors for sending different numbers of such data, and a data bus for communicating between such microprocessors and such counting pathways. 5. The system of claims in Article 1 where such a pathway for producing the first time signal consists of a pathway for producing a clock signal at a multiple of the first frequency and a second pathway for dividing the clock signal by that multiple to produce the first time signal. 6. The system of claims in paragraph 5 where the path for producing such clock signal and such second counting path from a part of a phase-locked loop, with such synchronization component of such video signal as input and such first time signal as output. 7. The system of claim 1 also includes a path for detecting the edges of pulses in the first time signal and producing a control signal for such counting path in order to synchronize such counting path with the first time signal. 8. A system of claims 1 in which the transmission path consists of a sliding register whose output is connected to the counting path and whose input is connected to the source of different numbers. 9. The system of claims in paragraph 1, whereby such a pathway for producing such sweeping synchronization signals consists of a phase-locked loop. 10. The system of claim 1 also includes a means for synchronized phase between the aforementioned second time signal and the aforementioned sweep synchronization signal. 11. The horizontal deviation system for controlling the phase relationship between the video signal and the sweep synchronization signal consists of: a path for generating a clock signal at a clock frequency relative to the horizontal synchronization component of the video signal; a first count path for dividing this clock signal by a first factor to produce a first time signal at a first frequency; a second count path, synchronized with the first count path, for dividing this clock signal by a second factor to produce a second time signal at a second frequency different from the first frequency; a path for differential portions to the second count path for phase adjustment between the first and second time signals to control horizontal image centering; and a path for synchronized generating the sweep synchronization signal from the second time signal. 12. The system of claims in clause 11 in which such second counting path is connected to the distant origin of such initial number. 13. The system of claim 12 also includes a data bus for connecting the aforementioned second counting path to the microprocessor. The microprocessor then transmits the aforementioned initial number. 14. The system of claims in clause 11 also includes a means for synchronized phase between the aforementioned second time signal and the aforementioned sweep synchronization signal. 15. The system of claims in paragraph 14 in which such a procedure for the phase correlation between the aforementioned second time signal and the aforementioned sweep synchronization signal can be operated manually. 16. A horizontal deviation system for a television handling at least two differential video signal processing consists of: a first production path to produce an fH time signal, which is synchronized with the fH horizontal synchronization component of the video signal; a counting path, synchronized with the first production path, to produce a 2fH time signal; a differential number source required to control the horizontal picture center alignment for handling at least two differential video signal processing; a first phase control path is connected to send one of these differential numbers to the counting path for phase adjustment between the fH and 2fH time signals to control the horizontal picture center alignment; a second production path, synchronized with the 2fH time signal, to produce a 2fH sweep synchronization signal; and a second phase control path is connected to the second production path for phase adjustment between the 2fH time signal and the 2fH sweep synchronization signal. 17. The system of claim 16 in which the first phase control pathway is connected to the data bus for receiving different numbers. 18. The system of claim 16 in which the aforementioned second-phase control pathway is connected to the manually operable pathway. 19. The system of claims in Article 16 where the first and second production routes consist of the first and second phase-locked loops, respectively. 20. The system of claims in paragraph 16, where such counting path divides the synchronized clock signal with such fH time signal to produce such 2fH time signal, such different numbers are used to predetermine such counting path. 21. The system of claim 20 in which the first phase control path is said to consist of a sliding register whose output is connected to the said counting path for sending such different numbers and whose input is connected to the remote source of such different numbers. 22. The system of claim 21 also includes a data bus for connecting such counting paths to the microprocessor; the microprocessor sends such different numbers to the such shift registers. 23. A horizontal deviation system with phase control circuitry for determining the phase relationship between the uncrossed 2fH sweep synchronization signal and the crossed 1fH video signal horizontal synchronization component consists of a first clock path to produce an nfH time signal, where fH is the horizontal sweep frequency and n is an integer; a circuit divided by n to produce a 1fH time signal from the said nfH time signal; a first phase-locked loop incorporating the said first clock path to synchronize the said 1fH time signal with the said video signal synchronization component; and a predefined n/2 divided counter circuit. A synchronized process is performed with the aforementioned 1fH time signal to produce a 2fH time signal from the aforementioned nfH time signal. A path is used to send different numbers to the aforementioned n/2 counter circuit to adjust the delay between the aforementioned 1fH time signal and the aforementioned 2fH time signal, and a path is operated in synchronization with the second time signal to produce a 2fH scan synchronization signal. 24. The system of claim 23 includes a data bus for transmitting the said number to the said counter circuit. 25. The system of claims in clause 23 includes registers for storing such amounts. 26. The system of claims in clause 23 consists of a path for decoding the predefined output counter of such counter circuit into the aforementioned 2fH time signal. 27. The system of claim 23 includes a manually operable part for adjusting the delay between the aforementioned 2fH time signal and the aforementioned 2fH sweep synchronization signal. 28. The system of claim 23 consists of a phase-locked loop operating in synchronization with the aforementioned second time signal, and a controllable oscillator for producing the aforementioned 2fH sweep synchronization signal, and a manually operable path for adjusting the delay between the aforementioned 2fH time signal and the aforementioned 2fH sweep synchronization signal, which is connected in the feedback path of the phase-locked loop. 29. The horizontal centering circuit for video signals from switched video sources consists of a first and a second video source and each a horizontal synchronization component. A path is connected to these video sources to select the video signal and its individual horizontal synchronization components from one of the first and second video sources as the output. A predefined division path, synchronized with the selected video signal's horizontal synchronization component, produces a time-sensor signal with a phase delay adjusted relative to the synchronization component depending on the predefined division path. A control path is used to activate the video signal selection path and to set the predefined division path by an appropriate number for the selected video signal. 30. The cycle of claim 29 where the aforementioned time signal is a synchronized, sweeping signal. 31. The circuit of claim 29 consists of a path for synchronized sweep synchronization signals from the aforementioned time signals. 32. The circuit of claim 29 in which such control pathway comprises the microprocessor, the video source selector switch, and the communication and control bus for communication between such microprocessor, the video source selector switch, such alternative pathway, and such section for producing the such synchronized timing signal. 33. The circuit of claim 32, where the path for producing the synchronized timing signal consists of a counting path for dividing the clock signal to produce the timing signal, such a counting path has preloadable inputs for different numbers from the microprocessor to adjust the phase delay accordingly.