TH17690A - Data drive circuit for LCD display. - Google Patents

Abstract

Data drives and systems that can be processed into Directly in the base material of the liquid crystal LCD display to eliminate the cost of processing circuit. Ambient and mixed assembly required in a matrix-sensitive liquid crystal display. Without swiping to attach them in a row A de-multiplex circuit is on the display to D multiplexing, a group of Y, a column of input signal, the image data is multiplexed to X groups of Y pixel capacitors that are on the substrate material in Z rows as well. Advance is on the substrate material to pre-charge the pixel capacitors to The first voltage level causes the image data signal to be connected there in a de-multiplexed manner. Causing the pixel to discharge to the second preset voltage level To give an impression Images while rows of pixels are sequentially swept.

Claims (8)

1. The type (104) display with the first (14) and second substrate material opposite, is separated by a layer of electrophoresis. A display is included. Y image input wires (13) located on the first support material, group X, group (72, 74, 76) of the Y switching element (86 ... 92,94 ... 100) in row Z. Row on first substrate material (14), common electrode (28) for all switching elements on the second substrate. The drive line is attached to the Z row of the switching element. For stimulating Switching elements in each group X group (66,68,70) of the Y-multiplexed element (108 ... 114) located on the first substrate material (14) and connected to the X group. Of the Y switch element and the Y image input line, the line is characterized by: at least the first substrate material (14) is a thin-film transistor glass made up of each decouple element. The (86 ... 92) for the coupling of image data on the Y-line input line sequentially and sequentially directly to each group of X groups of Y switching elements to create a video image. The switching transistor (86 ... 92) and each pixel capacitor element (94 ... 100) that make up each of the Y switching elements, the first control wire (104) for each group of the decoupling. The X-group duplex is on the first substrate material and is attached to each pair decouple component (108 ... 114), respectively, to The coupling input wires are connected to the paired switch transistors in one selected row of the Z row in each group of the X group switching elements (86 ... 92,94 ... 100), while each The row is stimulated Respectively, and a second control line (106) for each group of X group decomplexes that are on the first substrate material and are attached to each odd decomposition element. Respectively for the coupling The odd wire leads to the odd switching transistors in one selected row of Z rows in each group of X-group switching elements, while each row is energized sequentially to form a display image. Display (14) on claim 1, where each pixel capacitor element (94 ... 100) has the first electrode on the first substrate (14) and the common electrode ( 28) is on the second substrate. Each first electrode is connected Amalgamated to each corresponding Y-Switching Transistor (86 ... 92) in each of the X Groups (72 ... 76) of the Y Switching Element, and is also assembled. Each Y front charge element (120 ... 126) on the first substrate material is attached to each of the Y image input wires (13) between the decomplex elements. (108 ... 114) and corresponding switching transistors (86 ... 92) to pre-charge the data lines and The pixel element before the image data signal is attached to the image input cable 3. The display (14) according to claim 1 also includes Thin film transistors made up of each individual Y pre-charged element (102 ... 126) and the thin film transistor formed as each of the Y switching transistors (86 ... 92) in Each group of switching elements X group 4. Display (14) according to claim 3 where X = 6 groups Y = 64 and Z = 240 5. Display (14) according to claim 1, where picture The video is a television picture 6. Display (14) according to claim 1, where each of the Y switching elements (86 ... 92,94 ... 100) consists of a capacitor. Pixels (94 ... 100) and switching transistors (86 ... 92) created as display elements. And also included Line drive circuit (25) connected to the drive line for selecting the assigned row. Sequentially and activate the switching elements in each of the selected 1-Z rows and Y pre-charged elements (120 ... 126) located on the first substrate material (14) and connected to each A corresponding Y-switching element for pre-charging, data line. Each line and pixel capacitor in a selected 1-Z row causes condition information on the Y line (13) input image data line, and the selected pixel capacitor reaches the input image data voltage level. To create a video display, while each row is selected. 7. Display (14) according to claim 6, which is also included. Thin film transistors (120 ... 126) with source drain and gate electrodes are built as Individual pre-charged elements And its source electrode is attached to a wire of Input to the relevant Y-line (13), its voltage source The drain electrode of each pre-charged transistor and the pre-charged signal wire (118) is connected to the gate electrode of the thin film transistor. Pre-recharge each To make the transistor conduct electricity and pre-charge All data lines And the corresponding pixel capacitors (94 ... 100) in the selected row in the X selected group of elements Switch assembly (86 ... 92,94 ... 100) before the data on the image data line Y line (13) is connected to the switching component. Making it open the way of data lines to discharge each pixel capacitance to a level Input image data voltage To create a display image 8. Display I (14) according to claim 7, which is also included. First preset pressure The drain electrode of the pre-charged transistor (110 ... 114) is connected to the odd data line D1, D3 - Dn-1, and different preset voltages. two Connected to the drain electrode of Pre-charged transistors (108 ... 112) connected together Data lines into pairs D2, D4 - Dn 9. Display (14) according to one of the previous claims. That also includes Control path (102) To open the D multiplex circuit (66 ... 70), connect the Y-image input wires sequentially to the X group of Y switching elements (86 .. .92,94 ... 100) is a fixed period t, where the image stream is sequentially coupled to each of the X groups for the first period. Causes a second additional constant period to be allowed for the last X group of the switching element. To get into place at the input image data pressure level 1 0. Display (14) according to claim 9 that also contains The drive-row path (25) connected to the Z rows of the X groups of switching elements (72 ... 76) for generating the selected signals, each row of the Z-row switching elements, respectively, and the pre-charged circuit (116 ) Connected to Z rows of Y columns for charging Advance each switch element in each selected row. For the third period Before the line multiplexing, input image data (13) to X group of switching elements 1. 1. Display (14) according to Claim 10 that also contains A path for allocating the fourth period before the third period. For pre-recharging To deselect the switching element. (86 ... 92,94 ... 100) in rows n-1 by taking the signal Select a row to isolate the switching element. Causing it to retain its image data charge 1 2. Display (14) according to claim 11, where t = 42 microseconds X = 6 and Y = 64 1. 3.Display (14) according to any claim 9 to 12, where the control path (102) is opened via the de-multiplexing circuit (66 ... 70) to de-multiplex. Signal cable Input the Y line image data (13) to each group in the X group of Y columns for the third constant period to charge and discharge all of the internal data lines and selected pixels up to the input image data voltage level. Stabilize a second period of time for the opening of the pixel capacitors (94 ... 100) selected in the last X group to allow enough time to reach the input image voltage level. All pixel capacitors (94 ... 100) in n-1 rows were isolated during the fourth constant period and the second (16) circuits were provided for pre-charging, the internal data lines and capacitors. All pixels in n rows reach the first voltage level during the fifth constant period. Each n successive row of pixels is sequentially charged to the first voltage level. And then switched to the pressure level Input image data with a decoding signal that is well multiplexed for the specified time interval. And by pixels In each of the adjacent rows, n-1 is isolated to create a render 1. 4. Display (14) according to claim 1, where the switching element is included. Switching transistor (86..92,94 ... 100) and a pixel capacitor. The display also includes the first circuit (116) for pre-charging, the data line and all the pixel capacitors in the n swept rows to the first preset voltage level, the first for the first constant period, and the second circuit. (102) For decoding, the input signal is applied to X groups of capacitors. The pixels in the row n are swept at the next two constant intervals. Make the preset pressure level The first value in each pixel capacitor in each X group in the swept row is transformed to a level. Input image data voltage To create a renderer while Z rows are swiped sequentially by 1. 5. The display (14) on claim 14 also contains a third (25) circuit path for sweeping Z rows sequentially during the third fixed period. And isolated all pixel capacitors (94 ... 100) in row n-1 before pre-charging all pixel capacitors (94 ... 100) in n rows during the first constant period 1. 6. Display (14) according to claim 15, where at the second circuit, multiplexing (102), the input video signal to all groups of X group of pixel capacitors in a given row to n at time t. The second moment to make each pixel capacitor voltage Switch to the input image data voltage level, second value, first circuit (116), pre-charged all data lines and pixel capacitors (94 ... 100) each in the selected row n in the interval constant. first To make each pixel capacitor be extruded Pre-charge to the first preset voltage level and the third circuit (23), unselect the n-1 row by isolating all the pixel capacitors in the n-1 row during the third period 1. 7. Display (14) according to claim 16, where the second circuit (102) d multiplex the input signal. Image data to each X group of pixel capacitors (94 ... 100) in t / X intervals and allow an additional interval thereafter. This gives each of the pixel capacitors in the X group enough time to reach their level. Its input image data voltage before row n is deselected as row n-1 1. 8. Display (14) on one of the previous claims. Where the display (14) is an LCD