TH12717B - Intermittent reception control device - Google Patents

Abstract

The waiting period for the reception is roughly counted by the clock count. Low frequency using a low frequency counter And the like of the intermittent reception period, which cannot be counted by the low-frequency clock time resolution, is counted by a high-frequency clock using a high-frequency clock counter. high The output of the high-frequency clock is stopped while the receiving period is counted by the low-frequency clock counter as the result is the correct start time of the intermittent reception. It can be set with reduced power consumption caused by stopping the high frequency clock output.

Claims (15)

1. The interval reception control device provides a receiving unit for periodically receiving transmitted data from the master station at predetermined times and for setting the reception time. This device consists of: a high-frequency oscillation circuit for oscillating and transmitting a high-frequency clock signal with a period shorter than the transmission cycle period for one bit of data from the master station; a low-frequency oscillation circuit for oscillating and transmitting a low-frequency clock signal with a period longer than the transmission cycle period for one bit of data from the master station; an edge detector for detecting the edge of the low-frequency clock signal exiting the low-frequency oscillation circuit; a first high-frequency clock counting section for counting the number of high-frequency clock signals exiting the high-frequency oscillation circuit after the receiving unit begins waiting for transmitted data from the master station until the start edge is detected by the edge detector; a low-frequency clock counting section for counting the number of low-frequency clock signals after the start edge is detected by the edge detector and for generating a time signal when the count of low-frequency clock signals counted by the low-frequency clock counting section reaches a predetermined number; and a second high-frequency clock counting section for counting the number of signals... The high-frequency clock operates after the time signal is sent from the low-frequency clock counting section and for generating periodic reception start signals when the count of high-frequency clock signals counted by the second high-frequency clock counting section reaches a predetermined number; the count setting section for setting a predetermined number of high-frequency clock signals to be counted by the second high-frequency clock counting section based on the number of high-frequency clock signals counted by the first high-frequency clock counting section and resetting the clock signal; and the high-frequency oscillation circuit stopping section for stopping the high-frequency oscillation circuit while the low-frequency clock counting section is counting low-frequency clock signals. 2. Periodic reception control device pursuant to claim 1. In any case, the second high-frequency clock counting section comprises a delay section for the time signal generated by the low-frequency clock counting section for a specified period and the start of the high-frequency clock counting based on the time signal delayed by the delay time; and the high-frequency oscillation circuit stopping section shall subsequently be the section for stopping the oscillation of the high-frequency oscillation circuit when the start edge is detected by the edge detection section and for restarting the oscillation of the high-frequency oscillation circuit when the time signal is output from the low-frequency clock counting section. 3. Intermittent reception control device pursuant to claim 1. In any case, the count setting section shall be used to set a predetermined number of high-frequency clock signals to be counted by the high-frequency clock counting section according to the set number of clock signals, which is determined by the counting period of the low-frequency clock counting section and the reception waiting period, and the number of high-frequency clock signals. 4. The interval reception control device provided in the receiving unit is for periodically receiving data transmitted from the master station at a set time for setting the interval reception time. This device consists of: a high-frequency oscillation circuit for oscillating and outputting a high-frequency clock signal with a cycle time shorter than the transmission cycle time for one bit of data on the master station; a low-frequency oscillation circuit for oscillating and outputting a low-frequency clock signal with a cycle time longer than the transmission cycle time for one bit of data on the master station; a high-frequency clock counting unit for counting the number of high-frequency clock signals output from the high-frequency oscillation circuit; a low-frequency clock counting unit for counting the number of low-frequency clock signals output from the low-frequency oscillation circuit; and an interval reception control unit for counting the interval reception time using the high-frequency clock counting unit and the low-frequency clock counting unit, and for stopping the oscillation of the high-frequency oscillation circuit while the low-frequency clock counting unit is counting the number of low-frequency clock signals output from the low-frequency oscillation circuit. 5. Intermittent reception control device pursuant to claim 4. In what case does the intermittent reception control consist of a setting section for determining the period to stop the oscillation of the high-frequency oscillation circuit according to the number of low-frequency clock signals counted by the low-frequency clock signal counting section, and an oscillation switching section for switching the oscillation of the high-frequency oscillation circuit according to a period determined by the central setting? 6. Intermittent reception control device pursuant to claim 5. In any case, the intermittent reception control device includes a delay section for delaying the start of the high-frequency clock signal counting by the high-frequency clock signal counting section. 7. The interval reception control device, provided in the receiving unit, is for periodically receiving transmitted data from the base station at a specified period for setting a timer to restart interval reception after the interval reception is stopped. This device consists of: a high-frequency oscillation circuit for oscillating and outputting a high-frequency clock signal with a cycle period shorter than the transmission cycle period for one bit of data on the base station; a low-frequency oscillation circuit for oscillating and outputting a low-frequency clock signal with a cycle period longer than the transmission cycle period for one bit of data on the base station; an edge detector for detecting the edge of the low-frequency clock signal exiting the low-frequency oscillation circuit; a first high-frequency clock counting unit for counting the number of high-frequency clock signals exiting the high-frequency oscillation circuit after the receiving unit begins waiting for transmitted data from the base station until the start edge is detected by the edge detector; and a low-frequency clock counting unit for receiving the number of low-frequency clock signals after the start edge is detected by the edge detector and for generating a timing signal. When the count of high-frequency clock signals counted by the low-frequency clock counting section reaches a predetermined number, the second high-frequency clock counting section is used to count the number of high-frequency clock signals after the time signal is sent out from the low-frequency clock counting section and for generating the time signal to start periodic reception when the count of high-frequency clock signals counted by the second high-frequency clock counting section is a predetermined number; and the high-frequency oscillation circuit stopping section is used to stop the high-frequency oscillation circuit while the low-frequency clock counting section is counting low-frequency clock signals. 8. Intermittent reception control device pursuant to claim 7. In any case, the second high-frequency clock counting section consists of a delay section for the time delay created by the low-frequency clock counting section for a specified period and begins the high-frequency clock counting according to the time delay signal created by the delay section. 9. Intermittent reception control device pursuant to claim 8. In any case, the high-frequency oscillation circuit stop section will stop the high-frequency oscillation circuit when the start edge is detected by the edge detection section and restart the high-frequency oscillation circuit when the time signal is output from the low-frequency clock counting section. 10. Method for controlling interval reception: For interval reception, data transmitted from the base station at a specified period and for setting the interval reception time consists of the following steps: counting the interval reception time by the first clock signal; counting the remaining interval reception time by the second clock signal, which has a higher frequency than the first clock signal; and pausing the output of the second clock signal while the interval reception time is being counted by the first clock signal. 11. Method of control of succession under claim 10: In any case, the frequency of the first clock signal shall be lower than the frequency of the data transmitted from the master station; and the frequency of the second clock signal shall be higher than the frequency of the data transmitted from the master station. 12. The method of periodic reception control under claim 11 consists of a step of generating a time signal when the counting step by the first clock signal reaches a predetermined value which coincides with the point at which the counting step by the second clock signal is started when the time signal is generated. 13. The method of controlling succession under claim 12 is further comprising the procedure for calculating the remaining period based on the specified values and specified time periods. 14. The method of controlling succession under claim 13 is further comprised of a step for delaying the counting stage by a second clock signal when the time signal is generated. 15. The method of controlling succession under claim 12 is further comprised of a step for delaying the counting step by a second clock signal when the time signal is generated.