SU993480A1 - Fractional rate scaler - Google Patents

Description

The invention relates to a pulse technique and can be used in frequency conversion units of time and exemplary instrumentation, measuring devices, communications and data transmission devices, automation devices, which include computing devices, such as microprocessors.

The fractional frequency divider is known, which contains a variable integer division factor frequency divider, adders, a reference element and a delay unit tl 3. The disadvantages of the known device are limited functionality and low reliability.

The closest in technical essence to the present invention is a pulse frequency divider with a fractional division factor, containing a variable divider frequency divider, one input of which is connected to the input bus, the second input to the first control bus, the third input to the first output of the comparison unit The input of which is connected to the outputs of two adders, the first inputs of which are connected to the second and third bus

control, the second input of one adder is connected to the output of the second. adder, and the output of the frequency divider with a variable division factor through the delay element is connected to the output bus, the memory unit, the first and second inputs of which are connected to the outputs of the adders, two valves multiplier and divisor numbers, inputs

10 of which is connected to the third and fourth control signal buses, and the output is connected to the first input of the number multiplier, the second input of which is connected to the output of the holding element 15 and the first inputs of the valves, the second inputs of which are connected to the outputs of the comparison unit, and the outputs of the valves are connected to the third and the fourth input of the memory block, the output of which is connected to the third input of the multiplier of numbers, with the output of which the control input of the controlled delay element is connected. The disadvantage of the divider is

25 limited functionality, as it is not designed to work in the composition of the funds that have their own computing device. For example, when applied in

30 digital phase system

auto-tuning with a digital pulse phase detector1 {torus the phase error code of the fractional divider m0-. It can be taken into account when generating the output code of a digital pulse-phase detector. For this and similar applications in the fractional divider, it is important not to compensate for the phase error, but to obtain the exact code value of this error at each successive output pulse. In addition, the divider has low reliability,

The purpose of the invention is to enhance the functionality while improving reliability.

To achieve the goal, the fractional pulse frequency divider containing the adder, the bit outputs of which are connected to the corresponding inputs of the storage unit, the outputs of which are connected to the first group of inputs of the adder, the frequency divider with a variable division factor, the first input of which is connected to the input bus, bit inputs - with the first group of control buses, and output through the delay element - with the first input of the valve, the element OR, the trigger and the multiplexer are introduced, the first and second control inputs of which are connected with the single and zero outputs of the trigger, the first and second information groups of inputs, respectively, with the second and third groups of control buses, and the outputs with the second group of inputs of the adder, the outputs of all bits of which, except the sign and high, are connected to the code buses corrections, and the high-order output to the second input of the valve, the output of which is connected to the first single trigger input and the first input of the OR element, the second input of which is connected to the output of a frequency divider with a variable division factor and the zero input of the flip-flop, and an output - a write enable input of the memory unit, an output MSB of which is connected to the third input of the frequency divider with variable division ratio.

The drawing shows the structural scheme of the divider.

The divider contains the element OR 1, the divider 2 frequencies with a variable division factor, the valve 3, the delay element 4, the trigger 5, the storage block b, the multiplexer 7, the adder 8, the input bus 9, the first group of buses 10 controls the whole part code. the second group of tires 11 control code numerator fractional part of the division factor, the third group 12 control code denominator fractional part

the division factor; the correction code bus 13; the output bus 14;

The division factor of divider 2 can have one of two values K A or K2 A + 1, where A is whole

the fractional division ratio of the device. The value .K is set at a logical zero, the value K - at a logical one at the third input of divider 2, the Code of the number A

is fed to bus "s 10, on bus 11 is fed direct, and on bus 12 - reverse code, respectively, the numerator and denominator of the fractional coefficient K, Therefore, the adder in is calculated on

working with reverse codes of numbers

(the transfer chain from sign bit to low is not shown in the drawing), Delay Element 4 serves to delay the signal by the transient time

processes in multiplexer 7. and adder 8, trigger 5 controls the multiplexer If which transmits to the adder 8 a code from bus 11 with zero and with bus 12 with one state

trigger 5, if the adder is 8 binary, then the codes on buses 11 - 13 are also binary. On tires 10, the code corresponds to the type of divider 2, Required, the unit size of blocks 6–8 of the device is determined by

that the weight of the high bit of the adder 8 must satisfy the inequality

 Rtakuyu, ah, .- the greatest possible

where is fwrtKC

the value of the denominator of the fractional part K.

The fractional frequency divider of the follow-up pulse is as follows.

Let X be a logical variable at the third input of divider 2, If O, then divider 2 works with coefficient KA, and if X1, then with factor KA-I, Accordingly, the next output pulse of the device shifts towards the front or back, because

(AH) / fg,

-)

where aL is the fractional ratio of laziness; о / ft - numerator and denominator

its fractional part; f is the pulse frequency at the device input. When a divider 2 is triggered with a division factor A, the output pulse is shifted in the direction of advance by

“4 A -oL. 01

Claims (2)

Wi. When triggered with a factor (A + 1}, the output pulse shifts to the side lagged by the value of -vr-T V 2 11 I I.II. I .. I ..a tft 6X) Denoting l / () o, we turn to the rated time t. Then we will get.) (ZU Magnitude. The long-term dimension of time is a quantum of resolution, since the error of the temporary position / output of the device’s output pulse can be expressed only by the number of quanta. This is explained by the fact that for any combination of n actuations with coefficient A and the number m of operations with factor (A + 1): error of expression zhazhsya (:; ummah type L-tWcJ-W () LT | .., Accounting for the error code during further processing of information makes the fractional divider look like an ideal divider with fractional coefficients. Without taking into account the code of retranslation, the instability of the output pulse period is not greater than One period of the frequency that corresponds to the error quanta.The device operates in cycles, Jboa cycle ends with the appearance on tires 14 and 13 according to the output pulse and the error code of its time position, expressed in the number of quanta, and any output pulse with a bus 14 starts vovy 1st cycle consisting next pulse from the bus 14 arrives through Elet "ent 1 input resolution Vo ice unit 6 rewrites of the amount of the torus 8 in block 6 predvDUSchy code error itif,;,; simultaneously with the flush, trigger 5 (or its zero state is confirmed); the code of the number 0 through the multiplexer 7 is fed to the adder 8 in the adder 8, the code of the number i is formed, after a delay of the transition time. processes in trigger 5, multiplexer 7, adder 8, the pulse from delay element 4 arrives at the input of valve 3. Further processes depend on the sum value of LSn. If Atl / j ,, 2, then zero is written in the atresham discharge of adder 8 locked in the adder, the code of the number remains, determined by the ratio 4). If At, - 7 / -2, then in the high order of the adder 8 a unit is recorded, thereby the valve 3 is opened, the pulse from the delay element 4 is opened. Therefore, the process will continue as follows: through element 1, a pulse is fed to the input. Recording resolution of block b, thus the code from adder 8 with a unit into a discharge with weight 2 is rewritten into block 6; trigger 5 goes to the unit state and ensures the arrival of a number code (- /) from busses 12 through multiplexer 7 to adder 8, in which the sum X2.- i -ib - & t4 .- (p-ot) is formed ( at) . From this it follows that after the considered processes the code in the adder 8 always corresponds to a positive number less than 2, If in the cycle the code of the adder 8 corresponds to a high (4), then the next operation of divider 2 occurs with the coefficient K | (A, and if ), then the coefficient Ky. is set as required according to expressions (1) - (3). The cycle is completed by issuing the next pulse to bus 14 when: the corresponding new correction code is present on the tires 13. Next, the processes are repeated. The correction code is calculated exactly without or rounding. This allows for the ultimate use of the output information to be limited to the number of digits of the correction code that is actually necessary. The fractional pulse frequency divider containing an adder, the bit outputs of which are connected to the corresponding inputs of the storage unit, the outputs of which are It is connected to the first group of inputs of the adder, a frequency divider with a variable division factor, the first VHBD of which is connected to the input bus, the bit inputs to the first group of control buses, and the output through the delay element to the first input, a valve, characterized in that in order to extend the functionality while increasing reliability, an element or trigger is introduced into it and a multiplexer, the first and second control inputs of which are connected respectively to the single and zero outputs of the trigger, the first and second information groups of the inputs respectively 1o with the second and third groups of control buses, and the outputs with the second group of inputs of the adder, the outputs of all bits of which, except sign and high, connected to the correction code tires, and the high-order output to the second input of the valve, the output of which is connected to the first single trigger input and the first input of the OR element, the second the input of which is connected to the output of a frequency divider with a variable division factor and zero input of the trigger, and the output is connected to the input of a permit. recordings of the storage unit, the higher output of which is connected to the third input of a frequency divider with a variable division factor, Information sources, taken into account in examination 1, USSR Copyright Certificate. No. 744990, cl. H 03 K 23 / 00,11.01.78. 2. USSR author's certificate No. 750744, cl. H 03 K 23 / 02,18.11.78. fff Jr 1f 0 V --- N one at  i. L V A L L.t.LC //