SU987833A1 - Clock synchronization device - Google Patents

Description

(54) TLKT SYNCHRONIZATION DEVICE

The invention relates to the technique of transmitting discrete signals over channels with intersymbol interference and can be used in signal conversion devices (models) with phase difference modulation.

A clock synchronization device is known, comprising a series-connected reference generator and. a frequency divider, to the control in- terface of which the output of the comparison unit is connected, and two processing channels, each of which includes a phase detector and a band-pass filter {.1.3 "The disadvantage of this clock synchronization device is its low noise immunity during channel operation with intersymbol interference. The purpose of the invention is to increase noise immunity when working on channels with intersymbol interference.

To achieve this goal, a clock synchronization device containing a series-connected reference oscillator ii. A frequency divider, to the control input of which the output of the comparator unit is connected, and two processing channels, each of which includes a phase detector. torus and bandpass filter

The processing channel is connected in series with a threshold unit, a trigger and a phase shifter, as well as a delay element;

10 an amplitude detector input, the output of which is connected to the corresponding input of the comparator unit, the signal inputs of the phase detectors of both processing channels being combined

15 with the input of the charge element, the output of which is connected to the control input of the phase shifter of each processing channel, and the corresponding outputs of the frequency divider are connected to the other inputs of the triggers of both processing channels.

The drawing shows a structural electrical circuit of the device.

Clock synchronization device

25 contains processing channels 1 and 2, a reference generator 3, a frequency divider 4, a comparison unit 5 and a delay element b, each processing channel consisting of a phase detector 7 (7), a threshold block 8 (8), a trigger

Claims (1)

30 3 9 (9), phase shifter 10 (10), band-pass filter 11 (11) and amplitude detector 12 (12). The clock synchronization device operates as follows. The phase-manipulated signal received from the communication channel is the sum of the interference components. Under the boundaries of the parcels of one and the components with the highest level, the device is adjusted. When this input signal is supplied to the signal inputs of the phase detectors 7 and 7 of both channels 1 and 2 processing. The second input of the phase detector 7 (7) is supplied with a carrier frequency reference signal, normalized at the output of the band-pass filter 11 (11). The output signal of the phase detector 7 (7) is extremely limited in amplitude by the use of the threshold block 8 (8), and the sign of the resulting signal (test binary solution) is recorded in clock pulses in triggers 9 and 9. The signal from the output of the reference oscillator 3 is fed to the input of a divider 4 frequency, the outputs of which form pulse sequences of clock frequencies that are shifted between themselves in time by half the period of the clock frequency. In this case, the recording moments in the triggers 9 and 9 will be separated in time by half the duration of the elementary parcel. In the phase shifter 10 (S), an inverse operation of the phase manipulation performed on the transmission is performed over the input signal. When the delayed element b of the received phase-manipulation signal is multiplied by the separated test binary solutions in the phase shifter 10 (10), only one of the components to which these solutions correspond is removed. Multiplying the signal of other components by binary solutions that do not correspond to these components leads only to additional random manipulation. Further, the signal from the output of the phase shifter 10 (10) is averaged by a band-pass filter 11 (). Since the most reliable binary solutions correspond to the component with the highest level, the phase of the carrier signal at the output of the band-pass filter 11 (11) will be adjusted to this largest component. This, in turn, leads to an increase in the reliability of trial binary solutions corresponding to a given component at the HHMaeMqro signal, and further, to a more accurate selection of the signal of the carrier frequency of this component. This means that the device makes it possible to significantly suppress the interfering components in the information signal and select one of them, the most intense, which will be further adjusted to the clock pulses for the bounds of the parcels. The level of the signal at the output of the bandpass filter 11 (11) depends on the displacement of the boundaries of the elementary premises of the signal with respect to the pulses of the clock frequency coming from the outputs and the divider 4 frequencies. With an increase in the desynchronization of the phase of the borders of the elementary premises of the information signal (the component with the highest level) relative to the local clock frequency, the level of the extracted reference signal decreases. Using an amplitude detector 12 (12), a carrier frequency envelope is generated. Once per clock period, the comparison unit 5 performs a comparison on the level of the amplitude detectors 12 and 12 of the control signals allocated at the outputs and, depending on the result of this comparison i, adds or subtracts a pulse at the input of the 4-way divider. As a result, the phase adjustment of the local clock pulses at the outputs of frequency divider 4 is carried out by a certain amount. Such an adjustment will be made until the signal levels at the outputs of the amplitude detectors 12 and 12 are equal. If there is an adjustment, the pulse frequency signals at the outputs of frequency divider 4 will be shifted relative to the boundaries of the elementary parcels — the component of the information signal with the highest level, respectively, in the direction of advance and in the direction of lag by 1/4 of the duration of the package. Thus, the introduction of a nonlinear element into each of channels 1 and 2 (threshold blocks 8 and 8 and flip-flops 9 and 9) makes it possible to choose from the received phase-shifted signal with intersymbol interference the component with the highest level, the manipulation law of which corresponds to the selected binary solutions. As a result, the clock pulses will be adjusted for this component in phase. In the proposed clock synchronization device, the dependence of the phase position of the clock pulses during the transition from one component to another is clearly expressed on-off character. With fading interference components, this allows quick automatic adjustment of the most intense components of the received signal. This feature provides a significant increase in the noise immunity of clock synchronization during its operation over channels with strong intersymbol interference and, above all, in short-wave radio communications. Tests have confirmed the stable operation of the proposed device with different ratios between 1 interference components and a significant reduction in the loss of confidence in the reception of binary signals as compared to the known, when using this device in a model for transmitting discrete signals over KB radio channels. The invention of a clock synchronization device containing a series-connected reference oscillator and a frequency divider, to the control input of which the output of the comparator unit is connected, and two processing channels, each of which includes a phase detector and a band-pass filter, is about one million. This is due to the fact that, in order to improve noise immunity when working on channels with intersymbol interference, sequentially connected threshold block, trigger and phase shifter, as well as a delay element are introduced into each processing channel In this case, in each processing channel, the output of the phase detector is connected to the input of the threshold unit, the output of the phase shifter through a band-pass filter is connected to the control input of the phase detector and to the input of the amplitude detector, the output of which is connected to the corresponding input of the comparison unit, and;: ignition inputs of the phase detectors Both processing channels are combined with the input of the delay element, the output of which is connected to the control input of the phase shifter of each processing channel, and to the other inputs of the triggers of both processing channels By connecting the corresponding outputs of the frequency divider. Sources of information taken into account during the examination 1. USSR Author's Certificate No. 6286225, class, N 04 L 7/02, 1978 (. Prototype).