SU985947A1

SU985947A1 - Frequency synthesizer

Info

Publication number: SU985947A1
Application number: SU802990790A
Authority: SU
Inventors: Даниил Григорьевич Нисневич; Владимир Леонидович Гусев; Людмила Константиновна Максимченкова
Original assignee: Предприятие П/Я В-8828
Priority date: 1980-10-08
Filing date: 1980-10-08
Publication date: 1982-12-30

Description

Изобретение относится к радиотехнике и может быть использовано в технике свя зи, радиолокации и импульсной технике. Известен синтезатор частот, содержащий соединенные в кольцо управляемый генератор, делитель частоты с переменным з коэффициентом деления, фазовый детектор, сумматор и фильтр нижних частот, последовательно соединенные частотный дискриминатор и блок предварительной настройки, первый выход которого подключен к другому входу сумматора, последовательно соединенные опорный генератор и делитель опорной частоты, при этом первый вход частотного дискриминатора подключен к выходу делителя частоты с перемен-’⁵ным коэффициентом деления, а вторые входы фазового детектора и частотного дискриминатора объединены и подключены к выходу делителя опорной частоты, и фор-, мирователь кодов коэффициентов деления, первый выход которого соединен с управляющим входом делителя частоты с переменным коэффициентом деления 11 ] .The invention relates to radio engineering and can be used in communication, radar and pulse technology. A known frequency synthesizer comprising a controlled oscillator connected in a ring, a frequency divider with a variable division coefficient, a phase detector, an adder and a low-pass filter, a frequency discriminator connected in series, and a preset unit, the first output of which is connected to another adder input, a reference oscillator connected in series and reference divider, the first input of a frequency discriminator connected to the output of the frequency divider with a variable ^'5 nym division factor and sec e inputs of the phase detector and a frequency discriminator coupled and connected to the output of the reference frequency divider and for-, tors, code division ratios, a first output connected to the control input of the frequency divider with a variable division factor 11].

Недостатком известного синтезатора частот является малое быстродействие, определяемое номиналом частоты сравнения и количеством циклов регулирования при настройке на требуемую частоту.A disadvantage of the known frequency synthesizer is its low speed, determined by the nominal frequency of the comparison and the number of control cycles when tuning to the desired frequency.

Цель изобретения — повышение быстродействия.The purpose of the invention is improving performance.

Поставленная цель достигается тем, что в синтезатор частот, содержащий со— единенные в кольцо управляемый генератор, делитель частоты с переменным коэффициентом деления, фазовый детектор, сумматор и фильтр нижних частот, последовательно соединенные частотный дискриминатор и блок предварительной настройки, первый выход которого подключен к другому входу сумматора, последовательно соединенные опорный генератор и делитель опорной частоты, при этом первый вход частотного дискриминатора подключен к выходу делителя частоты ς переменным коэффициентом деления, а вторые входы , фазового детектора и частотного дискриминатора объединены и подключены к вы— to ходу делителя опорной частоты, и формирователь кодов коэффициентов деления, первый выход которого соединен с управляющим входом делителя частоты с переменным коэффициентом деления, между другим выходом блока предварительной настройки и входом формирователя кодов коэффициентов деления введены последовательно соединенные индикатор настройки и задатчик коэффициентов деления, а между вторым выходом формирователя кодов коэффициентов деления и другим входом, задатчика коэффициентов деления введен анализатор точности установки частоты, другой вход индикатора настройки соеди нен с третьим выходом формирователя ко-, дов коэффициентов деления, а делитель опорной частоты выполнен в виде делителя частоты с переменным коэффициентом деления- и его управляющий вход под- . ключей к четвертому выходу формирователя кодов коэффициентов деления.This goal is achieved by the fact that in a frequency synthesizer containing a controlled oscillator connected in a ring, a frequency divider with a variable division coefficient, a phase detector, an adder and a low-pass filter, a frequency discriminator and a preset unit connected in series, the first output of which is connected to another the adder input, the reference generator and the reference frequency divider connected in series, while the first input of the frequency discriminator is connected to the output of the frequency divider ς by variables by the division factor, and the second inputs of the phase detector and the frequency discriminator are combined and connected to the output of the reference frequency divider, and the code generator of the division coefficients, the first output of which is connected to the control input of the frequency divider with a variable division ratio, between the other output of the preset unit and a dividing factor code generator and a dividing coefficient adjuster are connected in series with the input of the code generator of the division coefficients, and between the second output of the code generator dividing coefficients and another input, a dividing coefficient setter, a frequency setting accuracy analyzer is introduced, another input of the tuning indicator is connected to the third output of the code former, dividing coefficient codes, and the reference frequency divider is made in the form of a frequency divider with a variable dividing coefficient - and its control input sub. keys to the fourth output of the generator codes codes division.

На чертеже приведена структурнаяэлектрическая схема синтезаторачастот.The drawing shows a structural electrical circuit of a frequency synthesizer.

Синтезатор частот содержит управляемый генератор 1, делитель частоты с переменным коэффициентом деления (ДПКД) 2, фазовый детектор (ФД) 3, 'опорный генератор 4, делитель 5 опорной частоты, формирователь 6 кодов коэффициентов де— пения, частотный дискриминатор 7, блок 8 предварительной настройки, сумматор 9, фильтр нижних частот (ФНЧ) 10, индикатор 11 настройки, анализатор 12 точности установки частоты и задатчик 13 коэффициентов деления.The frequency synthesizer contains a controlled oscillator 1, a frequency divider with a variable division coefficient (DPKD) 2, a phase detector (PD) 3, a reference oscillator 4, a frequency divider 5, a frequency shaper 6 of the coefficient codes, frequency discriminator 7, block 8 preliminary settings, adder 9, low-pass filter (LPF) 10, indicator 11 settings, the analyzer 12 accuracy of the frequency setting and the unit 13 of the division factors.

Синтезатор частот работает следующим образом.The frequency synthesizer works as follows.

Процедура настройки синтезатора со— I стоит из двух этапов. Первый этап - пред-’ , верительная грубая настройка, осуществляемая блоком 8 предварительной настройки^!по 'сигналам’ частотного дискриминатора 7. Блок 8 предварительной настройки осуществляет сканирование управляющего напряжения, запоминает уровень напряжения настройки, вырабатывает сигнал окончания этапа. Частота управляемого генератора 1 вводится в полосу синхронизации контура фазовой автоподстройки частоты, в состав которого входит ДПКД 2, ФД 3, сумматор 9 и ФНЧ 10.The procedure for tuning the synthesizer consists of two stages. The first stage is a pre- ', rough, coarse tuning performed by block 8 of the pre-setting ^! based on the 'signals' of the frequency discriminator 7. The preset unit 8 scans the control voltage, remembers the voltage level of the setting, and generates a signal for the end of the stage. The frequency of the controlled generator 1 is introduced into the synchronization strip of the phase-locked loop, which includes the DPKD 2, PD 3, adder 9 and low-pass filter 10.

На втором этапе настройки по сигналу ФД 3 производится точная настройка управляемого генератора 1 на требуемую частоту. При этом возможны два режима работы, выбор которых осуществляется задатчиком 13 коэффициентов деления по сигналу анализатора 12.At the second stage of tuning by the signal of ФД 3, the controlled generator 1 is precisely tuned to the required frequency. In this case, two operating modes are possible, the selection of which is carried out by the adjuster 13 of the division factors by the signal of the analyzer 12.

Задатчик 13 коэффициентов деления принимает решение о. режиме работы формирователя 6 кодов коэффициентов деления ДПКД 2 и делителя 5 опорной частоты.The unit 13 of the division factors makes a decision about. the operating mode of the shaper 6 codes of the division coefficients of the DPKD 2 and the divider 5 of the reference frequency.

Алгоритм принятия решения можно описать следующим образом:The decision-making algorithm can be described as follows:

, с=аЬ, где С. - выходной сигнал задатчика 13 коэффициентов деления, задающий режим работы формирователя 6 кодов с коэффициентами деления п_дпк^ и ηθ_Γ ;, c = ab, where C. is the output signal of the setter 13 of the division coefficients, specifying the operating mode of the shaper 6 codes with the division coefficients n _dpk ^ and ηθ _Γ ;

С - выходной сигнала задатчика 13 коэффициентов деления, задающий режим работы формирователя 6 кодов с коэффициентами деления ^дпкд ^{м п}ог '»C is the output signal of the setter 13 division coefficients, specifying the operating mode of the shaper 6 codes with division coefficients ^ dpcd ^{m p} og '

Ь — выходной сигнал индикатора 11 настройки, соответствующий этапу точной настройки;B is the output signal of the tuning indicator 11 corresponding to the fine tuning step;

- выходной сигнал индикатора 11 настройки, соответствующий этапу рительной настройки; ^пАпкд>^пд“ коэффициенты деления 2 соответственно на этапе точной варительной настройки;- the output signal of the tuning indicator 11, corresponding to the stage of rhythmic tuning; ⁿ Apkd> ^p d “division factors 2, respectively, at the stage of fine tuning;

^П or I ля 5 этапе a ^P or I la 5 stage a

ДПКД и предделите12, на частоты сигнал с ^{7 т}зад точность гп 4 ш _Эа д ;DPKD and predelteyte12, at a frequency signal from ^{7 t} back accuracy gp 4 w _Ea d;

выхода анализатораanalyzer output

12, за— »12, for— "

установки частоты, п’_ог - коэффициенты деления опорной частоты соответственно на точной и предварительной настройки; - сигнал с выхода анализатора если точность настройки синтезатора номиналfrequency settings, n ' _og - division factors of the reference frequency, respectively, on the exact and preliminary settings; - signal from the analyzer output if the synthesizer tuning accuracy is nominal

S если m данная для данного синтезатора.S if m is given for a given synthesizer.

Задатчик 13 коэффициентов деления может быть реализован с помощью комбинационной логической схемы.The unit 13 of the division coefficients can be implemented using a combinational logic circuit.

Формирователь 6 кодов выполняет следующие операции: вычисляет значения коэффициентов п_дпкди п_ог и запоминает их; при помощи аппарата ценных дробей вычисляет значения ^п _дпкдИ п’_ог и запоминает их; на этапе предварительной настройки по команде с задатчика 13 коэффициентов деления подает на управляющие входы ДПКД 2 и делителя 5 опорной частоты коды коэффициентов деления п_дпкди п'_ог, а на этапе точной настройки коды Пд_п(сдип[)_Г или Пд_пкд ип_ог ; вычисляет относительную точность m полученного приближения подходящей дроби и выдает значение ш на один из входов анализатора 12 точности.Shaper 6 codes performs the following operations: calculates the values of the coefficients p _dpc di p _og and remembers them; using the apparatus of valuable fractions, calculates the values of ^p _dpc dI p ' _og and stores them; at the stage of presetting, upon the command from the setpoint 13, the division coefficients supplies the codes of division coefficients p _dpcd and p ' _og to the control inputs of the DPKD 2 and the divider 5 of the reference frequency, and at the stage of fine-tuning the codes _{pd p (sd} ip [) _G or PD _pc ip _og ; calculates the relative accuracy m of the obtained approximation of a suitable fraction and outputs the value of w to one of the inputs of the accuracy analyzer 12.

Функции формирователя 6 кодов могут быть реализованы микро-ЭВМ с соответствующими характеристиками.The functions of the shaper 6 codes can be implemented by micro-computers with the corresponding characteristics.

Анализатор 12 точности запоминает значение точности настройки <*а55 данной для данного синтезатора, сравнивает значение т_?г,д ^{с 01} > поступившим от формирователя 6 кодов и вырабатывает следующие сигналы для задатчика 13 коэффициентов деления а или 3. 5The accuracy analyzer 12 remembers the value of the tuning accuracy <* a55 given for this synthesizer, compares the value m _{? D} ^{with 01} > received from the shaper 6 codes and generates the following signals for the adjuster 13 division factors a or 3. 5

Анализатор 12 точности может быть реализован с помощью.запоминающего устройства и комбинационной логической схе— мы.The precision analyzer 12 can be implemented using a storage device and a combinational logic circuit.

Начало и конец первого этапа опреде— ¹⁰лаются индикатором 11 настройки, который подает соответствующий сигнал на задатчик 13 коэффициентов деления.The beginning and the end of the first stage are determined — ^{10 are} determined by the setting indicator 11, which supplies the corresponding signal to the dial 13 of division factors.

Алгоритм определения этапа можно описать следующим образом ^1S b=de , Ь= х/ё , где d - сигнал начала этапа предварительной настройки с выхода формирователя 6 кодов; 20 е - сигнал окончания этапа предварительной настройки с выхода блока 8 предварительной настройки. Кроме того, инди— катор 11 настройки запоминает факт выработки сигналов Ь и Ь на время соот- 25 ветствуюшего этапа.The algorithm for determining the stage can be described as follows: ^1S b = de, b = x / e, where d is the signal of the beginning of the presetting stage from the output of the generator 6 codes; 20 e is the signal for the end of the presetting stage from the output of the presetting unit 8. In addition, the tuning indicator 11 remembers the fact that the b and b signals were generated for the duration of the corresponding stage.

Предлагаемый синтезатор частот дает возможность повысить быстродействие, - так как в нем сокращается наиболее продолжительный этап-этап предварительной 30 настройки на любую частоту из дискретного множества. При этом сохраняется высокая точность установки требуемого номинала выходной частоты.The proposed frequency synthesizer makes it possible to increase speed, since it reduces the longest stage — the stage of preliminary 30 tuning to any frequency from a discrete set. At the same time, high accuracy of setting the required output frequency rating is maintained.

Claims

(54) FREQUENCY SYNTHESIZER The invention relates to radio engineering and can be used in communication technology, radio broadcasting and pulse technology. Known frequency synthesizer containing connected in the cold controlled oscillator, frequency divider with variable doleav, phase detector, adder low pass filter, serially connected frequency discriminator and presetting unit, the first output of which is connected to the dual input of the adder, serially connected reference oscillator and a divider of the reference frequency, with the first input of the frequency discriminator connecting the check to the output of the frequency divider with a variable division factor, and the second The inputs of the phase detector and frequency discriminator are combined and connected to the output of the reference frequency divider, to form the dividing coefficients codes, the first output of which is connected to the control input of the frequency divider with the dividing coefficient dl tl}. A disadvantage of the known frequency synthesizer is the low speed, which is determined by the reference frequency and the number of adjustment cycles when tuned to the desired frequency. The purpose of the invention is to increase speed. Delivered del is achieved by the fact that in a frequency synthesizer containing a controllable oscillator connected in a ring, a divider often with variable division factor, a phase detector, an adder and a low-pass filter connected in series to a frequency discriminator in a presetter, the first output of which is connected to another input adder, serially connected reference oscillator and frequency divider, while the first input of the frequency discriminator is connected to the output of the frequency divider q variables the dividing factor, and the second inputs, the azov detector and the frequency discriminator are combined and connected to the output of the frequency divider, and the driver of the dividing coefficient codes, the first output of which is connected to the control input of the frequency divider with a variable division factor, between the other output of the presetting unit and the input of the dividing coefficient codes maker are entered in series the setup indicator and the dividing coefficient setting master, and between the second output of the kodo formatter KoE (1scheneniye division and another input, the divider factor adjuster introduced a frequency setting analyzer, another tuning indicator input is connected to the third output of the former DON division factors, and the reference frequency divider is executed as a frequency divider with a variable division factor - and its control input connected to the fourth output of the dividing coefficient coder. The drawing shows a structural electrical circuit of a frequency synthesizer. The frequency synthesizer contains a controlled oscillator 1, a frequency divider with a variable division factor (DPKD 2, a phase detector (PD) 3, a reference oscillator 4, a divider 5 of the reference frequency. Shaper 6 division ratio codes, frequency discriminator 7, block 8 preliminary settings, adder 9, low-pass filter (LPF) 1O, tuning indicator 11, frequency setting analyzer 12 and division factor setting unit 13. The frequency synthesizer works as follows. The synthesizer tuning procedure consists of two stages. Tap - Prev, coarse tuning, performed by preset tuning unit 8 by frequency discriminator signals 7 Preset tuning unit 8 scanning control voltage, remembers the tuning voltage level, generates a stage ending signal. The frequency of the controlled oscillator 1 is entered into the band synchronization of the phase locked loop, which includes DPKD 2, PD 3, adder 9 and LPF 10. At the second stage of tuning, according to the PD signal 3, the controlled tuning is performed. 1 for generators at the desired frequency. In this case, there are two possible modes of operation, the selection of which is carried out by the unit for adjusting the modulus 13 of the partitioning factor by the signal of the analyzer 12. The unit 13 for the division factors makes a decision on. the mode of operation of the farmer is 6 codes for the DPKD 2 division coefficients and divider 5 of the reference frequency. The decision algorithm can be described as follows:,, where C is the output signal of the generator of 13 division coefficients, which specifies the mode of operation of the generator of 6 codes with the division coefficients D and R; C - output signal of the setting unit 13 of the division factors, setting the mode of operation of the imaging unit 6 codes with a factor of 4) division octants b - output signal of the setting indicator 11, corresponding to the fine tuning step; B is the output signal of the setting indicator 11, corresponding to the presetting stage I of the AECC and the division coefficients of the PDKD 2, respectively, at the stage of precise and preliminary tuning; - division factors divide og, ogl 5 of the reference frequency, respectively, at the stage of fine tuning and presetting; a is the signal from the output of the analyzer 12, if the accuracy of the tuning of the synthesizer to the nominal frequency t gzzdd, 5 - the signal from the output of the analyzer 12, if m 7 m jQ is the accuracy of the frequency setting, measured for this synthesizer. The unit 13 of the division factors can be implemented using a combinational logic circuit. The code generator 6 performs the following operations: it calculates the values of the coefficients n and remembers them; with the aid of the apparatus of valuable fractions and memorizes the values of pdcA, it detects them; at the presetting stage, by command from the setting unit 13, the division factors feeds the control inputs Dpd, dI Gdr to the control inputs of the PDKD 2 and the divider 5 of the reference frequency, and at the stage of fine tuning the codes and POR or dpkd og; calculates the relative accuracy m of the approximation obtained using the fraction fraction of 5 percent and gives the value of m to one of the inputs of the precision analyzer 12. The functions of the former 6 codes can be implemented by microcomputers with corresponding characteristics. Accuracy analyzer 12 remembers the tuning accuracy value for a given synthesizer, compares the value received by the shaper 6 codes and generates the following signals for unit 13 of the dividing coefficients a or B, Accuracy analyzer 12 can be implemented using the memory device and the combinational logic circuit. The beginning and end of the first stage are determined by the setting indicator 11, which supplies the corresponding signal to the setpoint 13 of the division factors. The algorithm for determining the stage can be described as follows, b dvi, where “J is the signal of the beginning of the preliminary setting stage from the output of the driver 6 codes; e is the signal of the end of the pre-tuning step from the output of the pre-tuning block 8. In addition, the setting indicator 11 stores the fact of generation of signals fc and b for the time of the corresponding stage. The proposed frequency synthesizer makes it possible to increase the speed, since it shortens the longest stage — the stage of preliminary tuning to any frequency from a discrete set. At the same time, the accuracy of setting the required output frequency is maintained. Claims of the Invention A frequency synthesizer comprising a controllable oscillator connected in a ring, a variable division factor frequency divider, a phase detector, an adder and a low-pass filter, frequency discriminator connected in series, and a presetter whose first output is connected to another input of the adder are serially connected reference reference frequency generator and divider, (at the same time, the first hrd1 frequency discriminator is connected to the output of a frequency divider with a variable coefficient divided by and, and the second inputs of the phase center and frequency discriminator are combined and connected to the output of the reference frequency divider, and the division factor codes generator, the first output of which is connected to a variable division frequency divider control input, different .Teiyj, which is for the purpose of speed , between the other output of the presetting unit and the input of the generator of the dividing coefficient codes, a sequential connected indicator of the tuning and the setting unit of the dividing coefficients are entered, and between the second output of the dividing coefficient codes maker and another input of the dividing coefficients setting unit introduced a frequency setting accuracy analyzer, another tuning indicator input is connected to the third output of the dividing coefficient codes generator, and the reference frequency divider is made in the form of a frequency division divider with a variable division factor and its control input podklk "whose to the fourth output shaper codes codes swaddling. Sources of information taken into account during the examination 1. M. Zaretsky, M. et al. Frequency synthesizers with a phase locked loop. L., Energie, 1974, p. 2O5 - 211 (prototype),