SU980114A1 - Device for receiving and majority decoding of information - Google Patents

Description

The invention relates to telemechanics and computing and can be used in adaptive systems for the transmission and processing of discrete information for the correction of errors during repeated duplication of messages.

A device for gshaptive majority decoding is known, which contains shift registers and logic elements and allows three, five or more repetitions of a message to be subjected to majority processing without losing intermediate results.

A disadvantage of this device is the limited functionality, which is shown in the fact that not all possible combinations of message repetitions are analyzed.

 The device for adaptive majority decoding of telemechanical duplicated signals, which is closest to the proposed technical entity, contains a series-connected key and counter, the parallel outputs of which are connected to the additional inputs of the And through the corresponding elements of AND and the shift register. decision makers

the block whose output is connected to the control input of the key, the fault input of which is combined with the second inputs of the elements IG 2.

A disadvantage of the known device is the low reliability, which is manifested in that the first three and a total of five repetitions of the message were subjected to majority processing,

10 the device does not analyze the third, fourth and fifth repetitions and does not carry out their majority processing. If the first three repetitions are subjected to intense interference, then it can be argued with a high probability that not all errors will be corrected by a known device after receiving five repetitions.

The purpose of the invention is to increase the reliability of the device.

The goal is achieved by the fact that in a device for receiving and majority decoding information containing a key, the input of which

25 is connected to the information input of the device, the output is connected to the first input of the counter, the first and second outputs of the counter are connected to the first inputs of the first and second switches, respectively, the third switch. the switch outputs are connected to the information inputs of the corresponding shift register registers, the outputs of which are connected to the first, second and third inputs of the decision block, the first output of which is connected to the first output of the device, the outputs of the first and second shift registers are connected respectively to the second and third inputs of the counter The code converter first, second and third outputs of the counter are connected to the first, second and third inputs, respectively, of the code. converter, the fourth input of which is combined with the first input of the third switch and the fourth input of the decision block and connected to the output of the input key, the first, second and third outputs of the encoder are connected to the second inputs of the corresponding switches, the output of the third shift register is connected to the fifth input of the encoder, n The first input of the decision block is connected to the second output of the counter, the second and fourth outputs of the last block are connected to the third inputs of the first and second switches, respectively, and output of the device. In addition, the code converter is made on cyNCMaTope, AND, OR and OR-NOT elements, the output of the first AND element is connected to the first input of the first OR element, the output of which is connected to the first inputs of the second and third OR elements, the output of the OR-NOT element is connected to the second input the second element OR, the output of the adder is connected to the first input of the second element -I, the output of which is connected to the second input of the third element IL, the first input of the first element AND is connected to the first input of the code converter, the second input of the first element AND is combined with the first m input of the element OR NOT and is connected to the second input of the code converter, the first input of the sum of the matrix is combined with the second input of the second pord of the AND element and connected to the fourth input of the code converter, the input of which is connected to the second input of the adder, the outputs of the second element OR, the adder and the third element OR are connected respectively with the first, second and third outputs to the subconverter. In addition, the decision block is made on the switches, prohibition elements. AND, OR, the output of the first element AND is connected to the first input of the first element OR, the second input of which is connected to the output of the first prohibition element, the output to the first input of the first switch, the output of the second prohibition element and the output of the second And element are connected to the first 1 and second the inputs of the second element IL: the output of which is connected to the first input of the second switch, the second input of which is connected to the output of the third element OR, the first inputs of the first element AND, the first prohibition element and the second input of the first switch are connected to n to the left input of the decision block, the first inputs of the second prohibition element, the second element And the third element OR are connected to the second input of the decision block, the second inputs of the first and second elements are connected to the third input of the decision block, the second inputs of the prohibition element and the second input of the third element OR are connected respectively to the fourth and fifth inputs of the decision block, the output of the first switch is connected to the first and second inputs of the decision block, the output of the second switch is connected to the third and fourth inputs deciding th block. This achieves the analysis and majority processing of the first three repetitions, five repetitions in general and the last three repetitions (third, fourth and fifth). If the first three repetitions are subjected to intense interference, then with high probability the correct reception will be carried out after the majority processing of the last three repetitions of the message. FIG. 1 shows a block diagram of a device for receiving and majority decoding information; FIG. 2 shows a code converter circuit; FIG. 3 is a diagram of a decision block. The device contains (FIG. 1) a key 1, a counter 2, a code converter 3, switches 4-6, shift registers 7-9 and a decision block 10 containing the first output 11, input 12, the second output 13 and inputs 14-17. Code Converter 3 contains (figure 2) elements AND 18 and 19, elements OR 20-22, element OR NOT 23 and adder 24 modulo two with negation. Solving -block 10 also contains elements AND 25 and 2.6, elements OR 27-29, prohibition elements 30 and 31, and switches 32 and 33. Key 1 is for entering information into the device. Counter 2 contains three binary bits 2.2 and 2 and is designed to count the number of received 1 for like-named host elements. Code converter 3, included in operation at the moment of the beginning of reception of the fourth repetition, converts the codes of the input signals, by its effect the original assignment of the shift registers. The operation of the code converter is specified using Table 1, which can be used to obtain logical conditions (expressions) Y (X + Xs) + X. .x7T 4 (), x ,, x, x state of the bits of the counter 2, counting the number 1 of the same element received, repeated, respectively; Xd,) is the value of the same-named bits of the fourth and fifth repetitions, respectively; Y is a decision signal for the same elements of four repetitions, and for Y 1 there is a predominance of elements of a particular type, and for Yj 0 there is a predominance of elements of different types (the same number); Y is the decision signal by the same and third and fourth repetition elements, with the elements: the same, and the other elements, Y, the value of the decision result of the first (Y,) and second (Y) type, and for Y 1 in the same the elements are dominated by the information unit Y 0 - all the rest, and some other cases. The switches 4-6 are intended for switching the information inputs of the shift registers 7-9, which are multifunctional elements of the device. When receiving the first three repetitions in registers 7 and 8, the code of the number of received units is entered for each bit of a message, the third repetition is entered in register 9. After receiving four repetitions, the result of processing by code converter 3 is entered in registers 7-9. this five repetitions in register 7 is entered in the result of the majority processing of five repetitions; in the register 8, the result of processing the third, fourth and fifth repetitions. The operation of decision block 10 is defined by the following logical conditions obtained from Table 2: Y, where X is the value of the elements of the fifth repetition. Z is the result of the majority processing of five repetitions. / Z, the result of the majority processing of the last three repetitions. The device operates as follows. The initial state of counter 2 and shift registers 7–9 is zero, key 1 is open, the first inputs of switches 4 and 5 are open. The first repetition through the key 1 enters the input of the counter 2. If the received element 1, then in the first bit 2. of the counter 2 is recorded 1, which through the open switch 4 is recorded in the shift register 7, and the control signal sets the counter 2 to the state Oh, prepared to receive the next item. The unit is rewritten from the first bit to the second shift register 7. When O is received, the state of counter 2 is changed, and O is recorded in register 7. (Only information shifts take place. Thus, after the first repeat is received, it is recorded in shift register 7. State of registers 8 and 9 is zero. When shifted information in register 7 for one bit the first element of the first repetition from the output of register 7 is fed to the setup input of the first bit 2 of counter 2. If this element is 1, then the first bit of counter 2 is set to the same state. also 1 then with The standing of counter 2 changes - the first bit is set to O, and the second bit is set to 1. When reading the states of counter 2, the first bit of register 7 is written O, and the first bit of register 8 is 1. Next, the counter 2 is reset In O, the information in the registers is shifted by one bit and the counter 2 is set to the state corresponding to the second element of the first repetition. With the arrival of the next element of the second repetition, the processing is repeated. At the time of termination of reception of the second repetition, the first input of the switch 6 opens, ensuring the direct recording of the third repetition and register 9. When receiving each element of the third repetition, the state of the first and second bits of the counter 2 can be in one of the following states: 00, 10, 01 11. Information 1 is generated and output to the device in cases when counter 2 is in state 01, 11 (two or three units out of three possible). An information O is formed and output by the device for states 00

and 10 counters 2 (three or two yul out of three).

Consequently, information elements can be directly formed by the state of the second bit of counter 2. By entering the fifth input of the decision block 10, information elements through the OR 30 element are fed to the open second input of the switch 33, from which output is removed for further processing. From the moment the third repetition reception is finished, on switches 4-6, the programmer connects the second inputs and disconnects the first inputs. If the result of the majority processing of two out of three needs to be repeated, then the contents of register 8 enters the decision block 10 at the second input, where the passage through the OR element 28 and the switch 33 is output to the second output of the device.

If at the time of termination of the reception of the third repetition the result of the majority processing does not meet the requirement of correctness of information, then the reception of the fourth repetition continues, which comes through switch 1 to the fourth input of the code converter 3, to the fifth input of which the elements of the third repetition read from register 9 arrive The elements read from registers 7 and B, arriving at the installation inputs of bits 2 and 22 of counter 2, form the code of the number of received units for each message bit with the element, simultaneously coming from the fourth repetition. The code is read from the outputs of the bits of the counter 2 and is fed to the first three inputs of the code converter 3. The output signals y. , Y2., Ultrasonic, formed in accordance with Table 1 and which can be specified by expressions (1) respectively, are recorded in registers 7-9, passage through the second open input of switches 4-6 (first inputs of switches 4-6 at this moment At the end of the reception of the fourth repetition, the registers 7-9 will record the numerical values of the decision on four repetitions. From this moment, the second inputs of switches 4 and 5 and the first input of switch 31 are closed and the third inputs of switches 4 and 5 open, the first input of the switch 28 and second in one switch 31.

If the output signals of shift registers 7–9 Y.YI take the value 101, respectively, then this means that the decision (Xj 1) is taken over the four elements of the same name, this solution is 1 (), and the elements of the third and fourth repetitions do not match, those. the decision on the third and fourth repetitions is not accepted (). in this case, the element Y 25 is given single signals Y 1, YJ 1, which determines the appearance of 1 signal at the element output and 25 and its passage through the element OR 27, switch 32 to the first output of the device and writing to register 7, as a result majority processing of five repetitions (Z).

The value of the like element of the fifth repetition (Xj), which arrives at the fourth input of the decision block 10 on the formation of the result of the majority processing of five repetitions, does not affect. However, since the elements of the same name of the third and fourth repetitions do not coincide (), the result of the majority processing of the third repetition of the last repetitions (Z) is completely determined by the corresponding element of the fifth repetition. Since the prohibition 31 has no signal at the prohibiting input of the element (Y 0), the signal Xj at the fourth input of the decision block 10 through the prohibition element 31, the OR element 29 and the switch 33 passes to the fourth output and is written to the register 8 as a result of majority processing (Z) last three reps.

If the output signals of registers 7-9 are of the form 011, this means that the decision of the same four elements of the repetition is not made (), i.e. there is uncertainty, since two 1 and two O are accepted. In this case, the majority decision by five repetitions (Z) is entirely determined by the value of the corresponding element of the fifth repetition Xtt. Since the prohibition 3.0 signal is absent at the prohibiting input, the Hu signal at the fourth input through the AND 30 element, the OR element 27 and the switch 32 passes to the first output and is written to the register 7 as a result of the majority processing (Z. five repetitions.

At the same time, the signal signals Y, 2 1 and V are fed to the inputs of element And 26, the signal from whose output through element OR 29 and switch 33 passes to the fourth output and is written to register 8 as the majority result of the last three repetitions (Z) from the value of the corresponding element of the fifth repetition (Hu) This is because the elements of the same name of the third and fourth repetitions coincided () and their value corresponds to 1).

If the results of the majority processing (Zjf, t.) Need to be re-issued, the first input of the switch 32 and the first input of the switch 31 are closed and the second input of the switch 27 and the first input of the switch 31 are opened. Result Z from

Register 7 through the switch 27 is fed to the first output of the device. Result Z from register 8 through the element OR 28 and the switch 33 passes to the second output of the device. Table 2 shows all the possible solutions that can be obtained by the decision block 10. The logical elements of the block 10 thus work in the same way as described above.

The proposed device has a higher technical and economic efficiency than the known. The prior art device allows for the first three or only to be majority-processed. five repetitions in general. The proposed device allows additional processing of the third, fourth and fifth repetitions, which increases its reliability. Equivalent error probability for the method of majority processing of five repetitions is equal to .1 „, -

0

where P is the probability of the distortion of a single element.

For a known device with a half-time and three-fold errors in the seven and nine possible cases of error will not be wrong, which leads to loss of information

RI.-P94 where R cc7-Rho /

n is the number of elements in one repetition. In the proposed device

.,. where P -.: 4-P.,

91 o

tTo is achieved by correcting three variants of errors in case of a major o6paf during the last three repetitions. Consequently ,

.

those. information loss is almost halved.

Table 1

table 2

O 1 o

About 1

Oh oh

oh oh

about 1

Claims (3)

Invention Formula A device for receiving and majority decoding information that contains a key, the input of which is connected to the information input of the device, the output to the first input of the counter, the first and second outputs of the counter are connected to the first inputs of the first and second switches, respectively, the third switch, the outputs of the switches are connected to information inputs corresponding to the shift, the outputs of which are connected to the first, second and third inputs of the decision block, the first output of which is connected to the first output of the device1 1 ABOUT one eleven 1 o 1 1 1 1 about 1 1 about 1 1 The first and second shift registers are connected to the second and third inputs of the counter, respectively, characterized in that, in order to increase the reliability of the device, a code converter is entered into it, the first, second and third outputs of the counter are connected respectively to the first, second and third inputs of the code converter whose fourth input is combined with the first input of the third switch and the fourth input of the decision block and is connected to the output of the input key, the first, second and third outputs of the code converter of the connection with the second inputs of the corresponding switches, the output of the third shift register is connected to the fifth input of the code converter, the input of the decision block is connected to the second output of the counter, the second and fourth outputs of the decision block are connected respectively to the third inputs of the first and second switches and the second output of the device . 2. Device POP.1, characterized in that the code converter is made on an adder, AND, OR, and NOT elements, the output of the first element AND is connected to the first input of the first element OR, the output of which is connected to the first inputs of the second and third elements OR , the output of the OR element is NOT connected to the second input of the second element OR, the output of the adder is connected to the parks by the input of the second element AND, the output of which is connected to the second input of the third element OR, the first input of the first element AND is connected to the first input of the code converter, the second input of the first input AND element is combined with the first input of the element OR NOT and is connected to the second input of the code converter, the first input of the adder is combined with the third input of the second element AND and connected to the fourth input of the code converter, the fifth input of which is connected to the second input of the adder, the outputs of the second element OR , the adder and the third element OR are connected respectively with the first, second and third outputs of the code converter. 3. Device POP.1, characterized in that the decision block is made on the switches. Fg / g. / Prohibit elements, AND, OR, the output of the first element AND is connected to the first input of the first OR element, the second input of which is connected to the output of the first prohibition element, the output to the first input of the first switch, the output of the second prohibition element and the output of the second element Both are connected to the first and second inputs of the second OR element, the output of which is connected to the first input of the second switch, the second input of which is connected to the output of the third element NO, the first inputs of the first And element, the first prohibition element and the second input of the first The switches are connected to the first input of the decision block, the first, the inputs of the second prohibition element, the second element AND the third element OR are connected to the second input of the decision block, the second inputs of the first and second elements AND are connected to the third input of the decision block, the second inputs of the prohibition elements and the second input the third element OR are connected respectively to the fourth) and the fifth inputs of the decision block, output; the first switch is connected to the first and second inputs of the decision block, the output of the second switch is connected. with the third and fourth inputs of the decision block. Sources of information taken into account during the examination 1. USSR author's certificate number 767989, cl. H 04 L 1/10, 1978. 2. Author's certificate of the USSR according to application No. 2718711 / 18-09, 1978 (prototype). Fu1.2 0tff.J