SU974575A1

SU974575A1 - Analogue-digital converter

Info

Publication number: SU974575A1
Application number: SU813265132A
Authority: SU
Inventors: Хикмет Гамид Оглы Асадов; Яшар Адиль Оглы Мамедов; Ровшан Гусейн Кули Оглы Гусейнов; Алевтина Анатольевна Ибрагимова; Сергей Витальевич Красильников; Зульфугар Аваз Оглы Азимов
Original assignee: Особое Конструкторское Бюро Научного Центра "Каспий" Ан Азсср
Priority date: 1981-05-04
Filing date: 1981-05-04
Publication date: 1982-11-15

Description

С54; АНАЛОГО-ЦИФРОВОЙ ПРЕОБРАЗОВАТЕЛЬC54; ANALOG-DIGITAL CONVERTER

Изобретение относитс к измерительной технике и может быть применено в информационно-измеритель- ных устройствах.The invention relates to a measuring technique and can be applied in information-measuring devices.

Известно устройство преобразовани аналог-код, работ.ающее по методу последовательных приближений, содержащее буферный усилитель с последовательно соединенным компаратором, другой вход компаратора соединен с преобразователем код-аналог, выход компаратора соединен с логическим устройством-регистром (J1.An analog-to-code conversion device, operating in the method of successive approximations, containing a buffer amplifier with a series-connected comparator, is known, another comparator input is connected to a code-analog converter, the comparator output is connected to a logical register device (J1.

Этому устройству свойственна невысока точность преобразовани вследствие наличи у компаратора порога срабатывани , что также ограничивает разр дность аналого-цифрового преобразовател .This device is characterized by low conversion accuracy due to the presence of a threshold for the comparator, which also limits the size of the analog-to-digital converter.

Наиболее близким по технической сущности к предлагаемому вл етс устройство, содержащее последовательно соединенные буферный усилитель с компаратором, аналоговый сигнал поступает через буфер:2: й усилитель на один из входов компаратора, к другому входу компаратора подключен выход преобразовател код-аналог, входы которого подключены к логическому устройству-синхронному счетчику .сThe closest in technical essence to the present invention is a device containing a series-connected buffer amplifier with a comparator, an analog signal is fed through a buffer: a 2: amplifier to one of the inputs of a comparator; to another input of a comparator, the output of the code-analog converter, whose inputs are connected to logical unit-synchronous counter.

дешифратором, выход компаратора подключен к счетчику. С выходов дешифратора снимают разр дный код f 2 . с Недостатком устройства вл етс невысока точность преобразовани .the decoder, the output of the comparator is connected to the counter. The bits of the decoder are removed from the outputs of the decoder f 2. The disadvantage of the device is the low conversion accuracy.

Цель изобретени - повышение точности устройства.The purpose of the invention is to improve the accuracy of the device.

Поставленна цель достигаетс тем, The goal is achieved by

10 что в устройство, содержащее буферный усилитель, вход которого соединен с шиной входного сигнала, а выход с инвертирующим входом компаратора, выход которого соединен со входом ло15 гического устройства, входы которого соединены со входами преобразовател код-аналог, дополнительно введены ограничитель , сумматор и инвертор,вход которого подключен к шине входного 10 that a device containing a buffer amplifier, whose input is connected to the input signal bus, and an output with an inverting input of a comparator, whose output is connected to the input of a logic device, whose inputs are connected to the code-analogue converter inputs, is additionally introduced a limiter, an adder and an inverter whose input is connected to the input bus

20 сигнала, а выход - к первому входу сумматора, второй вход которого подключен к выходу преобразовател коданалог , при этом выход сумматора через ограничитель соединен с неинвср25 тирующим входом компаратора.20 of the signal, and the output is to the first input of the adder, the second input of which is connected to the output of the coding converter, while the output of the adder is connected to the non-inverting input of the comparator through a limiter.

Claims

FIG. 1 shows a block diagram of the device; FIG. 2 is the time diagram of the device operation, where -t 30 is the instant of operation of the comparator, (Jj, (-b) is the signal to be converted u (, t) -u () (Jhlt is the stepwise pilot signal from the converter code input, analog; fig. 3) graphic interpretation of the increase in accuracy, where (J is the time interval during which the comparator is in an indeterminate state (ii dr. The device contains an inverter 1, a buffer amplifier 2, the input of which receives an analogue analog signal) ((i.). The output of the buffer the amplifier is connected to the inverting input of the comparator 3. NeiIver A comparator input is connected through limiter 4 to the output of adder 5. An inverted angular signal Uct-fc is supplied to one input of the adder. Another input of the adder is connected to the converter code 6. The inputs of the analog converter are connected to the output of the logic device 7. The output of the comparator is connected to the input of the logic device. The device operates as follows: An analog DC signal is fed through the buffer amplifier 2 to the inverter input of the comparator 3 and simultaneously through the inverter 1 to the input of the adder a 5. To the other input of the adder, a stepwise sawtooth signal from the output of the converter is analogue signal 6. In the adder 5, a stepwise sawtooth signal is added to the inverted analog signal Uct-b MHB- The resulting signal) -u, ct) ik.y Limiter 4 is fed to the Hci second comparator input. As soon as the voltages C / c Ct UjC-t) are matched, the comparator generates a control reset signal for the counter of the logic unit 7. The counter stops. At the outputs of logic device 7, the resulting Kf-bit code appears. The accuracy of the conversion is increased by comparing the comparator (JcCt) not with the reference voltage, but with the total voltage, thereby reducing the time interval (2 during which the comparator is in an indeterminate state. This is graphically illustrated in; Fig. 2 and 3-d., c 2 the Invention may be recommended for use in information-measuring devices, measurement complexes, information processing devices. Invention Analog-to-digital converter containing a buffer amplifier e, whose input is connected to the input signal bus, and the output to the inverting input of a comparator, the output of which is connected to the input of a logic device whose outputs are connected to the code-analogue inputs of the converter, characterized in that, in order to improve the accuracy, a limiter is inserted into it, adder and inverter, the input of which is connected to the input signal bus, and the output to the first input of the adder, the second input of which is connected to the output of the code equivalent converter, while the output of the adder is connected to the non-inverter via a terminator the comparator input. Sources of information taken into account in the examination 1. Shilo VL, Linear integrated circuits, 1979, p. 339, fig.8: 23a.

2. In the same place 337, Fig. 8.21.

8e (x.ypoBeHi Dji, OHuu

.ypoepHtt OtpQHUt4