SU972544A1 - Data compression device - Google Patents

Description

(54) DEVICE TO COMPRESS INFORMATION

The invention relates to automation and computing, and is intended to analyze signals in real time, match the signal band with the bandwidth of the analyzing and measuring equipment, etc. A device is known for temporarily compressing signals consisting of several accumulation nodes with a switch and a recirculation delay line. in each node used as a storage unit of the adder, the output of which is the output of the device, the control unit inputs of the memory elements of the level The settings and input of the switch of the first accumulation unit are combined and form the input bus of device 1. However, this device cannot be used to measure the characteristics of periodic signals, since it does not separate the input signal period. The devices do not automatically determine the optimal number of fixed points for one period of the input signal and, therefore, in the First Frequency range, the variation in the approximation error of the input signal may be higher than the allowable one. This narrows the frequency range of the compressible input signals, which is a drawback of the device. It is also known a device for temporarily compressing the input signal containing control units and a memory block made using magnetostrictive: control unit delay lines with analog-code converter outputs, and outputs with the converter code analog t2. The disadvantage of such a device is that it cannot be used to measure the characteristics of periodic signals, since it does not select the period of the input signal. As in other known devices, when a periodic signal is compressed by this device, the approximation error of the input signal varies depending on its frequency range. The closest in technical essence to the proposed is a device for temporal compression of an input signal containing the code, the information input of which is connected to the input of the device, and the output is connected to the information input of the memory block, the output of the next / next is connected to the information input of the code-analog converter r, the output of which is connected to the output of the device, the input of the period determining unit is connected to the input of the device, the first output is connected to the first input of the frequency multiplying block, and the second output is connected to the first input of the addressing block, the output of which is connected to the address input of the memory block, the control input ana converter

the log code is combined with the second input of the addressing unit, the first output of the control unit is connected to the second input of the frequency multiplying unit 31.

The known device can be used to measure the characteristics of periodic signals of the infrasonic range. Frequencies with instruments of the audio frequency range, since it stores the digital signal under study on its period with the subsequent transfer of the spectrum. The device can be used to measure averages, moduli, rms voltage, harmonic coefficient, shape factor, etc.

The disadvantages of the known device include the practical impossibility of its use for carrying out spectral and harmonic analysis of infrasonic signals, since the scale of the spectrum conversion is unknown. The scale of the conversion can be determined by calculating the ratio of the periods of the input and transformed (time-compressed) signals, but its use for these purposes is extremely inconvenient, since its value can take any non-integer values, which makes it necessary to carry out an additional PFD of the control signal generator connected to the second the input of the frequency multiplying unit; the second output of the control signal generator is connected to the first input of the address driver, the second input of which is connected n with the control input of the analog-code converter, output — with the address input of the memory block; frequency dividers, decoders, additional frequency multiplying blocks, first and second groups of AND elements, OR elements and keys, and the second synchronizer output are connected to the control input. control signal generator, the third output of which is connected to the first input of the first key, the output of which is connected to the third input of the address generator and the control

5 code-analogue converter inputs, the first outputs of all frequency multiplying blocks are connected to the first inputs of the corresponding elements of the first and second groups, the second outputs are from

0 by the second inputs of the corresponding elements of the first group, the third output of the frequency multiplying unit is connected to the combined first inputs of all decoders, the third outputs of the additional frequency multiplying blocks are connected to the combined third inputs of the corresponding elements of the first group and the second inputs of the corresponding elements of the computation to identify the results , The purpose of the invention is to expand the field of application of the device due to automatic frequency scaling when converting the signal under study to provide spectral analysis of infrasonic periodic signals by analyzers of the spectrum of the audio frequency range. This goal is achieved by the fact that in an information compression tool containing a synchronizer, the first output of which is connected to the first input of the frequency multiplying unit, an analog-code converter, whose information input is combined with the information input of the control signal generator and the output the analog-code converter is connected to the information input of the memory block, the output of which is connected to the information input of the code-analog converter, the output of which is connected to the output of the device, first output the fourth group, the fourth outputs of all frequency multiplying blocks are connected to the second inputs of the corresponding decoders, the outputs of which are connected to the third inputs of the corresponding elements AND of the second group, the outputs of the elements AND of the first group are connected to the corresponding inputs of the first element OR, the output of which is connected to the first input of the second key, the second input of the second key is connected to the second output of the driver of control signals, the output, to the control input of the analog-code converter and the second input of the driver of data output, The elements of the second group are connected to the corresponding inputs of the OR element, whose output is connected to the second input of the first key, the first output of the synchronizer is connected to the input of the first frequency divider, the output of each frequency divider is connected to the input of the subsequent frequency divider and the first input of the corresponding additional multiplication unit frequencies, the second inputs of which are combined and connected to the first output of the driver of the control signals. Moreover, the frequency multiplying unit contains a pulse shaper, a frequency grid shaper, a decoder, a trigger, a counter and an element I, the output of the frequency grid former is connected to the first input of the decoder, the output of which is connected to the first input of the element I, the output of which through the first counter is connected to the first input the first trigger, the first output of the first trigger is connected to the input of the second trigger, the second output is connected to the input of the pulse former, the first and second outputs of which are connected respectively to the second input of the first trigger the key and the input of the second counter, the output of which is connected to the second input of the decoder, one of the outputs of the second trigger, the output of the decoder, the output of the frequency grid generator, the other output of the second Rigger, the output of the second counter, respectively, the first, second outputs of each frequency multiplying unit the third output of the frequency multiplying block, the third output of the additional frequency multiplying block, the fourth output of each frequency multiplying block, the second input of the And element and the input of the frequency grid former are connected accordingly but with each block of the first and second inputs of the frequency multiplying FIG. 1 shows a functional diagram of the device according to the invention; FIG. 2 shows an example of execution of a frequency multiplying unit. The device for compressing information contains an analog-code converter 1, a memory block 2, a code-analog converter 3, a period determination control signal generator k, N frequency multiplying units, where N is the number of decimal transformation scales, the address generator 6, the synchronizer 7, the N-1 dividers 8., - V.frequency, N decoders, OR elements, keys 11i, TC, two groups of N elements AND 121-12, 13i-13N. The frequency multiplying unit 5 contains a shaper 1 + a frequency grid, a decoder 15, a first counter 16, a trigger 17, a shaper 18 pulses, a second counter 19, a flip-flop 20, and an Element 21. The device operates as follows. steps on converter 1 analogue code and on driver t, at the outputs of the latter after start by synchronizer 7, the resolution signals are generated: on the first output the duration of the first period of the input si (zero; on the second output - on the duration of the second period-, on the third output - on reading information from memory block 2 after the end of the second period and until the next launch of the device ;, Thus, the operation of the proposed device is carried out in three stages. In the first stage (the first period of the input signal), the The start-up frequency of converter 1 is analog-code and the frequency of reading information from memory block 2 and clocking of converter 3 is analog code. The first inputs of frequency multiplying units receive a permission signal for their operation, so that in each frequency multiplying block from the frequency grid generated by the former of the frequency grid 1, selects a frequency that divides one period by a number equal to the number of ordinates and lies within 79 from d to 2 s (. This is done as follows. After the device is started up, the maximum frequency from frequency maker 1 of the frequency grid 1 arrives at counter 21 through element 21 and the decoder 15. After the first overflow of counter 16, Tov. the set of the number ot, the trigger 17 is set to the one state, and after the second overflow, the t-e-set of the number 2oL is set to the zero state. On the last transition, a pulse shaper 18 is triggered, which adds one to the contents of counter 19 and sets trigger 17 to one state. The most convenient implementation is when using a binary frequency grid, in that case the 1 + grid former is simply implemented on a binary counter, the pulse frequency from the neighboring outputs of which are twice as large. In the case of double overflow of the counter 1b, the frequency of the decoder 15 is reduced by half, and the state of the counter 16 and the trigger 17 corresponds to a number equal to ot. Thus, the number 2o1 and the frequency fj are replaced with the number c1 and the frequency f.j4 .-) f i / 2 | moreover, this is about the ISHOD after each double overflow of counter 16, due to which the selection frequency of the converter 1 analog-code is made. To ensure the convenience of spectral analysis using the proposed device, the frequency of converter 1 start is analogous - CODE f, j - and frequency 3 of converter 3 start code-analogue fj should respectively. worn as follows..f / f- 1 About where, 2, ..., n. The formation of the specified frequency grid is carried out using N blocks 5 -) - 5N frequency multiplication and (N-I) frequency dividers, the latter in this case having a division factor. Owing to this, on the neighboring Tt driver, the frequency grids are identical, the frequencies of the Coatna are ten. All frequency multiplying blocks start working simultaneously and the Frequency selection fj and f; performed as follows. After the counter 16 of the first frequency multiplying unit 5 overflows for the first time, the trigger 20 is triggered and includes the corresponding elements AND 12 and 13i 48 of both groups, and since the third inputs of the latter have such an enable signal, through them and through the elements OR 1П, 10 at 11, the frequencies fj i arrive. If the counter 16 of the second block Si multiplying the frequency overflows the first time, the corresponding trigger 20 is triggered and turns on the corresponding elements AND 122) 13 1 of both groups, and the first elements AND 12, 132 of both Groups turn off. Through the second element And 122 of the first group comes the frequency fj, and through the second element And 13 of the second group comes the frequency f :, and their ratio is f; / f; 10. Similar changes occur when the i-ro counter overflows in the i-ro frequency multiplier 5i, and the ratio f | / f; in. The fulfillment of this relation is ensured by the fulfillment of the relation f | i .ipin i (and by the fact that all frequencies f; come only from the first frequency multiplying unit 5, Thus, during the first period of the input signal, the frequencies fl and f | are selected, At the second stage of operation of the device (the second period of the input signal), the frequency multiplication blocks do not work, the address generator 6 and the second input of the second key 11 receive an enable signal from the second output of the shaper 0 With the selected frequency f; start up conversion The transponder 1.anal-code and recording the received selected input signal values into memory block 2. At the end of the second signal period, memory block 2 is filled from ot to 2 (sample values, the second key is closed, and the first key 11 is opened with the enable signal From the third output of the driver, the third stage of the device operation begins - reading information from memory block 2 and its conversion to analog form in converter 3. The frequency f is fed to the clock of the driver 6 and converter 3 code-analogue from the output n The first key 11). Information is read continuously until the next launch of the device. The beginning of the third stage of work means the end of the time (spectral) scale conversion of the input periodic signal. Thus, by introducing new nodes and connections, the temporal (spectral) scale of the signal under investigation is transformed with a factor multiple of K), thereby achieving a qualitatively new effect: the possibility of using such devices for practical spectral (harmonic) analysis of infrasonic periodic signals spectrum analyzers sound frequency range. In addition, the proposed device can be used for similar purposes in correlation analysis, as well as for studying the amplitude-frequency characteristics of various technical devices. In connection with the foregoing, it is possible to state a significant expansion of the field of application of the proposed device. Claim 1, A device for compressing information containing a synchronizer, the first output of which is connected to the first input of the frequency multiplying unit, an analog-code converter, the information input of which is combined with the information input of the control signal generator and connected to the input of the device, the output of the converter -code is connected to the information input of the memory block, the output of which is connected to the information input of the converter code-analogue, the output of which is connected to the output of the device, the first output of the form The control signaling gate is connected to the second input of the frequency multiplying unit, the second loop of the control signal generator is connected to the first input of the address driver, the second input of which is combined with the control input of the analog-code converter, the output - to the address input of the memory block These differences are that, in order to expand the field of application of the device, frequency dividers, decoders, additional frequency multiplying units, the first and second groups of AND elements, OR elements and keys, are introduced into the device, the second output is synchronized is connected to the control by the input of the control signal generator, the third output of which is connected to the first input of the first key, the output of which is connected to the third input of the address generator and control (the input of the code-analog converter, the first outputs of all frequency multiplying blocks are connected to the first the inputs of the corresponding elements of the first and second groups, the second outputs with the second inputs of the corresponding elements AND of the first group, the third output of the frequency multiplying unit is connected to the combined first inputs of all the decoded The ditch, the third outputs of the additional frequency multiplying blocks are connected to the combined third inputs of the corresponding AND elements of the first group and the second inputs of the corresponding AND elements of the second group, the fourth outputs of all frequency multiplying blocks are connected to the second inputs of the corresponding decoders, the outputs of which are connected to the third inputs of the corresponding And second elements the groups, the outputs of the elements And the first group is connected to the corresponding inputs of the first element OR, the output of which is connected to the first input of the watt The second key, the second input of the second key is connected to the second output of the driver of the control signals, the output is connected to the control switch. the analog-code converter input - and the second input of the address generator, the outputs of the elements of the second group are connected to the corresponding inputs of the second OR element, the output of which is connected to the second input of the first key, the first synchronizer output is connected to the input of the first frequency divider, the output of each frequency divider is connected to the input of the subsequent frequency divider and the first input of the corresponding additional frequency multiplying block, the second inputs of which are combined and connected to the first output of the control driver 2o signals The device according to claim 1, characterized in that the frequency multiplying unit contains a pulse shaper, a frequency grid shaper, a decoder, a trigger, a counter, and an element, and the output of the frequency grid shaper is connected to the first input of the decoder, the output of which is connected to the first input of the And element the output of which is connected through the first counter to the first input of the first trigger, the first output of the first trigger is connected to the input of the second trigger, the second output is connected to the input of the pulse former, the first and second outputs of which are connected to one of the outputs of the second trigger, the output of the decoder, the output of the frequency grid generator, another output of the second trigger, the output of the second estimator is connected respectively to the first, second outputs of each block frequency multiplication, the third output of the frequency multiplying block, the third output of the additional frequency multiplying block, the fourth output of each frequency multiplying block, the second input of the And element and the input form frequency grid l are respectively connected to first and second inputs of multiplying each frequency block

Sources of information taken into account in the examination

1, USSR author's certificate W 617827, cl „H PZ K 5/159, 1979.

2 "USSR Copyright Certificate No., Clo G 05 J 1/02, 1965s

3. USSR author's certificate in application number 2898832 / 18-2, class, G 08 C 19/00, 1980 (prototype).

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Claims (3)

Claim 1. A device for compressing information containing a synchronizer, the first output of which is connected to the first input of the frequency multiplier, an analog-to-code converter, the information input of which is combined with the information input of the control signal generator and connected to the device input, the output of the analog-code converter is connected to the information the input of the memory block, the output of which is connected to the information input of the code-analog converter, the output of which is connected to the output of the device, the first output of the control signal generator the signal is connected to the second input of the frequency multiplier, the second output of the control signal generator is connected to the first input of the address generator, the second input of which is connected to the control input of the analog-code converter, the output is connected to the address input of the memory block, which differs in that, in order to expand application areas of the device, frequency dividers, decoders, additional frequency multiplication blocks, the first and second groups of AND elements, OR elements and keys are introduced into it, the second synchronizer output is connected to the control input control signal generator, the third output of which is connected to the first input of the first key, the output of which is connected to the third input of the address generator and the control input of the code-analog converter, the first outputs of all frequency multiplication units are connected to the first inputs of the corresponding elements of the first and second groups, the second outputs - with the second inputs of the corresponding elements of the first group, the third output of the frequency multiplication unit is connected to the combined first inputs of all decoders, the third outputs are an additional of frequency multiplication blocks are connected to the combined third inputs of the corresponding elements of the first group and second inputs of the corresponding elements of the second group, the fourth outputs of all frequency multiplication blocks are connected to the second inputs of the corresponding decoders, the outputs of which are connected to the third inputs of the corresponding elements of the second group, the outputs of the elements And the first group is connected to the corresponding inputs of the first OR element, the output of which is connected to the first input of the second key, the second input of the second to yucha is connected to the second output of the driver of the control signals, the output is connected to the control input of the converter, an analog-code -and the second input of the address generator, the outputs of the AND elements of the second group are connected to the corresponding inputs of the second OR element, the output of which is connected to the second input of the first key, the first output synchronizer is connected to the input of the first frequency divider, the output of each frequency divider is connected to the input of the subsequent frequency divider and the first input of the corresponding additional frequency multiplication unit, sec e inputs of which are combined and connected to the first output driver control signals " 2 "Device according to π" 1, characterized in that the frequency multiplication unit comprises a pulse shaper, a frequency shaper, a decoder, a trigger, a counter and an I element, the output of the frequency shaper is connected to the first input of the decoder, the output of which is connected to the first input of the And element whose output through the first counter is connected to the first input of the first trigger11 9> RA _(the first output of the first trigger is connected to the input of the second trigger, the second output is to the input of the pulse shaper, the first and second outputs of which are connected respectively to the second input of the first trigger and the input of the second counter, the output of which is connected to the second input of the decoder, one of the outputs of the second trigger , the output of the decoder, the output of the frequency shaper, the other output of the second trigger, the output of the second counter is connected respectively to the first, second outputs of each frequency multiplication block, the third output of the block is multiplied frequency C 12 the fifth output of the additional frequency multiplication unit, the fourth output of each frequency multiplication unit, the second input of the element And and the input of the shaper 5 frequency grids are connected respectively to the first and second inputs of each frequency multiplication block.