SU968815A1 - Device for control in microdiagnosis - Google Patents

Description

one

The invention relates to computer technology and can be used to control and diagnose microprogram computers.

A device for controlling and diagnosing a firmware microprocessor-controlled digital computer 5 is known, which contains a memory block, a command register, a clock counter, a program register, and a G11-encoder.

Its disadvantages are low efficiency as well as narrow functionality.

Known are also firmware microcontrollers for control and diagnostics of digital computers containing a memory block, a program register, a command register, a start-stop node, a clock generator, a c4 tactics command, an clock counter, an encoder, a mode trigger, and elements

The disadvantage of these devices is low economy, speed and functional reliability.

The most (closer to the proposed technical essence and the achieved positive effect is the control and microdiagnostics device containing the command register, command counter, code converter, trigger mode: pulse generator, start-stop node, clock counter, program register, two address registers , three memory blocks, a block of OR elements, an AND-OR element, seven AND elements and two inverters, the first group of outputs of the command register is connected to the first group of information inputs of the program register and the transform code bodies, the output of which is connected to a single mode trigger input and to the first input of the clock counter set to zero, the second input of the zero setting of which is connected to the zero input of the mode trigger, to the second group of information inputs of the program register, to the first inputs of the first zero input and the second address registers and the output of the first element And, the first input of which is connected to the output of the start-up node and to the first input of the second element And, the output of which is connected to the counting input of the clock counter, and through the third element NT And - with the read input of the first memory block, the group of outputs of which is connected to the first group of outputs of the device through the first inputs of the block of OR elements; the output of the program register is connected to the address input of the second memory block, the first input of which is connected to the inputs of setting the program register to zero, the command register, to the second input of setting the address register to zero, to the third input of setting the clock counter to zero and to the counter input of the counter the commands whose output is the second outputs of the device, the group of installation inputs of the command counter connected to the second group of outputs of the command register, a third of the groups of outputs of which is the third output of the device, and the group of informs tional instruction register input is a first input device; The second 6B1 input of the second memory block is connected via the fourth element I to the synchronizing input of the code converter, the second input of the fourth element I connected to the zero output of the mode trigger, the unit output of which through the fifth element I is connected to the second inverter , the output of which is connected to the second input of the second element AND, and the single output of the mode trigger is also connected to the first input of the first group of inputs of the AND-OR element and to the input of the second inverter whose output is It is connected to the first input of the second group of inputs of the ORI element, the second input of the fifth element I is connected to the single output of the first overflow trigger of the taker counter and to the first input of the sixth element AND whose output is the fourth output of the device, and the second input of this element is connected to the single output the second overflow trigger of the clock counter, the zero output of the first overflow trigger of the clock counter is connected to the fifth output of the device via the seventh And element, the second input of which is connected to the third group The information inputs of the program register and with the third output of the second memory block, the output group of which is connected to the second inputs of the OR block, the output of the pulse generator is connected to the first input of the start-up node, the second input of which is the second input of the device i EXIT with the address input of the third memory block, the output group of which is connected to the first group of information inputs of the first address register, the first group of outputs of which is connected to the address input of the first block memory, and the second group of outputs of the register is connected with the first group of information inputs of the second register of the address. The disadvantage of this device is low reliability of operation and low speed.  The low reliability of the operation of the device is due to the lack of monitoring of the read mic5 commands.  In the operating mode, the device controls the execution of the usual computing commands of the computer by the working microprograms, which consist of the working microcommands recorded in the second; memory block.  In this case, each microinstruction has an address field in which the address of the next microcommand is specified.  Simultaneously with the execution of the working firmware, the monitoring of the lower and upper limits of its execution time is carried out.  .  In the diagnostic mode, the device controls the diagnostics of the control object.  The diagnostic firmware includes special diagnostic microcommands that are recorded in the first memory block, as well as some working microcommands, and the order of the latter in the diagnostic and working microprogram may differ from their order in the working microprogram.  The third block of memory is used to assign the address sequence of the work and special microcommands in the diagnostic firmware.  From it, simultaneously with reading the microcommand from the first and second memory blocks, an address microcommand is read, which specifies the address of the next working or special microcommand.  In diagnostics mode, the address information read from the second memory block is blocked.  The low speed of the device is due to the fact that the length of the diagnostic procedure in the device is set before it starts and does not change depending on the results of the diagnosis, while unconditional diagnosis makes it possible to reduce the average number of tests and, consequently, the time of diagnosis, due to implementation of the unconditional sequential diagnostic algorithm.  The aim of the invention is to increase the reliability of the operation and speed of the device.  The goal is achieved by the fact that the control and microdiagnostics device, which contains the command register, the program register, the first and second address registers, the command counter and the clock counter, the add-on code converter, the first, second and third memory blocks, mode triggers, pulse generator, the start-stop unit, the first switch, the first and WTO elements NOT, the first, second, third, fourth, fifth, sixth, seventh AND elements and the block of OR elements, with the input of the device commands connected to the information input of the command register The output of the initial address of the micro command of which is connected to the information input of the command counter, the output of the operation code of the command register is connected to the first information input of the program register and the information input of the add-on code converter, the control output of which is connected to. the first setting input of the clock counter and the single input of the trigger RB, the single output of which is connected to the first control, and through the first element NOT to the second control input of the first switch and the first input of the first element I, the zero output of the mode trigger is connected to the first input the second element And, the output of which is connected to the control input. the converter of addition codes, the first unit overflow output of the clock counter is connected to the first input of the third I element, the output of which is the first fault output of the device, the second single overflow output of the counter current meter is connected to the second inputs of the third and first I elements, the output of which is connected to the first the input of the fourth element is And, and through the second element is NOT - with the first input of the fifth element And, the output.  which is connected to the counting input of the clock counter, the zero output of the overflow clock counter is connected to the first input of the sixth And element, the output of which. is the second output fault of the device, the start-up input of the device and the output of the clock pulse generator are connected respectively to the first and second inputs of the start-up unit, the output of which is connected to the second inputs of the fourth and fifth elements And, the output of the fourth element And is connected to the zero input of the mode trigger , the second installation input of the clock counter and the first installation inputs of the program register of the first and second address registers, the output of which is connected to the address inputs of the first memory block, the output of the first the memory unit is connected to the first information input of the first address register, the first address output of which is connected to the first information input of the address register, the control output of the first address register is connected to the first input of the seventh And element, the output of which is connected to the control input of the second memory block, The second address output of the first register of the address is connected to the address input of the second memory block, the outputs of which are connected to the first inputs of the block of OR elements, the output of the micro-operator of the third memory block is connected with the second inputs of the OR block, the output of which is the output of the device microoperations, the output of the register of programs is connected to. the address inputs of the third memory block, the first control output of which is connected to the second input of the sixth And element and the second installation input of the program register, the second and third control outputs of the third memory block are connected respectively to the second input of the second And element and the second installation input of the first register addresses, the third installation input of the program register, the third installation input of the clock counter, the installation input of the command register and the counter input of the command counter, the output of which is the output The device addresses, the output of the second address register is connected to the address input of the first memory block, a test register, a correction block, a second switch, a block of AND elements, an eighth AND element, an OR element, a delay element, a modem adder) two are entered, the device input is connected to the information input of the correction unit, the output of which is connected to the single installation input of the clock counter, the information output of the addition code converter and the output of the addition field of the command register are connected respectively to the first and second information inputs of the second switch, the output of which is connected with the information counter cycles.  The second control output of the third memory block is connected to the first test input of the test register. the first input of the block of elements And through the delay element — with the first control inputs of the second switch; the single output of the mode trigger is connected to the second control input of the second switch, the first control input of the correction, the input of the first element, the first input of the modulo two and the inverse the input of the third element And the output of the fourth element And is connected to the second installation. the input of the test register, the output of which is connected to the second information input of the correction unit, the output of the first element AND is connected to the control input of the first memory block, the second control input of the correction unit, the second input of the seventh And element, and the forward input of the eighth element And, output which is connected to the control input of the third memory block, the control, the second and third address outputs of the first address register are connected respectively to the inverse input of the eighth And element, the second information input of the program register and the second input of the modulo-two adder, the output of which is connected to the second information input of the second address register, the third control output of the third memory block is connected to the second setting input second, the address register, the output address of the microcommand initial address of the command register is connected to the second entrance of the block of elements. And, the output of which is connected to the second information input of the first address register, the outputs of the second memory block are connected to the inputs of the OR elements, the outputs of which are connected to the first information input of the first switch, the control output of the second memory block label is connected to the second information input of the first switch , the output of which is connected to the third input of the starting block; Stop, the output of the block of elements OR is connected to the information input re-.  gistra test ,.  In addition, the correction node contains the first and second registers, the decoder, the first and second delay elements, modulo two, the AND element, the OR element, and the first and second control inputs of the block are connected respectively to the first input of the AND element and the input of the first delay element whose output is connected to the synchronization inputs of the first and second registers and through the second delay element to the second input of the element I, the output of the second element I is connected to the control input of the decoder, the output of which is connected to the inputs of the elec OR, the output of the element OR is the output of the block, the first information input. unit is connected to the information input of the first register and the first input of the adder modulo two, the output of which is connected to the information inputs of the second register, the second information input of the block and the output of the first register are connected respectively to the first and second information inputs of the decoder, the output of the second register is connected to the third information the input of the decoder and the second input of the modulo two.  The invention provides improved performance and reliability of the device.  The increase in speed is achieved by providing the ability to control the length of the conditional diagnostic procedure by implementing an unconditional sequential diagnostic algorithm.  Improving the reliability of the operation of the device is achieved by monitoring the compliance of readable micro-commands to the mode of operation.  The introduction of the indicated elements and connections allows one to control the correspondence of the readable microinstructions to the mode of operation of the device, to form the working and diagnostic microprograms upon a single record of the addresses of the working microinstructions, and also to control the length of the microdiagnostic procedure.  This increases the reliability of the operation and the speed of the device.  FIG.  1 shows a functional diagram of the proposed y-device, 9 96 in FIG. 2, a functional diagram of the start-stop unit; in fig.  3 is a functional diagram of the converter code additions; in fig, k is a functional diagram of the correction unit; in fig.  5 formats of commands given to the input of the device; FIG.  6 shows the formats of micro-instructions generated by the device; FIG. 7 is an example of a microdiagnostics algorithm scheme implemented. device; FIG. 8 is an example of a truth table implemented by a code converter; FIG. 9 is an example of a table of permitted sets of a descrambler node OR correction node; Fig. 10 is an example of a correspondence table describing the operation of the addition code converter 5 (Fig. 3).  The device (FIG. 1) contains the command register 1 with the operation field 2, the addition field 3 and the initial microcommand address field k, the addition code converter 5, mode 6 trigger, second element 7, delay element 8, test 9 register second switch 10, correction node 11, counter 12 clock cycles with the first 13 and second 14 triple overflow gels, first 15, third 16 and sixth 17 elements AND, register programs 18, third memory block 19, first inverter 20, element OR 21, first the switch 22, the command counter 23, the pulse generator 2, the node start-stop 25, the fourth element And 2b, second inverter 27, fifth element 28 and 28, second address register 29, first memory block 30, AND 31 block of elements first address register 32 with first address 33 third address field 3, second address field 35 and control field ZB the seventh 37th and eighth 38 elements AND, a block of modulo two 39, the second memory block O and the first block of elements OR C.  Symbol 42 in FIG.  1 designates the information input of the commands, the control input 43 of the code converter, the information input C of the code converter, the control output kS of the code converter, the information output 46 of the code converter, unit output 47 of the mode 6 trigger, the first information output 4§ of the device, test output 49 9, third output 50, field 4 of instruction register 1, device address output 51, pulse generator output 2h, device start input S3, third start-up node input 54, output And 26 element, output 510 correction node 5b, respectively first and second outputs 57 58 malfunctions, respectively, the first, second, third and fourth control outputs of the third memory unit 19, micro group 63 outputs the block memory 19, the output 64 of the first switch, the output b5 micro device.  A start / stop unit (FIG.  2) contains the trigger 66 and the element And 67.  The symbol 68 in FIG. 2 denotes the output of the start-up block.  The code converter (FIG. 3) contains a decoder 69 with a control input 43 and information input 44, an encoder 70 having (n + 1) outputs, the first of which form a separate group.  Symbol 71 in FIG.  3 denotes the outputs of the decoder, K-width field of operation code 2 of instruction register 1, is the bit number of the first overflow trigger 13 of the clock counter 12.  Node correction (Fig: 4) contains the first delay element 72, the block of modulo two 73, the first 74 and 75 second registers, the second. the delay element 76, the element And 77, the decoder 78 and the element OR 79.  Symbols 80 and 81 in FIG. 4 denote groups of outputs of the first and second registers, respectively, 5b — output of the correction unit, t-size of test sets formed by the device, g-size of output control and diagnostics responses.  In FIG. 5, symbol 82 denotes an operation code field, 83 an addition field, 84 an initial microcommand address field, A and A, (j.  - addresses of initial microinstructions, respectively, of the working and diagnostic i-th microprogram, Pr and condition codes, respectively, of the working and diagnostic i-th microprogram, Н „- code of addition of the length of the i-th diagnostic microprogram to the capacity () of the clock counter 12, n - bit number the first overflow trigger 13 clock counter, K0j, p4 and - the opcode of the working and diagnostic i-th program, respectively.  In FIG. 6, symbols U59, UO.  Ub1 Ub2 are marked respectively 59, 60, 61, 62 outputs of the third memory block 19, UBZ output of micro-operations, MO code of micro-operations; symbols 1 and О denote the presence of a single and zero signal, respectively, at the output of the memory briOKa, the symbol l.  means that in this category there can be both O and 1, depending on whether or not a microinstruction is included in the diagnostic firmware.  FIG.  7 symbols TV, T2, TZ, T T5 denote the first, second, third, fourth and fifth test sets, respectively, fed to the inputs of the control object and the diagnostics, the R-output reactions of the object to the supplied test sets, and the index with the symbol R corresponds to the reaction number , С - object states characterizing the type. and the place of failure in it, with the index at C.  corresponds to the state number, the result of adding modulo two of all previously obtained reactions of the object with the next filed.   FIG.  8, the symbols K and D designate working and diagnostic commands, respectively, the index for which corresponds to the command number, N is the firmware length, HQ, is the addition code of the number N to the capacity () of the clock counter 12: But (/ -1) -N, n - the bit number of the first overflow trigger 13 of the clock counter, X kk is the operation code, ykS is the signal at output 45 of the addition code converter, the signal at output 46 of the code converter, a dash at the intersection of the row and column indicates the absence of the corresponding information in the command format. .  9 symbol T marked.  test sets supplied to the input of the control object and the diagnostic index at. T corresponds to the dialing number, X + 9 is the test, dialing code supplied from input E to the second group of information inputs of the decoder 78 of the correction node 11, XZO is the code fed to the first group of information inputs of the X81 decoder code to the third group 81 information inputs of the decoder 78, C is the state of the control and diagnostics object (as shown in FIG.  7) corresponding to the moment of excitation of the output U5b of the correction unit 11.  Consider the purpose of the elements of the device (FIG.  one).  Command register 1 is for xp. change the code of the command being executed.  In any mode, field QO is located in field 2, and in field 4, the address A1 of the initial microcommand of the firmware being implemented.  In field 3, in the operating mode, it places the code Pr of the conditions that are checked in the object (for example, in the computer's operating unit) programmatically and determine the course of the program execution depending on the current results of the calculations.  In the diagnostics mode, this field also contains the code H, the addition of the number (N) of the diagnostic firmware cycles to the capacity of the cycle counter 12.  The formats of these commands are shown in FIG.  5Input B1 of instruction register 1 is designed to set the register to zero, input 42 is for recording information into the register.  The converter of 5 additional codes in the working mode converts the operation code to the HQ code.  additions.  This code is fed to output 46 and corresponds to the minimum possible length of the firmware for executing the command given by the operation code.  At the output 45, a zero signal is generated.  In diagnostic mode, a 5 code converter converts the diagnostic command operation code into a code containing a one in the bit corresponding to output 45, and zeros in all bits corresponding to the output 46 of the converter of 5 padding codes.  The issuance of codes to the outputs of the converter 5 codes is carried out when the enable signal is applied to its control input 43.  The trigger 6 mode is designed to fix the mode of the device.  The operating mode corresponds to the zero state of the trigger, and the diagnostic mode corresponds to one.  Element And 7 is designed to control the input signal to the input of the converter 5 codes.  /.   .  Delay element 8 is designed to delay the signal, allowing the addition of the Ng code to be written.  into the clock counter 12, at the response time of the element 7 and the code converter 5.  It can be performed, for example, on D-triggers.  The test register 9 is intended for storing a test applied to a control and diagnostics object.  The second switch 10 is intended to control the writing of the addition code to the clock counter 12.  Correction unit 11 is designed to form a signal for setting all bits of clock counter 112 into a single state at the moment it appears on

1396

the output of the control object and the diagnosis of such a response to the supplied test set, which allows the required failure to unambiguously determine the location of the failure in the object. This signal stops the diagnosis of the object. The location of a failure in an object can be determined, for example, by the operator using diagnostic tables, which are usually part of the operating and technical documentation of the computer, or the computer itself by software. The source data for this search is the number of the last test set submitted, the code of the last response received and the modulo sum of two object responses to all previous sets with the object response to the last test set.

The clock counter 12 is designed to count the number of micro-commands generated by the device and the implementation of: in the operating mode — checks the time (Tp) of the microprogram execution in the interval between its lower (T) and upper

/ t-lgpi

 by boundaries

mw P vrtdx and in diagnostic mode - control

the duration of the diagnostic procedure.

If this ratio is maintained in the operating mode, by the time the microprogram implementation ends, the overflow trigger 13 should be set to one, and the overflow trigger should remain at zero. .

If a microcommand is omitted, the left side of the reduced inequality is violated. At the same time, by the end of the firmware, the three | - heres 13 and AND will remain at zero.

If, as a result of failures or failures, extra microcommands are formed, the rights of 4acTb inequality are violated. This will be fixed by the single state of the 13 and AND triggers. Element I 15 is intended to form a signal for termination of the microdiagnostics process, as soon as the number of processed cycles has reached - there is no predetermined.

Element I 16 is intended to form a device failure signal in the event of violation of the relation Tr5 .., i.e. when the number of microprogram execution cycles exceeds the maximum possible for the firmware being implemented.

Element I 17 is intended to form a device failure signal in violation of the ratio T7 / addresses of working microcommands read from memory 19.

The memory unit 19 is intended for storing and dispensing operating parts of the working microcommands. The formats of microinstructions written in the block are shown in FIG. 6. At output 59, when reading the final microcommand of the working microprogram, an operation end signal is given, output 60 is signaled when the initial phase of the working and diagnostic microprograms is executed, output signal 61 is supplied when the final microcommand of the working and diagnostic microprograms is executed, output 62 is a signal It is fed into one of the diagnostic firmware and can only be executed in the operating mode. Signals of micro-operations, which are fed to the inputs of the control and diagnostics object, are output to output 63.

Inverter 20 is designed to form a control signal by the first switch 22. The OR element 21 is designed to detect the fact that a microcommand has been read from the central storage unit.

The first switch 22 is designed to check the conformity of the type of micro-instructions read from the memory blocks 19 and the operation mode of the device and form a signal at output 65 to prohibit the operation of the device if this correspondence is violated.

The command counter 23 is intended to form and issue an output to the 51 output of the command via the signals from the output 61 of the memory unit 19 depending on the address specified in the field A of the instruction register 1.

The pulse generator is designed to generate read pulses.

The start-stop unit 25 is designed to control the supply of pulses from the generator in the presence of a single enabling signal at input 53 and a zero signal at input 5.

Element And 26 is designed to control the transition of the device to the operating mode upon completion of the implementation of the firmware diagnostics. . Elements 27 and 28 are designed to control the delivery of read pulses to the counting input of a clock counter 12 and a memory block 19, 30 and kO. Address register 29 is designed to store addresses of address micro-instructions read from memory 30. Block I 31 is designed to control the writing of addresses of initial micro-commands to address register 32. Address register 32 is used to store address micro-commands read from memory 30. field 3 is set to the variable part of the own address field of the next address microcommand, in field 33 - the constant part of this address. In field 3, the address of the working or special microcommand to be read from memory blocks 19 and 36, respectively, is specified. In field 36, a micro-command type label is specified, the presence of which indicates that the field 35 contains the address of a special micro command. The absence of the label corresponds to the address of the working microcode 1y. Elements 37. And 38 control the supply of read pulses to the control inputs of memory blocks 40 and 19, respectively. The block of modulo-two adders is intended to modify the variable part of the address of address micro-instructions in the diagnostic mode. In the operating mode, the bits of the variable part of the address arrive at the output of the adder unit without changes, since its control input is supplied with a zero signal from the unit output of mode 6 trigger. The memory block 0 is designed to store the operating parts of special microcommands. The block of elements OR tl is designed to feed the operating parts of the workers and special microcommands to the output b5 of the device. The trigger 66 of the start-stop unit is pre-assigned to memorize the release signals and prohibit device operation at the inputs 53 and 5, respectively. Element Ib7 is designed to control the supply of pulses from the output 52 of the pulse generator to the output 68 of the node. The decoder 69 of the code converter 5 is designed to decipher the Operational Bit Code and excite the corresponding output bus 71 when there is a permission signal on the control input. The encoder 70 converts the supplied encoder ( a) unitary code into a (n + 1) bit code, in which the first bits specify the code Htv of the addition of the length N of the microprogram, and the (n + 1) code bit sets the trigger state 6 of the mode. The logic of the operation of the 5 code- converter can be explained by the example of the truth table shown in FIG. 8. In this example,. Correction node register 74 74 is intended to store the response of the control object and the diagnosis to the next test set. Register 75 is intended to store the result of a digitally modulo-summed two object responses to the last test set and all sets that preceded it. A modulo-two adder 73 performs a bitwise summation of the object's reactions to the next test set with a bitwise modulo-two object's reactions to all previous test sets. The delay element 72 is designed to delay the read-in pulse of micro-instructions, which is fed through the input 43 of the NOD to the inputs of the registers Ik and 75, for the time required to normalize the response of the object to the fed-in test set. The delay element 76 is designed to delay the sync pulse by the time required to set the response code to the register 75. Element And 77 is designed to control the supply of an enable signal to the control input of the decoder 78. The decoder 78 is designed to generate a signal on one of the outputs at the time of such a reaction of an object to the filed test set, which allows to unambiguously determine the place of failure in the object (i.e., determine its state (Fig. 7)). The element OR 79 generates a signal at the output 5b of the correction unit, when a single signal is generated at any of the outputs of the decoder 78. The logic of the decoder 78 can be explained by the example of the device implementation of the diagnostic algorithm, which is shown in FIG. this example. The task of the decoder in this case is to detect the moment it enters the C1-C7 state and generate a signal to stop this process, without waiting for all the test sets included in the diagnostic algorithm to be applied to the object. Due to this, a reduction in the execution time of the algorithm 1796 of diagnostics will be achieved, and consequently, an increase in the speed of the device will be ensured. Since each specified state is uniquely associated with a certain combination of test set code, the object’s response to this set and modulo two of this reaction with all previous reactions, the outputs of the decoder 78 should be excited only when these combinations of signals appear at its outputs. This is shown in the corresponding FIG. 7 of the table of allowed node sets, the decoder 78 is the OR element shown in FIG. 9 and corresponding to the algorithm in FIG. 7The delay elements 72 and 76 can be performed, for example, on D-triggers. Consider the operation of the device. It is possible in the diagnostic and operating modes. Independently of the mercury mode, before starting up the device, all its memory elements are set to zero. The command code is then written to command register 1. The work command has the format shown in FIG. 5a, diagnostic in fig. 56. From field 2 of register 1 to the information input of the register of programs 18, an operation code is entered, which sets the address of the microcommand on the register, which is called the initial phase of the microprogram. Any diagnostic and operational firmware starts there. Further, when a permitting signal is applied to the device 53 input, a read pulse from the 2k generator passes through the start-stop unit 25 and the AND element 28 to the read input of the memory block 30. Since the zero code is set in register 29, the output state of the block memory 30 at. it will remain zero. Through the element | And 38 the pulse also enters the input input of the memory block 19 and reads from it the initial phase of the microprogram. In this case, a single signal is fed to the output 60 of the block, through which the open signal And 7 gives the enabling signal to the input 3 of the code converter 5 and sets the test register 9 to zero. If the code supplied to the group of information inputs 44 of the code converter 5 sets the diagnostic firmware, then the signals on its line of outputs 46 will remain zero, and 18 the signal at output 45 will become single and set the mode trigger 6 to one state, fixing the device to go into diagnostic mode. After the converter 5 has triggered, the signal from the output 60 of the memory block 19 through the delay element 8 opens the inputs of the second switch 10, as a result of which the addition code H of length N of the diagnostic firmware to the capacitance () of the clock counter 12 sec floor 3 of the register 1 is fed to the clock counter input 12 and recorded in it. The same signal from the output 60 of the memory block 19 opens the block of elements AND 31, as a result of which, from floor 4, the address register 32 receives the address of the first address micro-command and the address of the first micro-command of the diagnostic firmware. The address of the first address microcommand from fields 33 and 34 goes to the register of address 29, while the variable part of the address from field 34 is modified by a block of modulo-39 adders, the control input of which is supplied with a single signal from the unit output of trigger 6 of the mode. The address of the first micro-command of the diagnostic microprogram from field 35 is fed to memory 40, and through register 18 to memory 19. In this case, signal 37 and 38 opens the signal from field B 3 (microcommand type label), preparing the path for the reading pulse . If in the field 35 the address of the working microcommand is written, then the label in the field 36 is absent, as a result, the element 38 will be open, which feeds the next read pulse to the memory block 19 If the address of the special microcommand is written in field 35, the field 36 will be written the element 38 will be closed and the element 37 will open, through which the next read pulse is fed to the memory block 40. The signals of the micro ops of the readable diagonal | microcommand through the block of elements OR 41 arrive at the output 65 of the device. With the same pulse, a unit is added to the clock counter 12, and the first address microcommand is read from memory 30, which is written to register 31. From the fields 33 and 34 of the register, the address of the next address microcommand, similar to the above, is sent to fields 29 and 34 of the register. The address of the next diagnostic / microcommand from the floor 35 of the register 32 enters the kO memory blocks and 19At the same time, the same read pulse arrives at the counting input of the clock counter 12 and adds one to it. On the next clock pulse, the device works in the same way as when reading the first microcommand,

issuing microoperations to diagnostic 10 presses, the intermicroprogram for output 65 is monitored with the simultaneous mode of operation and the type of working microchip counting by counter 12. When reading the final microcommand of the diagnostic microprogram, the first overflow trigger 13 is set to one and opens the element And 15 with a single signal from which through inverter 27, element 28 is closed, prohibiting the supply of read pulses to memory blocks 19, 30, 3b. In addition, by opening element 26, through which the next pulse from the output of the start-stop node 25 sets to zero the registers 29, 32 ,, the clock counter 12, the test register 9 and the mode trigger 6. In the program register 18, the address of the final one will be set. microinstructions that terminates any diagnostic and operational firmware. Since in this case the trigger 6 of the mode is set to zero, the element 15 is again closed by opening the inverter 27 element I 28. Through this element, the next read pulse of the start-up node. A 25 enters the control input of the memory block 19, read from it is the final firmware which excites the output of block b1. The signal from this output adds unit 8, the command counter 23, and the command register 1, the clock counter 12, the address registers 29, 32, and the program register 18 are set to zero. From the output 63 of the memory block 19 to the output b5 of the device, a signal is sent to allow the next sample commands from the main memory of the computer and writing it to the command register 1. In the diagnostic mode, the device controls the length of the microdiagnostic procedure by implementing a sequential unconditional diagnostic algorithm. At the time of the appearance at the object's output, such a reaction to the supplied test set, which allows for one-hour determination of the place of failure in the object, by a signal from output 5b of the correction node 11

all clock trigger triggers are set to one. In this case, the output of the element 15 is excited. Similarly to the above, the execution of the diagnostic firmware stops, without waiting for the delivery of all test sets provided by this firmware to the facility.

Claims (3)

1. USSR author's certificate W 503239, cl. G 06 F 9/06, 1976. 2. USSR author's certificate № «БЁЁО, cl. G About F 9/06, 197. 3. USSR author's certificate №, cl. G 06 F 9/06, 1980. . USSR Author's Certificate No. 7910t, cl. G About F 9/06, 1980. (prototype). FIG. 2 FIG. (rig 4 5) Mgi command diagnostic format 5 FIG. 6 ton UNAH I SO SO L. L || // // 1 (, OP1 Is-OPO 7 Fig.c "Vj