SU963131A1 - Sampler and storage device - Google Patents

Description

(54) DEVICE AND STORAGE DEVICE

The invention relates to measurement technology and can be used, in particular, in information conversion devices. A sampling and storage device containing a switched differential stage, current switches, current generators, and a source follower 1 is known. However, the known device does not have high accuracy and a sufficiently long storage time. The closest to the present invention is a sampling and storage device containing a differential amplifier, the first transistor battery of which is connected to the input voltage bus, the base of the second transistor is connected to the output bus, and the emitters are connected to the first current source connected to power source: not the power source, the base of the transistor of the current switch is connected to the buses of the control source of the other voltage, the field-effect transistor, the gate of which will accumulate flax capacitor is connected to an earth bus, the drain - with a positive power supply bus, the second current generator, one vgaodom connected to the negative bus of the power supply, resistors and the first transistor having its collector connected to a positive power supply bus 12. The disadvantage is that this device is not very fast. The purpose of the invention is to increase speed. This goal is achieved by the fact that a sampling and storage device containing a differential amplifier, the base of the first transistor of which is connected to the input source voltage source, the base of the second transistor is connected to the output bus, and the emitters are connected to the first current transistor. connected to the negative bus of the power supply source, the base of the transistors of the current switch is connected to the voltage source of the control voltage, the field transistor, the gate of which is connected to the ground bus through a storage capacitor, the drain is connected to a full bus power supply, the second current generator, one output connected Two additional transistors are added to the negative power supply busbar, resistors and the first transistor whose collector is connected to the positive power supply busbars in two transistors, the transistor from the current plug ti is a level transformer in the form of a Zener diode, the output bus is connected to the base of the first transistor, the emitter of which is connected to the collector of the second transistor of the current switch, the transistor rod is connected to the bases of the buffer cascade transistors - with the output bus, the collector of the first transistor of the buffer stage is connected to the input bus of the transistor current reflector connected to the positive power supply bus, the output bus of the transistor A current reflector is connected to the collector of the second transistor of the buffer cascade and to the gate of the proportional transistor; the emitter of the first transistor of the buffer cascade is connected to the collector of the first transistor through the first resistor of the first transistor of the differential amplifier and the Emitter of the first additional transistor. differential amplifier, the emitter of the second transistor of the buffer cascade is connected via the second and the resistor with the colliector of the second transistor of the differential usi Ithel and the emitter of the second transistor zyugo supplement, which soodtshepa base to the collector of the second transistor amplifier shtfferentsialnogo and dopolshtelnyh collectors of transistors connected to the negative supply rail tetany. In Figure 1: e shows the circuit diagram of the device proposed. The device contains a bus 1. The input voltage sources, the differential amplifier 1: 2 on transistors 3 and 4, the current in: 1OK1 receiver 5 on transistors 6 and 7, the source of current 8, source-GGK 9 control BJiCToiHtTo on the same pipe, accumulator cono; 1p 1.O, 1PTO-COPY follower 11, level transducer - stabilizer 12, output bus 13, current source 14, additional transistor 15, buffer cascade 16 on transistors 17 and 18, current transponder 19, resistor 2O, additional transistor 21, resistor 22 and an additional transistor 23. The device operates as follows. In the mode in The control circuit, from source 9, receives a signal to control the inputs of the current switch 5, which opens the transistor 6, which connects the emitters of transistors 3 and 4 of differential amplifier 2 to current source 8. At this moment, the base of transistor 3 voltage is supplied to the signal, which is amplified by the differential amplifier 2 together with the buffer cascade 16 and charges the storage capacitor 10. The negative feedback of the input signal is formed by the passage of the signal from the drive Nogo capacitor 1D; through the source follower 11 and the level translator - zener diode 12 to the output bus 13 and the base of transistor 4. The current of current source 14, flowing through the source follower 11, creates an initial sweep of the gate voltage Istok, which together with the voltage drop on the Zener diode 12 determines the working voltage on the collector of the transistor 8. The operating voltage on the collectors of transistors 3 and 4 is less than the voltage at the source of the repeater 11 on the wind; the voltage across the base-emitter of the transistors 17 and 18 and the voltage drop across the resistors 20 and 22. And for example The resistors 2Q, 22 are chosen so that when the differential amplifier 2 is operated linearly, it is less than the base-emitter junction opening voltage of the transistor 21 and 23. The current reflector 19 included in the collector of the buffer stage 16 increases the loop gain. In the mode of a large signal at the input, the dimple amplifier 2 goes out of the linear mode of operation, i.e. transistor 3 (or 4) closes. All current source 8 current passes through the corresponding circuit. On the resistor 2O (or 22) there will be a voltage drop sufficient to open the additional transistor 21 (or 23). Consequently, a positive current path through transistors 21, and 17 (or 23 and 18) is formed, which accelerates the charge of a positive capacitor 1O, i.e. the voltage across the bases of the transistors 3 and 4 is faster aligned. Differential amplifier 2 enters the linear mode of operation, and transistor 21 (or 23) is, respectively, disconnected

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In the storage mode, source 9 receives a signal at the control inputs of the current switch 5. Transistor 6 closes and transistor 7 opens. Differential amplifier 2, buffer. cascade 16, the reflector is de-energized. The current of the current source 8 passes through the auxiliary transistor 15. On the storage capacitor 1O there remains a voltage equal to the input at this moment of switching. At the same time, the base current of the additional transistor 15 increases, this compensates for the transient on the output bus 13, since the source follower is not covered by the NFB and the output resistance is high. I .-. The boundary caused by the passage of the input signal in the storage mode is reduced by the sequential connection of transistors 3, 4 and 18 between iA and 1 and the storage capacitor 1O. The leakage currents from the capacitor 10 are also reduced, since the reverse currents of the transistors of the current reflector 19 and the transistor 18 of the buffer stage can be chosen the same, which increases the storage time. In the sampling mode, by equalizing the voltage across the collectors of the transistors of the differential amplifier 2, it reduces the Ic mixing error caused by the effect of modulating the width of the base transition of the transistors. At the same time, the error caused by the temperature transient due to the contraction is reduced. Diffusion of dissipated power on the INPUT of the OX transistors 3 and 4. The use of the charging current forcing of a capacitive capacitor 10 reduces the transient time, and therefore, it is possible to reduce the current in the amplifier 2, i.e. will increase, static accuracy. Reducing the switching circuit to one reduces the total capacity and, therefore, the aperture time.

formula. Inventions

A sampling and storage device containing a differential amplifier whose base of the first transistor is connected to the input voltage source bus, the base of the second transistor is connected to the output bus, and sN rrTepbi is connected to the first current source connected to the negative power supply bus through the first transistor, the base of the transistors of the current switch is connected to the buses of the control voltage source, a field effect transistor, the gate of which through

the capacitor is connected to the ground bus, the drain is connected to a separate power supply bus, a second current generator connected to a negative power supply bus by one voltage, resistors and a first transistor whose collector is connected to a positive power supply bus, characterized in that increase in speed, two additional transistors are introduced into it, a buffer cascade on two transistors, a transistor current reflector and a level transducer in the form of a stabagatron, with the output bus connected to the base of the first the transistor, the ecgiter of which is connected to the co-collector of the second transistor of the current switch, the field-effect transistor rod is connected to the bases of the transistors of the buffer cascade and through the level transducer to the output bus, the collector of the first transistor of the buffer cascade is connected to the input current reflector connected to the positive busbar through the transistor. power source, the output bus transistor current reflector is connected to the collector of the second transistor of the buffer stage and to the gate of the field-effect transistor, the emitter of the first transistor The buffer stage is connected through the first resistor to the collector of the first transistor of the differential amplifier and to the emitter of the first additional transistor, whose base is connected to the collector of the first transistor of the differential amplifier, the second transistor of the buffer cascade is connected to the second transistor of the differential amplifier and to the second transistor. the emitter of the second pre-transistor transistor, the base of which is connected to the collector of the second transistor of differential amplification l, and the collectors of the additional transistors are connected to a separate suture power source.

7 9651318

Istochntsi Shfsfmatsii, .2, USSR Copyright Certificate

pryushty into account when examining the application Mi 2807883 / 18-21,

1. US patent No. 3.643.110, cl. H 03 K 17/60, 07.08.79 (protokp. H 03 K 17 / 6O. 1971.T1Sh).

+ fn

Claims (1)

SUMMARY OF THE INVENTION A sampling and storage device comprising a differential amplifier, the base of the first transistor of which is connected to a bus of an input voltage source, the base of a second transistor is connected to an output bus, and emitters are connected through a first transistor of a current switch to a first current source connected to a negative bus of a power source, the base of the transistors of the current switch are connected to the buses of the control voltage source, a field effect transistor, the gate of which through the storage capacitor with union of a ground _br bus Stock - with positive bus power source, a second current generator, one output connected to the negative supply rail, resistors and the first transistor having its collector connected to a positive power supply bus, characterized in that, in order to increase the speed of , it introduced two additional transistors, a buffer cascade on two transistors, a transistor current reflector and a level translator in the form of a zener diode, and the output bus is connected to the base of the first transistor, amy ter of which is connected to the collector of the second transistor current switch FET rod is connected with the bases of transistors of the buffer stage and through the translator level - with an output bus, the collector of the first transistor buffer stage coupled to the input bus transistor! About the current reflector connected to the positive bus of the power supply, the output bus of the transistor reflector is the storage name. In the sampling mode due to the equality of voltage across the collectors of transistors of differential amplifier 2 reduces | This is a mixing error caused by the modulation effect of the width of the base transition of transistors. At the same time, the error caused by the temperature transient due to decreases. differences in power dissipation at the input transistors 3 and 4. The use of boosting the charge current of the storage capacitor 10 reduces the transient time, and therefore can be reduced. current in differential amplifier 2, i.e. increase static accuracy. Reducing the switching goals to one reduces the total capacity and, consequently, the aperture time. current is connected to the collector of the second transistor of the buffer stage and to the gate of the field effect transistor, the emitter of the first transistor of the buffer stage through the first resistor is connected to the collector of the first transistor of the differential amplifier and the emitter of the first additional transistor, the base of which is connected to the collector of the first transistor of the differential amplifier, the emitter of the second transistor of the buffer stage connected through a second resistor to the collector of the second transistor of the differential amplifier and to the emitter in orogo additional transistor, the base of which is connected to the collector of the second transistor of the differential amplifier and the collector of additional transistors are connected to negative bus power source. 7 963131