SU924862A1 - Retrieval and storage device - Google Patents

Description

(5) SAMPLE AND STORAGE DEVICE

I

The invention relates to electronic engineering, and more specifically to electronic switching and measurement technology, and can be used, for example, in the construction of high-speed analog-to-digital converters.

Sampling and storage devices are known that contain a differential transistor cascade, current switches, current sources and a source follower 13.

The disadvantages of these devices are low transmission accuracy and low storage time of the input signal.

The closest to the proposed technical entity is a sampling and storage device containing six bipolar transistors, a MIS transistor, two current sources, a zener diode and a capacitor, the base of the first and the base of the second bipolar transistors, combined emitters

which are connected to the collector of the third bipolar transistor, connected to the input and output buses of the device, respectively, the bases of the third and fourth bipolar transistors, the combined emitters of which are connected to the first power supply bus through the first current source, a bipolar transistor connected to the collector of this transistor, the combined emitters of the fifth and sixth bipolar transistors, the bases of which are combined, are connected to the second power supply bus, to The olfS lecturer of the second bipolar transistor is connected to the gate of the MOS transistor and connected via a capacitor to the common bus, between the source of the MOS transistor, the drain of which is connected to the second bus of the power source, and the first bus of the power source connected in series the zener diode and the second current source, the connection point of which is connected to the output bus of the device 2. A disadvantage of the known device is the low accuracy of the transmission of the input signal. The purpose of the invention is to improve the accuracy of the input signal transmission. The goal is achieved in that a sampling and storage device containing six bipolar transistors, an MIS transistor, two current sources, a zener diode and a capacitor, the base of the first and the base of the second bipolar transistors, whose combined emitters are connected to the third bipolar the transistor, connected to the input and output buses of the device, respectively, the bases of the third and fourth bipolar transistors, the combined emitters of which through the first current source are connected to the first power supply bus, are connected control busbars, the base of the fifth bipolar transistor is connected to the collector of this transistor, the combined emitters of the fifth and sixth bipolar transistors, the bases of which are combined, are connected to the second power supply bus, the collector of the second bipolar transistor is connected to the gate of the MOS transistor and through a capacitor connected to the common bus, between the source of the MOS transistor, the drain of which is connected to the second bus of the power source, and the first bus of the power source, connected in series are the stabilizer and the second The current source, the connection point of which is connected to the output bus of the device, introduces the first and second additional bipolar transistors, the emitter, the base and the collector of the first additional bipolar transistor are connected respectively to the collector of the first bipolar transistor and to the source of the MIS transistor and the fifth collector the bipolar transistor, the emitter, the base and the collector of the second additional bipolar transistor are connected respectively to the collector of the fourth bipolar transistor, with the output bus and with the second power supply bus, the collector of the sixth bipolar transistor is connected to the gate of the MIS transistor.

Claims (2)

of the output bus 17 with respect to the potential of the gate of the transistor 11, when transmitting signals of negative polarity. This is necessary in order to avoid the transistor 2's naxisation. The current source 10 serves as a source follower load and provides an offset between the gate and the transfer source of the drawing. A schematic diagram illustrating an example of a specific implementation of the device is shown. The sampling and storage device contains the first 1, second 2, third 3, fourth 4, fifth 5j sixth 6 bipolar transistors, first 7 and second 8 additional bipolar transistors, first 9 and second 10 current sources, MOS transistor 11, zener diode 12, a capacitor 13. The source of the MIS transistor 11 is connected through a series-connected zener diode 12 and a current source 10 to the first power supply bus, and the drain of this transistor is connected to the second power supply bus 15. The base of the transistor 1 is connected to the input bus 1b, and the base of the transistor 2 is connected to the output bus G /. The bases of transistors 3 and 4 are connected to control buses 18 and 19. Transistors 1 and 2. are connected according to the differential amplifier circuit, transistors 3 and 4 play the role of current switches, and transistors 5 and 6 are connected according to the current reflector circuit. The device operates as follows. In the sampling mode, the control signals are opened to the buses 18 and 19, opening the transistor 3 and closing the transistor A. In this case, the transistor .8 is de-energized and the transistors 1 and 2 of the differential stage are energized. In this mode, the device operates as a normal amplifier with an input differential cascade on transistors 1 and 2, the load of which is a current reflector on transistors 5 and 6, and the current source 9 is connected to the emitter circuit. To reduce the effect of load resistance on the gain of the differential cascade at its output, a source follower is connected to the MPD transistor 11, to the source of which a level transducer - Zener diode 12 is connected, designed to bias the potential resistor 11 equal to the base-emitter voltage of the transistor 7. In storage mode The control buses 18, 19 are given signals that close the transistor 3 and open the transistor. In this case, the transistors 1 and 2 of the differential cascade and the transistors 5 and 6 of the current reflector are de-energized, because the current through the transistor 1 becomes equal to zero. The feedback is disconnected, while the voltage on the capacitor 13 is fixed at the level immediately preceding the transition and the storage mode. Simultaneously with the closing of the transistor 2 and the transistor 7, the transistor 8 opens, which ensures that the current branch from the output bus 17 remains unchanged during the transition from the sampling mode to the storage mode. Therefore, the current flowing through the MIS-transistor 11 does not change and the voltage jump on the output bus 17 when switching to the storage mode is negligible. The positive effect of the proposed device is to increase the accuracy of the input signal transmission and provide bipolar transistors as described above. In the sampling mode, increasing the accuracy of transmission the input signal is provided by the fact that the power dissipated at the collectors of transistors 1 and 2 of the differential stage is equal. This provides equivalent thermal conditions for these transistors and eliminates additional bias voltage, which has a negative effect on the accuracy of the input signal. During the transition from the sampling mode to the storage mode, due to the definitely connected transistor 8, there is practically no voltage jump on the output bus 17, which also leads to an increase in the accuracy of the input signal transmission. The invention The sampling and storage device containing six bipolar transistors, a MOSFET, two current sources, a Zener diode and a capacitor, the base of the first and the base of the second bipolar transistors, the combined emitters of which are connected to the collector of the third bipolar transistor, are connected to the input and The output busbars of the device, respectively, the bases of the third and fourth bipolar transistors, the combined emitters of which are connected to the first power supply bus through the first current source control, the base of the fifth bipolar transistor is connected to the collector of this transistor, the combined emitters of the fifth and sixth bipolar transistors, the bases of which are combined, are connected to the second power supply bus, the collector of the second bipolar transistor is connected to the gate of the MOS transistor and is connected via a capacitor to the common bus, between the source of the MOS transistor, the drain of which is connected to the second bus of the power source, and the first bus of the power source, connected in series are a zener diode and a second source The current, the connection point of which is connected to the output bus of the device, is characterized in that, in order to increase the transmission accuracy of the input signal, the first and second additional bipolar transistors, the emitter, the base and the collector of the first additional bipolar transistor are connected to the collector of the first bipolar transistor, with the source of the MOS transistor and with the collector of the fifth bipolar transistor, the emitter, the base and the collector of the second additional bipolar transistor are connected respectively venno to the collector of the fourth bipolar transistor, with the output bus of the device and a second bus of the power supply, the collector of the sixth bipolar transistor is connected to the gate of the MISFET. Sources of information taken into consideration and examination 1.US. Patent no., Cl. 307-235,1972. 2. USSR Author's Certificate of Application No. 2807883 / 18-21, l. N LZ K 17/60, 1979.