SU942119A1 - Teaching device - Google Patents

Description

(54) DEVICE FOR TRAINING

one

Isophilic matter relates to the field of automation and computer technology, in particular, to training devices, and can be used in the study of computer memory devices.

A device containing a memory block consisting of memory elements, an address and numeric block and allowing the state of the memory elements and the indication of these states is known.

It is also known a device, which contains a memory block consisting of memory elements, is an address and numeric block, and allows one to investigate the physical processes in the memory block while recording and reading information f 2.

The closest to the present invention is a device containing a memory block consisting of memory elements with two address inputs, a bit input and an output each, a common block, a numerical block and a software control unit, the first output of which

connected to the input of the address block, the second output with the second input of the numeric block 3.

The disadvantage of this device is the use in the memory block of non-tunable memory elements, which are closely interconnected, as well as the presence of rigid connections between the memory blocks and a; the digital and numerical blocks, which allows to model the structure

(About a storage device of only one type on the memory elements of the same physical nature and excludes the possibility of changing the configuration of the memory block (the number of memory cells and their size), while the synthesis of the memory block is impossible.

The goal of the acquisition is to expand the didactic possibilities of the device, as well as to increase the effectiveness of training by

20 giving the device the ability to change the structure.

This goal is achieved by the fact that the device containing the memory block, 394 control pulse shaper, the first output of which is connected to (in the driver of the address maker, and the second output - to the first input of the number code generator, is inserted in series the object being studied and the switch, the code distributor and the block of AND-OR elements, the output of which is connected to the second by the input of the number code generator, the first input to the output of the memory unit, and the second input to the second input of the structure changing unit The object, the third output of which is connected to the first input of the memory unit, and the input is connected to the third output of the control pulse generator, the first input of the code distributor is connected to the output of the number code generator, the second input is connected to the fourth output of the object structure change block, and the output with the second input of the memory block, the third input of which through the switch is connected to the output of the address maker. Moreover, the structure change block ig (the object under study contains the structure code generator and the The pulse distributor, whose outputs and the YDSL are the COOT outputs and the input of the unit. FIG. 1 shows the flow diagrams of the proposed device; in fig. 2 is a schematic diagram of the memory element of the memory block. The device contains 1 address shaper, memory block 2, consisting of memory elements 3, 1 | 4 number codes, shaper 5 control pulses, switch 6, code distributor 7, OR block 8, block 9 of the structure of the object under study , consisting, for example, of the generator 1O of the code of knitting and the distributor of 11 pulses. The address and bit inputs and the bit outputs of each element 3 are connected to 1 14, respectively. Shaper 5 is designed to control the generation and output of addresses and the number | forming a sequence of unit control signals depending on the structure of the simulated storage device. Element 3 is implemented with Kfig. 2) Hai is based on a known trigger 15 with complex input logic, which has two S-connected by AND, one R-inputs synchronized by C1, D-input synchronized by C2, and contains the first input element AND 16, the inputs of which are connected bus 12 and are the input inputs of element 3, and the output is connected to the y and C1 inputs of the trigger 5, the second two-input element AND 17, the first input of which is connected to the input and the trigger 15, the second input to the output of the first element I, the output is connected to the bus 14 of the element 3. The bus 13 of the azd dny element is connected to the D- and wrench 9-inputs trigger 15, the second, R and C2 inputs of the trigger 15 form the control input of the element 3 and are connected to the bus 18-2O, respectively, connected to the second output of lock 9. During the synthesis of the memory block of the 3D type, the address buses X of the block 2 are formed by switching between one of the address inputs 12 of several elements 3, and the address buses Y by switching other inputs 12 between themselves. Formed buses X and Y are connected by switch 6 to the driver 1. During the synthesis of a memory block of a storage device of type 2 J) target area tol on one of the coordinates. Bit input and output buses of memory block 2 are formed by a set of busbars 13 and 14, respectively, of the required elements 3. Distributor 7 and block 8 in accordance with a given type of structure provide the required connections of the bit inputs and outputs of each element 3 to the output and the first input driver 4, respectively. The switch 6, the valve 7 and the block 8 are controlled by the signals of the distributor 11, which, in turn, is controlled by the driver Y. The configuration (the number of memory cells and their size) is synthesized block of memory is limited by the relation where m is the number of memory cells: U - a width of the memory cells} N - total number of elements 3. For a given value of N w limited number of outputs and address unit synthesized depends on the structure; memory device, and the value of q is limited by the number of second inputs of the numeric block. The proposed circuit of elements 3 allows the storage units to be removed from memory devices assembled on elements with destruction of information when reading, for example, ferrite cores with a rectangular hysteresis loop, and elements that are not destroyed during connection, for example, on thin magnetic films. For this, a change in the mode of operation of the accumulator elements is performed by a block of a change in the structure of the object being studied.

In the Read with Destruction mode after writing information from some cell of the memory block to the numeric block, the trigger of this cell is stored on the bus 19sggs. In this mode, information is written (restored) to the memory cell via the bus 13 elements 3 using their S - inputs, for which the control signal of the distributor 11 is fed through bus 18 to the second 9 inputs of all the flip-flops 15. Using the S-input to record information in this mode is determined by the need to simulate these storage elements, the principles of which allow by producing them record only Koxia unit.

In the Read without destroying mode, the control signal of the distributor 11 is not fed through the bus 18, but through the bus 20, ensuring the recording of new information without erasing the old one by using the B input of the trigger 15. The device consists of the front panel and the electrical circuit. The front panel shows a block diagram of the device and contains all the sockets, device controls and display elements. The device operates as follows in accordance with the option of the task, the student sets on the sensors of the former 1O conditional numbers of the type of structure, the way the memory element is functioning, and the configuration of the memory block. In accordance with these numbers, the distributor 11 outputs the combination of signals to the switch 6, the distributor 7 and the block 8, which provide the specified commutation of the inputs and outputs of the memory elements 3. In the imaging unit 5, the learner forms the required sequence of signals and, changing the address and number, writes information in memory block 2 and after; from 1c, its reading. Monitoring the correctness of the actions of the trainee

This is done by comparing the information read and read.

The proposed device with advanced funhgonalnymi opportunities

allows you to simulate the structure of the storage devices of types 2D and 31, made on the memory with the destruction of information when reading and without destroying it, to synthesize the memory block

| For these structures, different csnfuggurations, which, by increasing the number of job options, contributes to the individualization of information and enhances its effectiveness.

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Claims (2)

1. A training device containing a memory block that generates control pulses, the first output of which is connected to the input of the address generator, and the second output - with the first input of a number code generator, characterized in that, in order to expand the didactic capabilities of the device, it contains the nose; the unit of change of the structure of the object being studied and the switchboard, the code distributor and the I-LLI element block whose output is connected to the second input of the number code generator, the first input to the memory block output, and the second shsod with BTOpbnvf output of the block for changing the structure of the object being studied, the third output of which is connected to the first input of the memory block, and the input to the third output of the control pulse generator, the first input of the code distributor is connected to the output of the number code generator, the second input is with the fourth the output of the unit changes the structure of the object being studied, and the output - with the second input of the memory unit, the third input of which is connected via the switch to the output of the FS) address world. 2. The device according to claim 1, wherein the unit for changing the structure of the object to be studied contains in series a structure code generator and a pulse distributor, the output and input of which are, respectively, the outputs and input of the block. Sources of information taken into account in the examination 1. UK Patent No. 1341843, cl. SLEE B 5/00,, shublik. 1973. 2.Stroganov P.P. Computational i discrete-action devices. Ed. 794 1198 Le vngradskogo Polytechnic Institute-3, Digital computers, Mulberry named Kalinin, 1971, p. 105 -Ed. Solovyov G.I. M., Atomizdat, 118.19.77, p. 213-220 (prototype).