SU942020A1 - Microprogram control device - Google Patents

Description

one

The invention relates to computing and is intended for operation in a central processor of high-speed computers with command execution level NM (n is a finite number of command execution combination levels).

A device for microprogram control is known, containing groups of elements AND / OR, NOT, blocks of the main memory of the microprograms. From the main and additional modules of the microprogram through the elements AND, OR the microinstruction is selected on the register of the microinstructions. The performance increase is achieved by the combined execution of the last micro-command from the sequence of micro-commands required to execute the system command, with reference to the first micro-command of the sequence. next system command 1.

The disadvantage of such a device is that it provides only a two-level combination. This does not allow to achieve the high processing speed of commands required in large computing systems.

The closest to the one proposed is a firmware device

a lot of control designed to work as part of a processor with three levels of combining commands. This device; contains groups of elements AND, OR, NOT, blocks of main and additional memory microprograms, the first and second address registers, the operation code registers of the first command and the second commands, registers

10 main and additional microinstructions and a node modifying the address of a microcommand. Of the two blocks of the main and additional memory of the microprogram, two micro15 commands are synchronously selected. The actions dependent on the operation code of the system command are controlled by the main micro-command, and the actions depending on the execution cycle of the command are controlled by the micro-command selected from the auxiliary firmware memory. The micro-addressing system provides access to main or additional microprogram memory without loss of time 2.

The disadvantages of the known device are that in the additional memory of the firmware it is necessary to have its own microcommand image for each case of executing commands (with combining the execution of three commands, two commands and without combining). This significantly increases the capacity of the firmware memory and makes it difficult to use this software. It is not advisable to use this device (in a central process box with more than three command execution levels, KipoMe can not expand the number of commands executed without increasing the amount of firmware memory , hardware volume of the firmware control device and the processor. The purpose of the picture is to reduce the hardware and simplify the firmware for the processor with the amount of combining more than three. The goal is achieved by the fact that the firmware control device containing the microinstructor address switch, the microprogram memory, the standalone memory, the microinstructor address register, the 1ND microc register, and the first input of the address switch. The second and third inputs of the address switch are connected to the outputs of the first | And second sections of the microinstruction register, respectively, and the inputs of the first and second sections of the microcoman register are connected respectively to the output The first and second sections of the microprogram memory, whose inputs are connected respectively to the outputs of the first and second sections of the micro-command address register, whose inputs are connected to the first and second outputs of the address switch, respectively, have been entered a priority block, an encoder, addresses of the first micro-command, 3.4, .-. n section of the microinstruction address register, 3,4 ... p. of the microinstructions memory section, 3,4, ... n section of the microinstructions register, where the inputs of the priority block are the requests of the procedures of the device, and the output of the priority block is connected to The fourth input of the switch of the address, the fifth input of which is connected to the output of the encoder of the address of the first microcommand, the sixth input to the output of the first section of the constant memory, the input 1 of the sections of which are connected to the group n of inputs of the device operation, and the input of the first section connected to the input of the encoder, outputs the memory of the constants are with the outputs of the device constants, 3,4, ... n the outputs of the switch are connected respectively 5 to inputs 3,4, ... n sections of the register of the microinstruction address, the outputs of which are connected respectively to the inputs 3,4, ... The i sections of the microprogram memory whose outputs are connected respectively to the inputs 3, 4 .... n sections of the microcommand register, the outputs of which are connected respectively to the group of inputs of the switch and are the outputs of the microcommands of the device. Figure 1 presents the block diagram of the proposed device; in Fig.2, the composition of the microcommand. The device consists of memory 1 of constants, block 2; priority ,, encoder 3 addresses of the first microcommand, switch 4 addresses of the microinstructions, register 5 addresses of microcommands, memory 6 of the microprograms, register 7 of LOTs of the commands, inputs 8 requests of the procedures of the device, inputs of the 9th address constants of procedures, inputs of 10 operation codes. The device is intended for processing commands such as those received in the EC computer, recovery procedures for control, interrupt handling, timer and console operations. Consider the operation of the proposed device, limiting it to four levels of Command Combination, on the example of executing the command of the PX format. A PX format command (for example, a fixed point addition) is executed in the processor in eight machine cycles (each of which is performed at a certain level of registration): TO is the cycle of operation of the priority 2 of servicing requests to the processor to perform recovery procedures for monitoring, processing interrupt, console (service) operation, timer operation or command. T1 is the tact of fetching a command from the command word buffer and decrypting the command. T2 - the tact of address modification. In this cycle, the address of the destination in the main memory is modified. The types of actions performed in this tact are four. These four types of actions are initiated by circuit orders obtained on the basis of the command operation code on the encoder 3, the addresses of the first microcommand in T1. TK is an address translation clock. In the TK cycle, the logical address is converted to an absolute if the forwarding mode is set and a request is sent to the buffer (main) memory. i. T4 is the operation cycle of the buffer memory. T5 is a clock for receiving operands from the buffer (main) memory and from the processor local memory and transferring them to the operating device. T6 - tact operation of the operating device. T7 is the clock of recording the result of the operation in the local memory of the processor. Suppose that the cycles of maintenance, T1 are zero at the zero level T2 and TZ at the first level, T4 and T5 at the second level, Tb and T7 at the third level of command execution combining. The microoperations of the TO cycles, T1 are controlled schematically, all other firmware. According to the number of levels managed by the micro-software, the memory of 1 constants, the register of 5 addresses of micro-instructions, the memory of microprograms and the register of 7 micro-instructions are divided into the same number of sections. The microcommands controlling the actions of each at their own level are looped into the corresponding section of the register of 7 microcommands. All microcommands consist of the floor of the practical part (figure 2). At each level, different units of processor equipment operate, which makes it possible not to duplicate the executive fields of microcommands of different levels. The exception is only the control field of the local memory of the processor, which can be accessed at each level in different half-cycles. Conflicts on accessing the local memory are resolved schematically in cycles of maintenance and T1. In the combined mode of command filling, four commands are executed simultaneously at the levels. If more than eight clock cycles are required to execute a command, then at T2 of this command, the input of the priority circuit 2 to the microcommand address switch is locked, and the processor equipment is monopolized by this command. The lock is released by one of the microcommands of this command, after which the combined execution of commands is restored. The formation of the address of each of the following microcommands is done in one of three ways: using an unconditional branch; using a conditional transition and using the transition in the register. In case of unconditional transition, the address of the next micro-command is in the 14-field of the word of the micro-command (Fig. 2). In the conditional transition, the address of the next microcommand is formed from the contents of field 14 (FIG. 2) and the condition of the transition reduced to the state of the bits of register 5 of the microcommand address. When navigating through the register, the address of the next micro-command is either located on a certain register (unconditional transition through the register), or is formed from the contents of such a register and the transition condition (conditional transition through the register). The firmware memory number 6 of the microprogram 6 to which the next microinstruction should be accessed is placed in field 12 (FIG. 2) of the microinstruction. This same field controls the movement of command information from level to level. The presence of a conditional transition and a case transition is identified by field 13 (FIG. 2}. The contents of fields 12, 13, and 14 of the micro-command are sent to the switch 4 of the micro-instructions. The address to the first section of the microprogram memory b begins with the first micro-instruction in T2. according to the number of different tacts, the TOR is divided into sixteen groups. Since the first microcommand of each command is executed in the tactical cycle, all the first microcommands of all the commands are stored in the memory of the microprograms into a separate zone of sixteen words whose address is The four-bit address inside the zone is formed schematically on the encoder 3 addresses in the T2 cycle based on the first-level opcode received via the 10 opcode lines. The same opcode turns into the first section of the 1 constant memory following the address constant microinstruction} .Inframes 1 constants are stored signs, dependent on pt operation codes, executed sx commands and necessary when executing them, for example, indication of the privilege of the command being executed, length of the operands, sign of command execution in the unes Hinnom mode, etc. The access to the sections of the memory 1 of the constants occurs according to the operation code of the command of the corresponding level. In the TK cycle, simultaneously with the execution of the first microcommand, a second microcommand is sampled at the address formed at the input of the memory 1 of the constants. Subsequent micro-instructions are selected by addresses generated by one of the above methods. The development of the first micro-instructions for processing such procedures as interruption, console and timer operations, recovery by control occurs by switching the register to the address constants of the first micro-instructions generated in the processor nodes and entering the 9 address constants of the procedures into the switch of 4 micro-addresses of the micro-commands under control of signals generated by priority block 2 based on requests received via lines of 8 device request inputs. When organizing transitions from level to level with the combined execution of commands, guiding the principle of conceptualization of commands, the following transitions are allowed: from each of the levels to the next, previous one, to the same and the first. In particular cases, not all possible transitions are necessary. For example, for the case n 4 provides with an optional transition from the third to the second level .; In general, there is no need to divide the memory of the firmware into equal sections by volume. In the case of rii: 4r, for example, the first section of the firmware is twice the second and third sections. This also applies to the memory 1 of constants and to the register of 7 micro-instructions and to the register of 5 addresses of micro-instructions. Thus, the proposed technical solution provides a significant reduction in the required amount of microprogram memory in comparison with the prototype. Due to the fact that when the microprogram memory is divided into sections, each of which controls the actions performed at a certain level, there is no need to duplicate the control fields in the microinstructions and the number of microinstructions depending on possible combinations of combinations in the performance of operations. We quantify the decrease in the amount of firmware memory in the compared versions. . Imagine the entire amount of the required microprogram memory (V) in the form of the sum of two components: the part of the microprogram memory () that controls the combined actions in the process, the amount of which depends on the organization of the microprogram control and the number of combination levels, and Firmware memory (Vpons-k) which controls non-compatible actions and does not depend on the number of levels and the structure of the firmware control device. V Vvar + (1) The length of one microcommand will be conditionally represented as r ЕИ + Bq, (2) where ly is the total length of the fields defining the actions performed by this microcommand, processor nodes (the executive part), the value 2 depends from the organization of memory 1 and 1 program and the number of combining levels (n) managed by microprogram 20; the total length of the fields constituting mainly the address part of the microcommand that is independent of the version of the microprogram memory structure and the combining levels. When comparing the two options for organizing the firmware control devices (1 - the proposed technical solution, 2 - 2), the required assumptions of the microprogram memory are based on the following assumptions: a) in both the firmware versions the same actions as the combined ones are controlled, and non-interchangeable, with V, gt Vcon9t. b) the number of functionally different microcommands that determine the operation of all processor nodes is the same (for a given n), regardless of whether the memory of the microprograms is partitioned by levels of alignments. or not, and is Q- & CV,., where q. - the number of microinstructions executed at the i-oM level; c) the length of the address part of the microinstructions is the same for both variants of the ГУ 2tW 2с; (4) d) since Q con9i is the length of the executive part of the microcommands of all levels for the first variant, then (assuming that all B are equal} (JUe. (5) e) because in the second variant B depends on the possible types of combined operations (0 , 1n, simultaneously executed commands) for each of the types must be provided with its own image of microcommands for each of the actions, the total number of microcommands for the second variant is: n SCH nQ. Hence v}; | Vconst + + a) - Vcotis-t +, + Zq) .nQ (nye) Q ()) Вд y -L consV - 1l "" YY1 / 5 / f) n 50nSt ieM- C,) M (G 4onst "() For the EC command system and if The features of the firmware-controlled levels of combining the numerical ratios between 2j, 2a, 4; onst are approximately as follows: / 2v,: 2a 3: 5 (10) 4, Q (2n + Sc,) (11) Substituted in (9), and relations (1C) and (11), we obtain 3.125 (12) The proposed technical solution is also a universal structure (i.e., independent of the number of commands to be combined) capable of expanding the composition of executable commands

(for example, when introducing special processors into the system), which is achieved by the presence of memory 1 of constants. In the proposed solution, microprogramming is facilitated due to the absence of the need to take into account in the microprograms of the variants of execution of commands with and without overlap.

In addition, with the increase in the number of levels of combining and the composition of the commands being executed, the microscopic memory of the microprograms does not significantly increase the time; g sampling of the microcommand from the microprogram memory / which ultimately is an important parameter when the processor is working.

Claims (2)

1. US Patent 3,800,293, Cl. 340-172.5, otlib. 1974. 2. Authors certificate of the USSR 561964, cl. G 06 F 9/22, 1977 (prototype). ilil m T ySHGG I fII I iL uH I I-ITi. , ,eleven with nxicz 9. / ug Jj Zj